1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include "opt_cpu.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcib_private.h> 44 #include <isa/isavar.h> 45 #ifdef CPU_ELAN 46 #include <machine/md_var.h> 47 #endif 48 #include <x86/legacyvar.h> 49 #include <machine/pci_cfgreg.h> 50 #include <machine/resource.h> 51 52 #include "pcib_if.h" 53 54 int 55 legacy_pcib_maxslots(device_t dev) 56 { 57 return 31; 58 } 59 60 /* read configuration space register */ 61 62 uint32_t 63 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 64 u_int reg, int bytes) 65 { 66 return(pci_cfgregread(0, bus, slot, func, reg, bytes)); 67 } 68 69 /* write configuration space register */ 70 71 void 72 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 73 u_int reg, uint32_t data, int bytes) 74 { 75 pci_cfgregwrite(0, bus, slot, func, reg, data, bytes); 76 } 77 78 /* route interrupt */ 79 80 static int 81 legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin) 82 { 83 84 #ifdef __HAVE_PIR 85 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev), 86 pci_get_function(dev), pin)); 87 #else 88 /* No routing possible */ 89 return (PCI_INVALID_IRQ); 90 #endif 91 } 92 93 /* Pass MSI requests up to the nexus. */ 94 95 int 96 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, 97 int *irqs) 98 { 99 device_t bus; 100 101 bus = device_get_parent(pcib); 102 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 103 irqs)); 104 } 105 106 int 107 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 108 { 109 device_t bus; 110 111 bus = device_get_parent(pcib); 112 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 113 } 114 115 int 116 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 117 uint32_t *data) 118 { 119 device_t bus, hostb; 120 int error, func, slot; 121 122 bus = device_get_parent(pcib); 123 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 124 if (error) 125 return (error); 126 127 slot = legacy_get_pcislot(pcib); 128 func = legacy_get_pcifunc(pcib); 129 if (slot == -1 || func == -1) 130 return (0); 131 hostb = pci_find_bsf(0, slot, func); 132 KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__, 133 slot, func)); 134 pci_ht_map_msi(hostb, *addr); 135 return (0); 136 } 137 138 static const char * 139 legacy_pcib_is_host_bridge(int bus, int slot, int func, 140 uint32_t id, uint8_t class, uint8_t subclass, 141 uint8_t *busnum) 142 { 143 #ifdef __i386__ 144 const char *s = NULL; 145 static uint8_t pxb[4]; /* hack for 450nx */ 146 147 *busnum = 0; 148 149 switch (id) { 150 case 0x12258086: 151 s = "Intel 824?? host to PCI bridge"; 152 /* XXX This is a guess */ 153 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */ 154 *busnum = bus; 155 break; 156 case 0x71208086: 157 s = "Intel 82810 (i810 GMCH) Host To Hub bridge"; 158 break; 159 case 0x71228086: 160 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge"; 161 break; 162 case 0x71248086: 163 s = "Intel 82810E (i810E GMCH) Host To Hub bridge"; 164 break; 165 case 0x11308086: 166 s = "Intel 82815 (i815 GMCH) Host To Hub bridge"; 167 break; 168 case 0x71808086: 169 s = "Intel 82443LX (440 LX) host to PCI bridge"; 170 break; 171 case 0x71908086: 172 s = "Intel 82443BX (440 BX) host to PCI bridge"; 173 break; 174 case 0x71928086: 175 s = "Intel 82443BX host to PCI bridge (AGP disabled)"; 176 break; 177 case 0x71948086: 178 s = "Intel 82443MX host to PCI bridge"; 179 break; 180 case 0x71a08086: 181 s = "Intel 82443GX host to PCI bridge"; 182 break; 183 case 0x71a18086: 184 s = "Intel 82443GX host to AGP bridge"; 185 break; 186 case 0x71a28086: 187 s = "Intel 82443GX host to PCI bridge (AGP disabled)"; 188 break; 189 case 0x84c48086: 190 s = "Intel 82454KX/GX (Orion) host to PCI bridge"; 191 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1); 192 break; 193 case 0x84ca8086: 194 /* 195 * For the 450nx chipset, there is a whole bundle of 196 * things pretending to be host bridges. The MIOC will 197 * be seen first and isn't really a pci bridge (the 198 * actual buses are attached to the PXB's). We need to 199 * read the registers of the MIOC to figure out the 200 * bus numbers for the PXB channels. 201 * 202 * Since the MIOC doesn't have a pci bus attached, we 203 * pretend it wasn't there. 204 */ 205 pxb[0] = legacy_pcib_read_config(0, bus, slot, func, 206 0xd0, 1); /* BUSNO[0] */ 207 pxb[1] = legacy_pcib_read_config(0, bus, slot, func, 208 0xd1, 1) + 1; /* SUBA[0]+1 */ 209 pxb[2] = legacy_pcib_read_config(0, bus, slot, func, 210 0xd3, 1); /* BUSNO[1] */ 211 pxb[3] = legacy_pcib_read_config(0, bus, slot, func, 212 0xd4, 1) + 1; /* SUBA[1]+1 */ 213 return NULL; 214 case 0x84cb8086: 215 switch (slot) { 216 case 0x12: 217 s = "Intel 82454NX PXB#0, Bus#A"; 218 *busnum = pxb[0]; 219 break; 220 case 0x13: 221 s = "Intel 82454NX PXB#0, Bus#B"; 222 *busnum = pxb[1]; 223 break; 224 case 0x14: 225 s = "Intel 82454NX PXB#1, Bus#A"; 226 *busnum = pxb[2]; 227 break; 228 case 0x15: 229 s = "Intel 82454NX PXB#1, Bus#B"; 230 *busnum = pxb[3]; 231 break; 232 } 233 break; 234 case 0x1A308086: 235 s = "Intel 82845 Host to PCI bridge"; 236 break; 237 238 /* AMD -- vendor 0x1022 */ 239 case 0x30001022: 240 s = "AMD Elan SC520 host to PCI bridge"; 241 #ifdef CPU_ELAN 242 init_AMD_Elan_sc520(); 243 #else 244 printf( 245 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n"); 246 #endif 247 break; 248 case 0x70061022: 249 s = "AMD-751 host to PCI bridge"; 250 break; 251 case 0x700e1022: 252 s = "AMD-761 host to PCI bridge"; 253 break; 254 255 /* SiS -- vendor 0x1039 */ 256 case 0x04961039: 257 s = "SiS 85c496"; 258 break; 259 case 0x04061039: 260 s = "SiS 85c501"; 261 break; 262 case 0x06011039: 263 s = "SiS 85c601"; 264 break; 265 case 0x55911039: 266 s = "SiS 5591 host to PCI bridge"; 267 break; 268 case 0x00011039: 269 s = "SiS 5591 host to AGP bridge"; 270 break; 271 272 /* VLSI -- vendor 0x1004 */ 273 case 0x00051004: 274 s = "VLSI 82C592 Host to PCI bridge"; 275 break; 276 277 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */ 278 /* totally. Please let me know if anything wrong. -F */ 279 /* XXX need info on the MVP3 -- any takers? */ 280 case 0x05981106: 281 s = "VIA 82C598MVP (Apollo MVP3) host bridge"; 282 break; 283 284 /* AcerLabs -- vendor 0x10b9 */ 285 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */ 286 /* id is '10b9" but the register always shows "10b9". -Foxfair */ 287 case 0x154110b9: 288 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge"; 289 break; 290 291 /* OPTi -- vendor 0x1045 */ 292 case 0xc7011045: 293 s = "OPTi 82C700 host to PCI bridge"; 294 break; 295 case 0xc8221045: 296 s = "OPTi 82C822 host to PCI Bridge"; 297 break; 298 299 /* ServerWorks -- vendor 0x1166 */ 300 case 0x00051166: 301 s = "ServerWorks NB6536 2.0HE host to PCI bridge"; 302 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 303 break; 304 305 case 0x00061166: 306 /* FALLTHROUGH */ 307 case 0x00081166: 308 /* FALLTHROUGH */ 309 case 0x02011166: 310 /* FALLTHROUGH */ 311 case 0x010f1014: /* IBM re-badged ServerWorks chipset */ 312 s = "ServerWorks host to PCI bridge"; 313 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 314 break; 315 316 case 0x00091166: 317 s = "ServerWorks NB6635 3.0LE host to PCI bridge"; 318 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 319 break; 320 321 case 0x00101166: 322 s = "ServerWorks CIOB30 host to PCI bridge"; 323 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 324 break; 325 326 case 0x00111166: 327 /* FALLTHROUGH */ 328 case 0x03021014: /* IBM re-badged ServerWorks chipset */ 329 s = "ServerWorks CMIC-HE host to PCI-X bridge"; 330 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 331 break; 332 333 /* XXX unknown chipset, but working */ 334 case 0x00171166: 335 /* FALLTHROUGH */ 336 case 0x01011166: 337 case 0x01101166: 338 case 0x02251166: 339 s = "ServerWorks host to PCI bridge(unknown chipset)"; 340 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1); 341 break; 342 343 /* Compaq/HP -- vendor 0x0e11 */ 344 case 0x60100e11: 345 s = "Compaq/HP Model 6010 HotPlug PCI Bridge"; 346 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1); 347 break; 348 349 /* Integrated Micro Solutions -- vendor 0x10e0 */ 350 case 0x884910e0: 351 s = "Integrated Micro Solutions VL Bridge"; 352 break; 353 354 default: 355 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) 356 s = "Host to PCI bridge"; 357 break; 358 } 359 360 return s; 361 #else 362 const char *s = NULL; 363 364 *busnum = 0; 365 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST) 366 s = "Host to PCI bridge"; 367 return s; 368 #endif 369 } 370 371 /* 372 * Scan the first pci bus for host-pci bridges and add pcib instances 373 * to the nexus for each bridge. 374 */ 375 static void 376 legacy_pcib_identify(driver_t *driver, device_t parent) 377 { 378 int bus, slot, func; 379 uint8_t hdrtype; 380 int found = 0; 381 int pcifunchigh; 382 int found824xx = 0; 383 int found_orion = 0; 384 device_t child; 385 devclass_t pci_devclass; 386 387 if (pci_cfgregopen() == 0) 388 return; 389 /* 390 * Check to see if we haven't already had a PCI bus added 391 * via some other means. If we have, bail since otherwise 392 * we're going to end up duplicating it. 393 */ 394 if ((pci_devclass = devclass_find("pci")) && 395 devclass_get_device(pci_devclass, 0)) 396 return; 397 398 bus = 0; 399 retry: 400 for (slot = 0; slot <= PCI_SLOTMAX; slot++) { 401 func = 0; 402 hdrtype = legacy_pcib_read_config(0, bus, slot, func, 403 PCIR_HDRTYPE, 1); 404 /* 405 * When enumerating bus devices, the standard says that 406 * one should check the header type and ignore the slots whose 407 * header types that the software doesn't know about. We use 408 * this to filter out devices. 409 */ 410 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 411 continue; 412 if ((hdrtype & PCIM_MFDEV) && 413 (!found_orion || hdrtype != 0xff)) 414 pcifunchigh = PCI_FUNCMAX; 415 else 416 pcifunchigh = 0; 417 for (func = 0; func <= pcifunchigh; func++) { 418 /* 419 * Read the IDs and class from the device. 420 */ 421 uint32_t id; 422 uint8_t class, subclass, busnum; 423 const char *s; 424 device_t *devs; 425 int ndevs, i; 426 427 id = legacy_pcib_read_config(0, bus, slot, func, 428 PCIR_DEVVENDOR, 4); 429 if (id == -1) 430 continue; 431 class = legacy_pcib_read_config(0, bus, slot, func, 432 PCIR_CLASS, 1); 433 subclass = legacy_pcib_read_config(0, bus, slot, func, 434 PCIR_SUBCLASS, 1); 435 436 s = legacy_pcib_is_host_bridge(bus, slot, func, 437 id, class, subclass, 438 &busnum); 439 if (s == NULL) 440 continue; 441 442 /* 443 * Check to see if the physical bus has already 444 * been seen. Eg: hybrid 32 and 64 bit host 445 * bridges to the same logical bus. 446 */ 447 if (device_get_children(parent, &devs, &ndevs) == 0) { 448 for (i = 0; s != NULL && i < ndevs; i++) { 449 if (strcmp(device_get_name(devs[i]), 450 "pcib") != 0) 451 continue; 452 if (legacy_get_pcibus(devs[i]) == busnum) 453 s = NULL; 454 } 455 free(devs, M_TEMP); 456 } 457 458 if (s == NULL) 459 continue; 460 /* 461 * Add at priority 100 to make sure we 462 * go after any motherboard resources 463 */ 464 child = BUS_ADD_CHILD(parent, 100, 465 "pcib", busnum); 466 device_set_desc(child, s); 467 legacy_set_pcibus(child, busnum); 468 legacy_set_pcislot(child, slot); 469 legacy_set_pcifunc(child, func); 470 471 found = 1; 472 if (id == 0x12258086) 473 found824xx = 1; 474 if (id == 0x84c48086) 475 found_orion = 1; 476 } 477 } 478 if (found824xx && bus == 0) { 479 bus++; 480 goto retry; 481 } 482 483 /* 484 * Make sure we add at least one bridge since some old 485 * hardware doesn't actually have a host-pci bridge device. 486 * Note that pci_cfgregopen() thinks we have PCI devices.. 487 */ 488 if (!found) { 489 #ifndef NO_LEGACY_PCIB 490 if (bootverbose) 491 printf( 492 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n"); 493 child = BUS_ADD_CHILD(parent, 100, "pcib", 0); 494 legacy_set_pcibus(child, 0); 495 #endif 496 } 497 } 498 499 static int 500 legacy_pcib_probe(device_t dev) 501 { 502 503 if (pci_cfgregopen() == 0) 504 return ENXIO; 505 return -100; 506 } 507 508 static int 509 legacy_pcib_attach(device_t dev) 510 { 511 #ifdef __HAVE_PIR 512 device_t pir; 513 int bus; 514 515 bus = pcib_get_bus(dev); 516 /* 517 * Look for a PCI BIOS interrupt routing table as that will be 518 * our method of routing interrupts if we have one. 519 */ 520 if (pci_pir_probe(bus, 0)) { 521 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0); 522 if (pir != NULL) 523 device_probe_and_attach(pir); 524 } 525 #endif 526 device_add_child(dev, "pci", DEVICE_UNIT_ANY); 527 return bus_generic_attach(dev); 528 } 529 530 int 531 legacy_pcib_read_ivar(device_t dev, device_t child, int which, 532 uintptr_t *result) 533 { 534 535 switch (which) { 536 case PCIB_IVAR_DOMAIN: 537 *result = 0; 538 return 0; 539 case PCIB_IVAR_BUS: 540 *result = legacy_get_pcibus(dev); 541 return 0; 542 } 543 return ENOENT; 544 } 545 546 int 547 legacy_pcib_write_ivar(device_t dev, device_t child, int which, 548 uintptr_t value) 549 { 550 551 switch (which) { 552 case PCIB_IVAR_DOMAIN: 553 return EINVAL; 554 case PCIB_IVAR_BUS: 555 legacy_set_pcibus(dev, value); 556 return 0; 557 } 558 return ENOENT; 559 } 560 561 /* 562 * Helper routine for x86 Host-PCI bridge driver resource allocation. 563 * This is used to adjust the start address of wildcard allocation 564 * requests to avoid low addresses that are known to be problematic. 565 * 566 * If no memory preference is given, use upper 32MB slot most BIOSes 567 * use for their memory window. This is typically only used on older 568 * laptops that don't have PCI buses behind a PCI bridge, so assuming 569 * > 32MB is likely OK. 570 * 571 * However, this can cause problems for other chipsets, so we make 572 * this tunable by hw.pci.host_mem_start. 573 */ 574 SYSCTL_DECL(_hw_pci); 575 576 static unsigned long host_mem_start = 0x80000000; 577 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start, 578 0, "Limit the host bridge memory to being above this address."); 579 580 rman_res_t 581 hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count) 582 { 583 584 if (start + count - 1 != end) { 585 if (type == SYS_RES_MEMORY && start < host_mem_start) 586 start = host_mem_start; 587 if (type == SYS_RES_IOPORT && start < 0x1000) 588 start = 0x1000; 589 } 590 return (start); 591 } 592 593 struct resource * 594 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 595 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 596 { 597 598 if (type == PCI_RES_BUS) 599 return (pci_domain_alloc_bus(0, child, rid, start, end, count, 600 flags)); 601 start = hostb_alloc_start(type, start, end, count); 602 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 603 count, flags)); 604 } 605 606 int 607 legacy_pcib_adjust_resource(device_t dev, device_t child, 608 struct resource *r, rman_res_t start, rman_res_t end) 609 { 610 611 if (rman_get_type(r) == PCI_RES_BUS) 612 return (pci_domain_adjust_bus(0, child, r, start, end)); 613 return (bus_generic_adjust_resource(dev, child, r, start, end)); 614 } 615 616 int 617 legacy_pcib_release_resource(device_t dev, device_t child, struct resource *r) 618 { 619 620 if (rman_get_type(r) == PCI_RES_BUS) 621 return (pci_domain_release_bus(0, child, r)); 622 return (bus_generic_release_resource(dev, child, r)); 623 } 624 625 int 626 legacy_pcib_activate_resource(device_t dev, device_t child, struct resource *r) 627 { 628 if (rman_get_type(r) == PCI_RES_BUS) 629 return (pci_domain_activate_bus(0, child, r)); 630 return (bus_generic_activate_resource(dev, child, r)); 631 } 632 633 int 634 legacy_pcib_deactivate_resource(device_t dev, device_t child, 635 struct resource *r) 636 { 637 if (rman_get_type(r) == PCI_RES_BUS) 638 return (pci_domain_deactivate_bus(0, child, r)); 639 return (bus_generic_deactivate_resource(dev, child, r)); 640 } 641 642 static device_method_t legacy_pcib_methods[] = { 643 /* Device interface */ 644 DEVMETHOD(device_identify, legacy_pcib_identify), 645 DEVMETHOD(device_probe, legacy_pcib_probe), 646 DEVMETHOD(device_attach, legacy_pcib_attach), 647 DEVMETHOD(device_shutdown, bus_generic_shutdown), 648 DEVMETHOD(device_suspend, bus_generic_suspend), 649 DEVMETHOD(device_resume, bus_generic_resume), 650 651 /* Bus interface */ 652 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar), 653 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar), 654 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource), 655 DEVMETHOD(bus_adjust_resource, legacy_pcib_adjust_resource), 656 DEVMETHOD(bus_release_resource, legacy_pcib_release_resource), 657 DEVMETHOD(bus_activate_resource, legacy_pcib_activate_resource), 658 DEVMETHOD(bus_deactivate_resource, legacy_pcib_deactivate_resource), 659 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 660 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 661 662 /* pcib interface */ 663 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots), 664 DEVMETHOD(pcib_read_config, legacy_pcib_read_config), 665 DEVMETHOD(pcib_write_config, legacy_pcib_write_config), 666 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), 667 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi), 668 DEVMETHOD(pcib_release_msi, pcib_release_msi), 669 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix), 670 DEVMETHOD(pcib_release_msix, pcib_release_msix), 671 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi), 672 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 673 674 DEVMETHOD_END 675 }; 676 677 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1); 678 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, 0, 0); 679 680 /* 681 * Install placeholder to claim the resources owned by the 682 * PCI bus interface. This could be used to extract the 683 * config space registers in the extreme case where the PnP 684 * ID is available and the PCI BIOS isn't, but for now we just 685 * eat the PnP ID and do nothing else. 686 * 687 * we silence this probe, as it will generally confuse people. 688 */ 689 static struct isa_pnp_id pcibus_pnp_ids[] = { 690 { 0x030ad041 /* PNP0A03 */, "PCI Bus" }, 691 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" }, 692 { 0 } 693 }; 694 695 static int 696 pcibus_pnp_probe(device_t dev) 697 { 698 int result; 699 700 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0) 701 device_quiet(dev); 702 return(result); 703 } 704 705 static int 706 pcibus_pnp_attach(device_t dev) 707 { 708 return(0); 709 } 710 711 static device_method_t pcibus_pnp_methods[] = { 712 /* Device interface */ 713 DEVMETHOD(device_probe, pcibus_pnp_probe), 714 DEVMETHOD(device_attach, pcibus_pnp_attach), 715 DEVMETHOD(device_detach, bus_generic_detach), 716 DEVMETHOD(device_shutdown, bus_generic_shutdown), 717 DEVMETHOD(device_suspend, bus_generic_suspend), 718 DEVMETHOD(device_resume, bus_generic_resume), 719 { 0, 0 } 720 }; 721 722 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1); 723 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, 0, 0); 724 725 #ifdef __HAVE_PIR 726 /* 727 * Provide a PCI-PCI bridge driver for PCI buses behind PCI-PCI bridges 728 * that appear in the PCIBIOS Interrupt Routing Table to use the routing 729 * table for interrupt routing when possible. 730 */ 731 static int pcibios_pcib_probe(device_t bus); 732 733 static device_method_t pcibios_pcib_pci_methods[] = { 734 /* Device interface */ 735 DEVMETHOD(device_probe, pcibios_pcib_probe), 736 737 /* pcib interface */ 738 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt), 739 {0, 0} 740 }; 741 742 DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods, 743 sizeof(struct pcib_softc), pcib_driver); 744 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, 0, 0); 745 ISA_PNP_INFO(pcibus_pnp_ids); 746 747 static int 748 pcibios_pcib_probe(device_t dev) 749 { 750 int bus; 751 752 if ((pci_get_class(dev) != PCIC_BRIDGE) || 753 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI)) 754 return (ENXIO); 755 bus = pci_read_config(dev, PCIR_SECBUS_1, 1); 756 if (bus == 0) 757 return (ENXIO); 758 if (!pci_pir_probe(bus, 1)) 759 return (ENXIO); 760 device_set_desc(dev, "PCIBIOS PCI-PCI bridge"); 761 return (-2000); 762 } 763 #endif 764