xref: /freebsd/sys/x86/isa/elcr.c (revision 38f0b757fd84d17d0fc24739a7cda160c4516d81)
1 /*-
2  * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 /*
31  * The ELCR is a register that controls the trigger mode and polarity of
32  * EISA and ISA interrupts.  In FreeBSD 3.x and 4.x, the ELCR was only
33  * consulted for determining the appropriate trigger mode of EISA
34  * interrupts when using an APIC.  However, it seems that almost all
35  * systems that include PCI also include an ELCR that manages the ISA
36  * IRQs 0 through 15.  Thus, we check for the presence of an ELCR on
37  * every machine by checking to see if the values found at bootup are
38  * sane.  Note that the polarity of ISA and EISA IRQs are linked to the
39  * trigger mode.  All edge triggered IRQs use active-hi polarity, and
40  * all level triggered interrupts use active-lo polarity.
41  *
42  * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
43  * controls IRQ 0, bit 1 controls IRQ 1, etc.  If the bit is zero, the
44  * associated IRQ is edge triggered.  If the bit is one, the IRQ is
45  * level triggered.
46  */
47 
48 #include <sys/param.h>
49 #include <sys/bus.h>
50 #include <sys/systm.h>
51 #include <machine/intr_machdep.h>
52 
53 #define	ELCR_PORT	0x4d0
54 #define	ELCR_MASK(irq)	(1 << (irq))
55 
56 static int elcr_status;
57 int elcr_found;
58 
59 /*
60  * Check to see if we have what looks like a valid ELCR.  We do this by
61  * verifying that IRQs 0, 1, 2, and 13 are all edge triggered.
62  */
63 int
64 elcr_probe(void)
65 {
66 	int i;
67 
68 	elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8;
69 	if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) |
70 	    ELCR_MASK(8) | ELCR_MASK(13))) != 0)
71 		return (ENXIO);
72 	if (bootverbose) {
73 		printf("ELCR Found.  ISA IRQs programmed as:\n");
74 		for (i = 0; i < 16; i++)
75 			printf(" %2d", i);
76 		printf("\n");
77 		for (i = 0; i < 16; i++)
78 			if (elcr_status & ELCR_MASK(i))
79 				printf("  L");
80 			else
81 				printf("  E");
82 		printf("\n");
83 	}
84 	if (resource_disabled("elcr", 0))
85 		return (ENXIO);
86 	elcr_found = 1;
87 	return (0);
88 }
89 
90 /*
91  * Returns 1 for level trigger, 0 for edge.
92  */
93 enum intr_trigger
94 elcr_read_trigger(u_int irq)
95 {
96 
97 	KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
98 	KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
99 	if (elcr_status & ELCR_MASK(irq))
100 		return (INTR_TRIGGER_LEVEL);
101 	else
102 		return (INTR_TRIGGER_EDGE);
103 }
104 
105 /*
106  * Set the trigger mode for a specified IRQ.  Mode of 0 means edge triggered,
107  * and a mode of 1 means level triggered.
108  */
109 void
110 elcr_write_trigger(u_int irq, enum intr_trigger trigger)
111 {
112 	int new_status;
113 
114 	KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
115 	KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
116 	if (trigger == INTR_TRIGGER_LEVEL)
117 		new_status = elcr_status | ELCR_MASK(irq);
118 	else
119 		new_status = elcr_status & ~ELCR_MASK(irq);
120 	if (new_status == elcr_status)
121 		return;
122 	elcr_status = new_status;
123 	if (irq >= 8)
124 		outb(ELCR_PORT + 1, elcr_status >> 8);
125 	else
126 		outb(ELCR_PORT, elcr_status & 0xff);
127 }
128 
129 void
130 elcr_resume(void)
131 {
132 
133 	KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
134 	outb(ELCR_PORT, elcr_status & 0xff);
135 	outb(ELCR_PORT + 1, elcr_status >> 8);
136 }
137