132580301SAttilio Rao /*- 232580301SAttilio Rao * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org> 332580301SAttilio Rao * All rights reserved. 432580301SAttilio Rao * 532580301SAttilio Rao * Redistribution and use in source and binary forms, with or without 632580301SAttilio Rao * modification, are permitted provided that the following conditions 732580301SAttilio Rao * are met: 832580301SAttilio Rao * 1. Redistributions of source code must retain the above copyright 932580301SAttilio Rao * notice, this list of conditions and the following disclaimer. 1032580301SAttilio Rao * 2. Redistributions in binary form must reproduce the above copyright 1132580301SAttilio Rao * notice, this list of conditions and the following disclaimer in the 1232580301SAttilio Rao * documentation and/or other materials provided with the distribution. 1332580301SAttilio Rao * 3. Neither the name of the author nor the names of any co-contributors 1432580301SAttilio Rao * may be used to endorse or promote products derived from this software 1532580301SAttilio Rao * without specific prior written permission. 1632580301SAttilio Rao * 1732580301SAttilio Rao * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1832580301SAttilio Rao * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1932580301SAttilio Rao * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2032580301SAttilio Rao * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2132580301SAttilio Rao * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2232580301SAttilio Rao * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2332580301SAttilio Rao * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2432580301SAttilio Rao * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2532580301SAttilio Rao * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2632580301SAttilio Rao * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2732580301SAttilio Rao * SUCH DAMAGE. 2832580301SAttilio Rao */ 2932580301SAttilio Rao 3032580301SAttilio Rao #include <sys/cdefs.h> 3132580301SAttilio Rao __FBSDID("$FreeBSD$"); 3232580301SAttilio Rao 3332580301SAttilio Rao /* 3432580301SAttilio Rao * The ELCR is a register that controls the trigger mode and polarity of 3532580301SAttilio Rao * EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only 3632580301SAttilio Rao * consulted for determining the appropriate trigger mode of EISA 3732580301SAttilio Rao * interrupts when using an APIC. However, it seems that almost all 3832580301SAttilio Rao * systems that include PCI also include an ELCR that manages the ISA 3932580301SAttilio Rao * IRQs 0 through 15. Thus, we check for the presence of an ELCR on 4032580301SAttilio Rao * every machine by checking to see if the values found at bootup are 4132580301SAttilio Rao * sane. Note that the polarity of ISA and EISA IRQs are linked to the 4232580301SAttilio Rao * trigger mode. All edge triggered IRQs use active-hi polarity, and 4332580301SAttilio Rao * all level triggered interrupts use active-lo polarity. 4432580301SAttilio Rao * 4532580301SAttilio Rao * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0 4632580301SAttilio Rao * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the 4732580301SAttilio Rao * associated IRQ is edge triggered. If the bit is one, the IRQ is 4832580301SAttilio Rao * level triggered. 4932580301SAttilio Rao */ 5032580301SAttilio Rao 5132580301SAttilio Rao #include <sys/param.h> 5232580301SAttilio Rao #include <sys/bus.h> 5332580301SAttilio Rao #include <sys/systm.h> 5432580301SAttilio Rao #include <machine/intr_machdep.h> 5532580301SAttilio Rao 5632580301SAttilio Rao #define ELCR_PORT 0x4d0 5732580301SAttilio Rao #define ELCR_MASK(irq) (1 << (irq)) 5832580301SAttilio Rao 5932580301SAttilio Rao static int elcr_status; 6032580301SAttilio Rao int elcr_found; 6132580301SAttilio Rao 6232580301SAttilio Rao /* 6332580301SAttilio Rao * Check to see if we have what looks like a valid ELCR. We do this by 6432580301SAttilio Rao * verifying that IRQs 0, 1, 2, and 13 are all edge triggered. 6532580301SAttilio Rao */ 6632580301SAttilio Rao int 6732580301SAttilio Rao elcr_probe(void) 6832580301SAttilio Rao { 6932580301SAttilio Rao int i; 7032580301SAttilio Rao 7132580301SAttilio Rao elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8; 7232580301SAttilio Rao if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) | 7332580301SAttilio Rao ELCR_MASK(8) | ELCR_MASK(13))) != 0) 7432580301SAttilio Rao return (ENXIO); 7532580301SAttilio Rao if (bootverbose) { 7632580301SAttilio Rao printf("ELCR Found. ISA IRQs programmed as:\n"); 7732580301SAttilio Rao for (i = 0; i < 16; i++) 7832580301SAttilio Rao printf(" %2d", i); 7932580301SAttilio Rao printf("\n"); 8032580301SAttilio Rao for (i = 0; i < 16; i++) 8132580301SAttilio Rao if (elcr_status & ELCR_MASK(i)) 8232580301SAttilio Rao printf(" L"); 8332580301SAttilio Rao else 8432580301SAttilio Rao printf(" E"); 8532580301SAttilio Rao printf("\n"); 8632580301SAttilio Rao } 8732580301SAttilio Rao if (resource_disabled("elcr", 0)) 8832580301SAttilio Rao return (ENXIO); 8932580301SAttilio Rao elcr_found = 1; 9032580301SAttilio Rao return (0); 9132580301SAttilio Rao } 9232580301SAttilio Rao 9332580301SAttilio Rao /* 9432580301SAttilio Rao * Returns 1 for level trigger, 0 for edge. 9532580301SAttilio Rao */ 9632580301SAttilio Rao enum intr_trigger 9732580301SAttilio Rao elcr_read_trigger(u_int irq) 9832580301SAttilio Rao { 9932580301SAttilio Rao 10032580301SAttilio Rao KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); 10132580301SAttilio Rao KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); 10232580301SAttilio Rao if (elcr_status & ELCR_MASK(irq)) 10332580301SAttilio Rao return (INTR_TRIGGER_LEVEL); 10432580301SAttilio Rao else 10532580301SAttilio Rao return (INTR_TRIGGER_EDGE); 10632580301SAttilio Rao } 10732580301SAttilio Rao 10832580301SAttilio Rao /* 10932580301SAttilio Rao * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered, 11032580301SAttilio Rao * and a mode of 1 means level triggered. 11132580301SAttilio Rao */ 11232580301SAttilio Rao void 11332580301SAttilio Rao elcr_write_trigger(u_int irq, enum intr_trigger trigger) 11432580301SAttilio Rao { 11532580301SAttilio Rao int new_status; 11632580301SAttilio Rao 11732580301SAttilio Rao KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); 11832580301SAttilio Rao KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); 11932580301SAttilio Rao if (trigger == INTR_TRIGGER_LEVEL) 12032580301SAttilio Rao new_status = elcr_status | ELCR_MASK(irq); 12132580301SAttilio Rao else 12232580301SAttilio Rao new_status = elcr_status & ~ELCR_MASK(irq); 12332580301SAttilio Rao if (new_status == elcr_status) 12432580301SAttilio Rao return; 12532580301SAttilio Rao elcr_status = new_status; 12632580301SAttilio Rao if (irq >= 8) 12732580301SAttilio Rao outb(ELCR_PORT + 1, elcr_status >> 8); 12832580301SAttilio Rao else 12932580301SAttilio Rao outb(ELCR_PORT, elcr_status & 0xff); 13032580301SAttilio Rao } 13132580301SAttilio Rao 13232580301SAttilio Rao void 13332580301SAttilio Rao elcr_resume(void) 13432580301SAttilio Rao { 13532580301SAttilio Rao 13632580301SAttilio Rao KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); 13732580301SAttilio Rao outb(ELCR_PORT, elcr_status & 0xff); 13832580301SAttilio Rao outb(ELCR_PORT + 1, elcr_status >> 8); 13932580301SAttilio Rao } 140