1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_auto_eoi.h" 37 #include "opt_isa.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/interrupt.h> 43 #include <sys/kernel.h> 44 #include <sys/lock.h> 45 #include <sys/module.h> 46 47 #include <machine/cpufunc.h> 48 #include <machine/frame.h> 49 #include <machine/intr_machdep.h> 50 #include <machine/md_var.h> 51 #include <machine/resource.h> 52 #include <machine/segments.h> 53 54 #include <dev/ic/i8259.h> 55 #include <x86/isa/icu.h> 56 #include <isa/isareg.h> 57 #include <isa/isavar.h> 58 59 #ifdef __amd64__ 60 #define SDT_ATPIC SDT_SYSIGT 61 #define GSEL_ATPIC 0 62 #else 63 #define SDT_ATPIC SDT_SYS386IGT 64 #define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL) 65 #endif 66 67 #define MASTER 0 68 #define SLAVE 1 69 70 #define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq)) 71 72 #define NUM_ISA_IRQS 16 73 74 static void atpic_init(void *dummy); 75 76 inthand_t 77 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2), 78 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5), 79 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8), 80 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11), 81 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14), 82 IDTVEC(atpic_intr15); 83 /* XXXKIB i386 uses stubs until pti comes */ 84 inthand_t 85 IDTVEC(atpic_intr0_pti), IDTVEC(atpic_intr1_pti), 86 IDTVEC(atpic_intr2_pti), IDTVEC(atpic_intr3_pti), 87 IDTVEC(atpic_intr4_pti), IDTVEC(atpic_intr5_pti), 88 IDTVEC(atpic_intr6_pti), IDTVEC(atpic_intr7_pti), 89 IDTVEC(atpic_intr8_pti), IDTVEC(atpic_intr9_pti), 90 IDTVEC(atpic_intr10_pti), IDTVEC(atpic_intr11_pti), 91 IDTVEC(atpic_intr12_pti), IDTVEC(atpic_intr13_pti), 92 IDTVEC(atpic_intr14_pti), IDTVEC(atpic_intr15_pti); 93 94 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq) 95 96 #define ATPIC(io, base, eoi) { \ 97 .at_pic = { \ 98 .pic_register_sources = atpic_register_sources, \ 99 .pic_enable_source = atpic_enable_source, \ 100 .pic_disable_source = atpic_disable_source, \ 101 .pic_eoi_source = (eoi), \ 102 .pic_enable_intr = atpic_enable_intr, \ 103 .pic_disable_intr = atpic_disable_intr, \ 104 .pic_vector = atpic_vector, \ 105 .pic_source_pending = atpic_source_pending, \ 106 .pic_resume = atpic_resume, \ 107 .pic_config_intr = atpic_config_intr, \ 108 .pic_assign_cpu = atpic_assign_cpu \ 109 }, \ 110 .at_ioaddr = (io), \ 111 .at_irqbase = (base), \ 112 .at_intbase = IDT_IO_INTS + (base), \ 113 .at_imen = 0xff, \ 114 } 115 116 #define INTSRC(irq) \ 117 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \ 118 IDTVEC(atpic_intr ## irq ## _pti), (irq) % 8 } 119 120 struct atpic { 121 struct pic at_pic; 122 int at_ioaddr; 123 int at_irqbase; 124 uint8_t at_intbase; 125 uint8_t at_imen; 126 }; 127 128 struct atpic_intsrc { 129 struct intsrc at_intsrc; 130 inthand_t *at_intr, *at_intr_pti; 131 int at_irq; /* Relative to PIC base. */ 132 enum intr_trigger at_trigger; 133 u_long at_count; 134 u_long at_straycount; 135 }; 136 137 static void atpic_register_sources(struct pic *pic); 138 static void atpic_enable_source(struct intsrc *isrc); 139 static void atpic_disable_source(struct intsrc *isrc, int eoi); 140 static void atpic_eoi_master(struct intsrc *isrc); 141 static void atpic_eoi_slave(struct intsrc *isrc); 142 static void atpic_enable_intr(struct intsrc *isrc); 143 static void atpic_disable_intr(struct intsrc *isrc); 144 static int atpic_vector(struct intsrc *isrc); 145 static void atpic_resume(struct pic *pic, bool suspend_cancelled); 146 static int atpic_source_pending(struct intsrc *isrc); 147 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 148 enum intr_polarity pol); 149 static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id); 150 static void i8259_init(struct atpic *pic, int slave); 151 152 static struct atpic atpics[] = { 153 ATPIC(IO_ICU1, 0, atpic_eoi_master), 154 ATPIC(IO_ICU2, 8, atpic_eoi_slave) 155 }; 156 157 static struct atpic_intsrc atintrs[] = { 158 INTSRC(0), 159 INTSRC(1), 160 INTSRC(2), 161 INTSRC(3), 162 INTSRC(4), 163 INTSRC(5), 164 INTSRC(6), 165 INTSRC(7), 166 INTSRC(8), 167 INTSRC(9), 168 INTSRC(10), 169 INTSRC(11), 170 INTSRC(12), 171 INTSRC(13), 172 INTSRC(14), 173 INTSRC(15), 174 }; 175 176 CTASSERT(nitems(atintrs) == NUM_ISA_IRQS); 177 178 static __inline void 179 _atpic_eoi_master(struct intsrc *isrc) 180 { 181 182 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic, 183 ("%s: mismatched pic", __func__)); 184 #ifndef AUTO_EOI_1 185 outb(atpics[MASTER].at_ioaddr, OCW2_EOI); 186 #endif 187 } 188 189 /* 190 * The data sheet says no auto-EOI on slave, but it sometimes works. 191 * So, if AUTO_EOI_2 is enabled, we use it. 192 */ 193 static __inline void 194 _atpic_eoi_slave(struct intsrc *isrc) 195 { 196 197 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic, 198 ("%s: mismatched pic", __func__)); 199 #ifndef AUTO_EOI_2 200 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI); 201 #ifndef AUTO_EOI_1 202 outb(atpics[MASTER].at_ioaddr, OCW2_EOI); 203 #endif 204 #endif 205 } 206 207 static void 208 atpic_register_sources(struct pic *pic) 209 { 210 struct atpic *ap = (struct atpic *)pic; 211 struct atpic_intsrc *ai; 212 int i; 213 214 /* 215 * If any of the ISA IRQs have an interrupt source already, then 216 * assume that the I/O APICs are being used and don't register any 217 * of our interrupt sources. This makes sure we don't accidentally 218 * use mixed mode. The "accidental" use could otherwise occur on 219 * machines that route the ACPI SCI interrupt to a different ISA 220 * IRQ (at least one machine routes it to IRQ 13) thus disabling 221 * that APIC ISA routing and allowing the ATPIC source for that IRQ 222 * to leak through. We used to depend on this feature for routing 223 * IRQ0 via mixed mode, but now we don't use mixed mode at all. 224 */ 225 for (i = 0; i < NUM_ISA_IRQS; i++) 226 if (intr_lookup_source(i) != NULL) 227 return; 228 229 /* Loop through all interrupt sources and add them. */ 230 for (i = 0, ai = atintrs + ap->at_irqbase; i < 8; i++, ai++) { 231 if (ap->at_irqbase + i == ICU_SLAVEID) 232 continue; 233 intr_register_source(&ai->at_intsrc); 234 } 235 } 236 237 static void 238 atpic_enable_source(struct intsrc *isrc) 239 { 240 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; 241 struct atpic *ap = (struct atpic *)isrc->is_pic; 242 243 spinlock_enter(); 244 if (ap->at_imen & IMEN_MASK(ai)) { 245 ap->at_imen &= ~IMEN_MASK(ai); 246 outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen); 247 } 248 spinlock_exit(); 249 } 250 251 static void 252 atpic_disable_source(struct intsrc *isrc, int eoi) 253 { 254 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; 255 struct atpic *ap = (struct atpic *)isrc->is_pic; 256 257 spinlock_enter(); 258 if (ai->at_trigger != INTR_TRIGGER_EDGE) { 259 ap->at_imen |= IMEN_MASK(ai); 260 outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen); 261 } 262 263 /* 264 * Take care to call these functions directly instead of through 265 * a function pointer. All of the referenced variables should 266 * still be hot in the cache. 267 */ 268 if (eoi == PIC_EOI) { 269 if (isrc->is_pic == &atpics[MASTER].at_pic) 270 _atpic_eoi_master(isrc); 271 else 272 _atpic_eoi_slave(isrc); 273 } 274 275 spinlock_exit(); 276 } 277 278 static void 279 atpic_eoi_master(struct intsrc *isrc) 280 { 281 #ifndef AUTO_EOI_1 282 spinlock_enter(); 283 _atpic_eoi_master(isrc); 284 spinlock_exit(); 285 #endif 286 } 287 288 static void 289 atpic_eoi_slave(struct intsrc *isrc) 290 { 291 #ifndef AUTO_EOI_2 292 spinlock_enter(); 293 _atpic_eoi_slave(isrc); 294 spinlock_exit(); 295 #endif 296 } 297 298 static void 299 atpic_enable_intr(struct intsrc *isrc) 300 { 301 } 302 303 static void 304 atpic_disable_intr(struct intsrc *isrc) 305 { 306 } 307 308 309 static int 310 atpic_vector(struct intsrc *isrc) 311 { 312 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; 313 struct atpic *ap = (struct atpic *)isrc->is_pic; 314 315 return (IRQ(ap, ai)); 316 } 317 318 static int 319 atpic_source_pending(struct intsrc *isrc) 320 { 321 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; 322 struct atpic *ap = (struct atpic *)isrc->is_pic; 323 324 return (inb(ap->at_ioaddr) & IMEN_MASK(ai)); 325 } 326 327 static void 328 atpic_resume(struct pic *pic, bool suspend_cancelled) 329 { 330 struct atpic *ap = (struct atpic *)pic; 331 332 i8259_init(ap, ap == &atpics[SLAVE]); 333 if (ap == &atpics[SLAVE] && elcr_found) 334 elcr_resume(); 335 } 336 337 static int 338 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 339 enum intr_polarity pol) 340 { 341 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; 342 u_int vector; 343 344 /* Map conforming values to edge/hi and sanity check the values. */ 345 if (trig == INTR_TRIGGER_CONFORM) 346 trig = INTR_TRIGGER_EDGE; 347 if (pol == INTR_POLARITY_CONFORM) 348 pol = INTR_POLARITY_HIGH; 349 vector = atpic_vector(isrc); 350 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) || 351 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) { 352 printf( 353 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n", 354 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level", 355 pol == INTR_POLARITY_HIGH ? "high" : "low"); 356 return (EINVAL); 357 } 358 359 /* If there is no change, just return. */ 360 if (ai->at_trigger == trig) 361 return (0); 362 363 /* 364 * Certain IRQs can never be level/lo, so don't try to set them 365 * that way if asked. At least some ELCR registers ignore setting 366 * these bits as well. 367 */ 368 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) && 369 trig == INTR_TRIGGER_LEVEL) { 370 if (bootverbose) 371 printf( 372 "atpic: Ignoring invalid level/low configuration for IRQ%u\n", 373 vector); 374 return (EINVAL); 375 } 376 if (!elcr_found) { 377 if (bootverbose) 378 printf("atpic: No ELCR to configure IRQ%u as %s\n", 379 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" : 380 "level/low"); 381 return (ENXIO); 382 } 383 if (bootverbose) 384 printf("atpic: Programming IRQ%u as %s\n", vector, 385 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low"); 386 spinlock_enter(); 387 elcr_write_trigger(atpic_vector(isrc), trig); 388 ai->at_trigger = trig; 389 spinlock_exit(); 390 return (0); 391 } 392 393 static int 394 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id) 395 { 396 397 /* 398 * 8259A's are only used in UP in which case all interrupts always 399 * go to the sole CPU and this function shouldn't even be called. 400 */ 401 panic("%s: bad cookie", __func__); 402 } 403 404 static void 405 i8259_init(struct atpic *pic, int slave) 406 { 407 int imr_addr; 408 409 /* Reset the PIC and program with next four bytes. */ 410 spinlock_enter(); 411 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4); 412 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET; 413 414 /* Start vector. */ 415 outb(imr_addr, pic->at_intbase); 416 417 /* 418 * Setup slave links. For the master pic, indicate what line 419 * the slave is configured on. For the slave indicate 420 * which line on the master we are connected to. 421 */ 422 if (slave) 423 outb(imr_addr, ICU_SLAVEID); 424 else 425 outb(imr_addr, IRQ_MASK(ICU_SLAVEID)); 426 427 /* Set mode. */ 428 if (slave) 429 outb(imr_addr, SLAVE_MODE); 430 else 431 outb(imr_addr, MASTER_MODE); 432 433 /* Set interrupt enable mask. */ 434 outb(imr_addr, pic->at_imen); 435 436 /* Reset is finished, default to IRR on read. */ 437 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR); 438 439 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */ 440 if (!slave) 441 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1); 442 443 spinlock_exit(); 444 } 445 446 void 447 atpic_startup(void) 448 { 449 struct atpic_intsrc *ai; 450 int i; 451 452 /* Start off with all interrupts disabled. */ 453 i8259_init(&atpics[MASTER], 0); 454 i8259_init(&atpics[SLAVE], 1); 455 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]); 456 457 /* Install low-level interrupt handlers for all of our IRQs. */ 458 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) { 459 if (i == ICU_SLAVEID) 460 continue; 461 ai->at_intsrc.is_count = &ai->at_count; 462 ai->at_intsrc.is_straycount = &ai->at_straycount; 463 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase + 464 ai->at_irq, pti ? ai->at_intr_pti : ai->at_intr, SDT_ATPIC, 465 SEL_KPL, GSEL_ATPIC); 466 } 467 468 /* 469 * Look for an ELCR. If we find one, update the trigger modes. 470 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are 471 * edge triggered and that everything else is level triggered. 472 * We only use the trigger information to reprogram the ELCR if 473 * we have one and as an optimization to avoid masking edge 474 * triggered interrupts. For the case that we don't have an ELCR, 475 * it doesn't hurt to mask an edge triggered interrupt, so we 476 * assume level trigger for any interrupt that we aren't sure is 477 * edge triggered. 478 */ 479 if (elcr_found) { 480 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) 481 ai->at_trigger = elcr_read_trigger(i); 482 } else { 483 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) 484 switch (i) { 485 case 0: 486 case 1: 487 case 2: 488 case 8: 489 case 13: 490 ai->at_trigger = INTR_TRIGGER_EDGE; 491 break; 492 default: 493 ai->at_trigger = INTR_TRIGGER_LEVEL; 494 break; 495 } 496 } 497 } 498 499 static void 500 atpic_init(void *dummy __unused) 501 { 502 503 /* 504 * Register our PICs, even if we aren't going to use any of their 505 * pins so that they are suspended and resumed. 506 */ 507 if (intr_register_pic(&atpics[0].at_pic) != 0 || 508 intr_register_pic(&atpics[1].at_pic) != 0) 509 panic("Unable to register ATPICs"); 510 511 if (num_io_irqs == 0) 512 num_io_irqs = NUM_ISA_IRQS; 513 } 514 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_FOURTH, atpic_init, NULL); 515 516 void 517 atpic_handle_intr(u_int vector, struct trapframe *frame) 518 { 519 struct intsrc *isrc; 520 521 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector)); 522 isrc = &atintrs[vector].at_intsrc; 523 524 /* 525 * If we don't have an event, see if this is a spurious 526 * interrupt. 527 */ 528 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) { 529 int port, isr; 530 531 /* 532 * Read the ISR register to see if IRQ 7/15 is really 533 * pending. Reset read register back to IRR when done. 534 */ 535 port = ((struct atpic *)isrc->is_pic)->at_ioaddr; 536 spinlock_enter(); 537 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS); 538 isr = inb(port); 539 outb(port, OCW3_SEL | OCW3_RR); 540 spinlock_exit(); 541 if ((isr & IRQ_MASK(7)) == 0) 542 return; 543 } 544 intr_execute_handlers(isrc, frame); 545 } 546 547 #ifdef DEV_ISA 548 /* 549 * Bus attachment for the ISA PIC. 550 */ 551 static struct isa_pnp_id atpic_ids[] = { 552 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, 553 { 0 } 554 }; 555 556 static int 557 atpic_probe(device_t dev) 558 { 559 int result; 560 561 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids); 562 if (result <= 0) 563 device_quiet(dev); 564 return (result); 565 } 566 567 /* 568 * We might be granted IRQ 2, as this is typically consumed by chaining 569 * between the two PIC components. If we're using the APIC, however, 570 * this may not be the case, and as such we should free the resource. 571 * (XXX untested) 572 * 573 * The generic ISA attachment code will handle allocating any other resources 574 * that we don't explicitly claim here. 575 */ 576 static int 577 atpic_attach(device_t dev) 578 { 579 struct resource *res; 580 int rid; 581 582 /* Try to allocate our IRQ and then free it. */ 583 rid = 0; 584 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0); 585 if (res != NULL) 586 bus_release_resource(dev, SYS_RES_IRQ, rid, res); 587 return (0); 588 } 589 590 /* 591 * Return a bitmap of the current interrupt requests. This is 8259-specific 592 * and is only suitable for use at probe time. 593 */ 594 intrmask_t 595 isa_irq_pending(void) 596 { 597 u_char irr1; 598 u_char irr2; 599 600 irr1 = inb(IO_ICU1); 601 irr2 = inb(IO_ICU2); 602 return ((irr2 << 8) | irr1); 603 } 604 605 static device_method_t atpic_methods[] = { 606 /* Device interface */ 607 DEVMETHOD(device_probe, atpic_probe), 608 DEVMETHOD(device_attach, atpic_attach), 609 DEVMETHOD(device_detach, bus_generic_detach), 610 DEVMETHOD(device_shutdown, bus_generic_shutdown), 611 DEVMETHOD(device_suspend, bus_generic_suspend), 612 DEVMETHOD(device_resume, bus_generic_resume), 613 { 0, 0 } 614 }; 615 616 static driver_t atpic_driver = { 617 "atpic", 618 atpic_methods, 619 1, /* no softc */ 620 }; 621 622 static devclass_t atpic_devclass; 623 624 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0); 625 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0); 626 ISA_PNP_INFO(atpic_ids); 627 #endif /* DEV_ISA */ 628