1 /*- 2 * Copyright (c) 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/memdesc.h> 39 #include <sys/mutex.h> 40 #include <sys/proc.h> 41 #include <sys/queue.h> 42 #include <sys/rman.h> 43 #include <sys/rwlock.h> 44 #include <sys/sched.h> 45 #include <sys/sf_buf.h> 46 #include <sys/sysctl.h> 47 #include <sys/systm.h> 48 #include <sys/taskqueue.h> 49 #include <sys/tree.h> 50 #include <sys/vmem.h> 51 #include <dev/pci/pcivar.h> 52 #include <vm/vm.h> 53 #include <vm/vm_extern.h> 54 #include <vm/vm_kern.h> 55 #include <vm/vm_object.h> 56 #include <vm/vm_page.h> 57 #include <vm/vm_map.h> 58 #include <vm/vm_pageout.h> 59 #include <machine/bus.h> 60 #include <machine/cpu.h> 61 #include <machine/intr_machdep.h> 62 #include <x86/include/apicvar.h> 63 #include <x86/include/busdma_impl.h> 64 #include <x86/iommu/intel_reg.h> 65 #include <x86/iommu/busdma_dmar.h> 66 #include <x86/iommu/intel_dmar.h> 67 68 u_int 69 dmar_nd2mask(u_int nd) 70 { 71 static const u_int masks[] = { 72 0x000f, /* nd == 0 */ 73 0x002f, /* nd == 1 */ 74 0x00ff, /* nd == 2 */ 75 0x02ff, /* nd == 3 */ 76 0x0fff, /* nd == 4 */ 77 0x2fff, /* nd == 5 */ 78 0xffff, /* nd == 6 */ 79 0x0000, /* nd == 7 reserved */ 80 }; 81 82 KASSERT(nd <= 6, ("number of domains %d", nd)); 83 return (masks[nd]); 84 } 85 86 static const struct sagaw_bits_tag { 87 int agaw; 88 int cap; 89 int awlvl; 90 int pglvl; 91 } sagaw_bits[] = { 92 {.agaw = 30, .cap = DMAR_CAP_SAGAW_2LVL, .awlvl = DMAR_CTX2_AW_2LVL, 93 .pglvl = 2}, 94 {.agaw = 39, .cap = DMAR_CAP_SAGAW_3LVL, .awlvl = DMAR_CTX2_AW_3LVL, 95 .pglvl = 3}, 96 {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL, 97 .pglvl = 4}, 98 {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL, 99 .pglvl = 5}, 100 {.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL, 101 .pglvl = 6} 102 }; 103 #define SIZEOF_SAGAW_BITS (sizeof(sagaw_bits) / sizeof(sagaw_bits[0])) 104 105 bool 106 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl) 107 { 108 int i; 109 110 for (i = 0; i < SIZEOF_SAGAW_BITS; i++) { 111 if (sagaw_bits[i].pglvl != pglvl) 112 continue; 113 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) 114 return (true); 115 } 116 return (false); 117 } 118 119 int 120 ctx_set_agaw(struct dmar_ctx *ctx, int mgaw) 121 { 122 int sagaw, i; 123 124 ctx->mgaw = mgaw; 125 sagaw = DMAR_CAP_SAGAW(ctx->dmar->hw_cap); 126 for (i = 0; i < SIZEOF_SAGAW_BITS; i++) { 127 if (sagaw_bits[i].agaw >= mgaw) { 128 ctx->agaw = sagaw_bits[i].agaw; 129 ctx->pglvl = sagaw_bits[i].pglvl; 130 ctx->awlvl = sagaw_bits[i].awlvl; 131 return (0); 132 } 133 } 134 device_printf(ctx->dmar->dev, 135 "context request mgaw %d for pci%d:%d:%d:%d, " 136 "no agaw found, sagaw %x\n", mgaw, ctx->dmar->segment, 137 pci_get_bus(ctx->ctx_tag.owner), 138 pci_get_slot(ctx->ctx_tag.owner), 139 pci_get_function(ctx->ctx_tag.owner), sagaw); 140 return (EINVAL); 141 } 142 143 /* 144 * Find a best fit mgaw for the given maxaddr: 145 * - if allow_less is false, must find sagaw which maps all requested 146 * addresses (used by identity mappings); 147 * - if allow_less is true, and no supported sagaw can map all requested 148 * address space, accept the biggest sagaw, whatever is it. 149 */ 150 int 151 dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr, bool allow_less) 152 { 153 int i; 154 155 for (i = 0; i < SIZEOF_SAGAW_BITS; i++) { 156 if ((1ULL << sagaw_bits[i].agaw) >= maxaddr && 157 (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) 158 break; 159 } 160 if (allow_less && i == SIZEOF_SAGAW_BITS) { 161 do { 162 i--; 163 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) 164 == 0); 165 } 166 if (i < SIZEOF_SAGAW_BITS) 167 return (sagaw_bits[i].agaw); 168 KASSERT(0, ("no mgaw for maxaddr %jx allow_less %d", 169 (uintmax_t) maxaddr, allow_less)); 170 return (-1); 171 } 172 173 /* 174 * Calculate the total amount of page table pages needed to map the 175 * whole bus address space on the context with the selected agaw. 176 */ 177 vm_pindex_t 178 pglvl_max_pages(int pglvl) 179 { 180 vm_pindex_t res; 181 int i; 182 183 for (res = 0, i = pglvl; i > 0; i--) { 184 res *= DMAR_NPTEPG; 185 res++; 186 } 187 return (res); 188 } 189 190 /* 191 * Return true if the page table level lvl supports the superpage for 192 * the context ctx. 193 */ 194 int 195 ctx_is_sp_lvl(struct dmar_ctx *ctx, int lvl) 196 { 197 int alvl, cap_sps; 198 static const int sagaw_sp[] = { 199 DMAR_CAP_SPS_2M, 200 DMAR_CAP_SPS_1G, 201 DMAR_CAP_SPS_512G, 202 DMAR_CAP_SPS_1T 203 }; 204 205 alvl = ctx->pglvl - lvl - 1; 206 cap_sps = DMAR_CAP_SPS(ctx->dmar->hw_cap); 207 return (alvl < sizeof(sagaw_sp) / sizeof(sagaw_sp[0]) && 208 (sagaw_sp[alvl] & cap_sps) != 0); 209 } 210 211 dmar_gaddr_t 212 pglvl_page_size(int total_pglvl, int lvl) 213 { 214 int rlvl; 215 static const dmar_gaddr_t pg_sz[] = { 216 (dmar_gaddr_t)DMAR_PAGE_SIZE, 217 (dmar_gaddr_t)DMAR_PAGE_SIZE << DMAR_NPTEPGSHIFT, 218 (dmar_gaddr_t)DMAR_PAGE_SIZE << (2 * DMAR_NPTEPGSHIFT), 219 (dmar_gaddr_t)DMAR_PAGE_SIZE << (3 * DMAR_NPTEPGSHIFT), 220 (dmar_gaddr_t)DMAR_PAGE_SIZE << (4 * DMAR_NPTEPGSHIFT), 221 (dmar_gaddr_t)DMAR_PAGE_SIZE << (5 * DMAR_NPTEPGSHIFT) 222 }; 223 224 KASSERT(lvl >= 0 && lvl < total_pglvl, 225 ("total %d lvl %d", total_pglvl, lvl)); 226 rlvl = total_pglvl - lvl - 1; 227 KASSERT(rlvl < sizeof(pg_sz) / sizeof(pg_sz[0]), 228 ("sizeof pg_sz lvl %d", lvl)); 229 return (pg_sz[rlvl]); 230 } 231 232 dmar_gaddr_t 233 ctx_page_size(struct dmar_ctx *ctx, int lvl) 234 { 235 236 return (pglvl_page_size(ctx->pglvl, lvl)); 237 } 238 239 int 240 calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size, 241 dmar_gaddr_t *isizep) 242 { 243 dmar_gaddr_t isize; 244 int am; 245 246 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) { 247 isize = 1ULL << (am + DMAR_PAGE_SHIFT); 248 if ((base & (isize - 1)) == 0 && size >= isize) 249 break; 250 if (am == 0) 251 break; 252 } 253 *isizep = isize; 254 return (am); 255 } 256 257 dmar_haddr_t dmar_high; 258 int haw; 259 int dmar_tbl_pagecnt; 260 261 vm_page_t 262 dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags) 263 { 264 vm_page_t m; 265 int zeroed; 266 267 zeroed = (flags & DMAR_PGF_ZERO) != 0 ? VM_ALLOC_ZERO : 0; 268 for (;;) { 269 if ((flags & DMAR_PGF_OBJL) == 0) 270 VM_OBJECT_WLOCK(obj); 271 m = vm_page_lookup(obj, idx); 272 if ((flags & DMAR_PGF_NOALLOC) != 0 || m != NULL) { 273 if ((flags & DMAR_PGF_OBJL) == 0) 274 VM_OBJECT_WUNLOCK(obj); 275 break; 276 } 277 m = vm_page_alloc_contig(obj, idx, VM_ALLOC_NOBUSY | 278 VM_ALLOC_SYSTEM | VM_ALLOC_NODUMP | zeroed, 1, 0, 279 dmar_high, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 280 if ((flags & DMAR_PGF_OBJL) == 0) 281 VM_OBJECT_WUNLOCK(obj); 282 if (m != NULL) { 283 if (zeroed && (m->flags & PG_ZERO) == 0) 284 pmap_zero_page(m); 285 atomic_add_int(&dmar_tbl_pagecnt, 1); 286 break; 287 } 288 if ((flags & DMAR_PGF_WAITOK) == 0) 289 break; 290 if ((flags & DMAR_PGF_OBJL) != 0) 291 VM_OBJECT_WUNLOCK(obj); 292 VM_WAIT; 293 if ((flags & DMAR_PGF_OBJL) != 0) 294 VM_OBJECT_WLOCK(obj); 295 } 296 return (m); 297 } 298 299 void 300 dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags) 301 { 302 vm_page_t m; 303 304 if ((flags & DMAR_PGF_OBJL) == 0) 305 VM_OBJECT_WLOCK(obj); 306 m = vm_page_lookup(obj, idx); 307 if (m != NULL) { 308 vm_page_free(m); 309 atomic_subtract_int(&dmar_tbl_pagecnt, 1); 310 } 311 if ((flags & DMAR_PGF_OBJL) == 0) 312 VM_OBJECT_WUNLOCK(obj); 313 } 314 315 void * 316 dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 317 struct sf_buf **sf) 318 { 319 vm_page_t m; 320 bool allocated; 321 322 if ((flags & DMAR_PGF_OBJL) == 0) 323 VM_OBJECT_WLOCK(obj); 324 m = vm_page_lookup(obj, idx); 325 if (m == NULL && (flags & DMAR_PGF_ALLOC) != 0) { 326 m = dmar_pgalloc(obj, idx, flags | DMAR_PGF_OBJL); 327 allocated = true; 328 } else 329 allocated = false; 330 if (m == NULL) { 331 if ((flags & DMAR_PGF_OBJL) == 0) 332 VM_OBJECT_WUNLOCK(obj); 333 return (NULL); 334 } 335 /* Sleepable allocations cannot fail. */ 336 if ((flags & DMAR_PGF_WAITOK) != 0) 337 VM_OBJECT_WUNLOCK(obj); 338 sched_pin(); 339 *sf = sf_buf_alloc(m, SFB_CPUPRIVATE | ((flags & DMAR_PGF_WAITOK) 340 == 0 ? SFB_NOWAIT : 0)); 341 if (*sf == NULL) { 342 sched_unpin(); 343 if (allocated) { 344 VM_OBJECT_ASSERT_WLOCKED(obj); 345 dmar_pgfree(obj, m->pindex, flags | DMAR_PGF_OBJL); 346 } 347 if ((flags & DMAR_PGF_OBJL) == 0) 348 VM_OBJECT_WUNLOCK(obj); 349 return (NULL); 350 } 351 if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) == 352 (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) 353 VM_OBJECT_WLOCK(obj); 354 else if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) == 0) 355 VM_OBJECT_WUNLOCK(obj); 356 return ((void *)sf_buf_kva(*sf)); 357 } 358 359 void 360 dmar_unmap_pgtbl(struct sf_buf *sf) 361 { 362 363 sf_buf_free(sf); 364 sched_unpin(); 365 } 366 367 static void 368 dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz) 369 { 370 371 if (DMAR_IS_COHERENT(unit)) 372 return; 373 /* 374 * If DMAR does not snoop paging structures accesses, flush 375 * CPU cache to memory. 376 */ 377 pmap_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz, 378 TRUE); 379 } 380 381 void 382 dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst) 383 { 384 385 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 386 } 387 388 void 389 dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst) 390 { 391 392 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 393 } 394 395 void 396 dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst) 397 { 398 399 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 400 } 401 402 /* 403 * Load the root entry pointer into the hardware, busily waiting for 404 * the completion. 405 */ 406 int 407 dmar_load_root_entry_ptr(struct dmar_unit *unit) 408 { 409 vm_page_t root_entry; 410 411 /* 412 * Access to the GCMD register must be serialized while the 413 * command is submitted. 414 */ 415 DMAR_ASSERT_LOCKED(unit); 416 417 VM_OBJECT_RLOCK(unit->ctx_obj); 418 root_entry = vm_page_lookup(unit->ctx_obj, 0); 419 VM_OBJECT_RUNLOCK(unit->ctx_obj); 420 dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry)); 421 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP); 422 /* XXXKIB should have a timeout */ 423 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS) == 0) 424 cpu_spinwait(); 425 return (0); 426 } 427 428 /* 429 * Globally invalidate the context entries cache, busily waiting for 430 * the completion. 431 */ 432 int 433 dmar_inv_ctx_glob(struct dmar_unit *unit) 434 { 435 436 /* 437 * Access to the CCMD register must be serialized while the 438 * command is submitted. 439 */ 440 DMAR_ASSERT_LOCKED(unit); 441 KASSERT(!unit->qi_enabled, ("QI enabled")); 442 443 /* 444 * The DMAR_CCMD_ICC bit in the upper dword should be written 445 * after the low dword write is completed. Amd64 446 * dmar_write8() does not have this issue, i386 dmar_write8() 447 * writes the upper dword last. 448 */ 449 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB); 450 /* XXXKIB should have a timeout */ 451 while ((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32) != 0) 452 cpu_spinwait(); 453 return (0); 454 } 455 456 /* 457 * Globally invalidate the IOTLB, busily waiting for the completion. 458 */ 459 int 460 dmar_inv_iotlb_glob(struct dmar_unit *unit) 461 { 462 int reg; 463 464 DMAR_ASSERT_LOCKED(unit); 465 KASSERT(!unit->qi_enabled, ("QI enabled")); 466 467 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap); 468 /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */ 469 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT | 470 DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW); 471 /* XXXKIB should have a timeout */ 472 while ((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) & 473 DMAR_IOTLB_IVT32) != 0) 474 cpu_spinwait(); 475 return (0); 476 } 477 478 /* 479 * Flush the chipset write buffers. See 11.1 "Write Buffer Flushing" 480 * in the architecture specification. 481 */ 482 int 483 dmar_flush_write_bufs(struct dmar_unit *unit) 484 { 485 486 DMAR_ASSERT_LOCKED(unit); 487 488 /* 489 * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported. 490 */ 491 KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0, 492 ("dmar%d: no RWBF", unit->unit)); 493 494 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF); 495 /* XXXKIB should have a timeout */ 496 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS) == 0) 497 cpu_spinwait(); 498 return (0); 499 } 500 501 int 502 dmar_enable_translation(struct dmar_unit *unit) 503 { 504 505 DMAR_ASSERT_LOCKED(unit); 506 unit->hw_gcmd |= DMAR_GCMD_TE; 507 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 508 /* XXXKIB should have a timeout */ 509 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) == 0) 510 cpu_spinwait(); 511 return (0); 512 } 513 514 int 515 dmar_disable_translation(struct dmar_unit *unit) 516 { 517 518 DMAR_ASSERT_LOCKED(unit); 519 unit->hw_gcmd &= ~DMAR_GCMD_TE; 520 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 521 /* XXXKIB should have a timeout */ 522 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) != 0) 523 cpu_spinwait(); 524 return (0); 525 } 526 527 int 528 dmar_load_irt_ptr(struct dmar_unit *unit) 529 { 530 uint64_t irta, s; 531 532 DMAR_ASSERT_LOCKED(unit); 533 irta = unit->irt_phys; 534 if (DMAR_X2APIC(unit)) 535 irta |= DMAR_IRTA_EIME; 536 s = fls(unit->irte_cnt) - 2; 537 KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK && 538 powerof2(unit->irte_cnt), 539 ("IRTA_REG_S overflow %x", unit->irte_cnt)); 540 irta |= s; 541 dmar_write8(unit, DMAR_IRTA_REG, irta); 542 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP); 543 /* XXXKIB should have a timeout */ 544 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS) == 0) 545 cpu_spinwait(); 546 return (0); 547 } 548 549 int 550 dmar_enable_ir(struct dmar_unit *unit) 551 { 552 553 DMAR_ASSERT_LOCKED(unit); 554 unit->hw_gcmd |= DMAR_GCMD_IRE; 555 unit->hw_gcmd &= ~DMAR_GCMD_CFI; 556 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 557 /* XXXKIB should have a timeout */ 558 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) == 0) 559 cpu_spinwait(); 560 return (0); 561 } 562 563 int 564 dmar_disable_ir(struct dmar_unit *unit) 565 { 566 567 DMAR_ASSERT_LOCKED(unit); 568 unit->hw_gcmd &= ~DMAR_GCMD_IRE; 569 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 570 /* XXXKIB should have a timeout */ 571 while ((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) != 0) 572 cpu_spinwait(); 573 return (0); 574 } 575 576 #define BARRIER_F \ 577 u_int f_done, f_inproc, f_wakeup; \ 578 \ 579 f_done = 1 << (barrier_id * 3); \ 580 f_inproc = 1 << (barrier_id * 3 + 1); \ 581 f_wakeup = 1 << (barrier_id * 3 + 2) 582 583 bool 584 dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id) 585 { 586 BARRIER_F; 587 588 DMAR_LOCK(dmar); 589 if ((dmar->barrier_flags & f_done) != 0) { 590 DMAR_UNLOCK(dmar); 591 return (false); 592 } 593 594 if ((dmar->barrier_flags & f_inproc) != 0) { 595 while ((dmar->barrier_flags & f_inproc) != 0) { 596 dmar->barrier_flags |= f_wakeup; 597 msleep(&dmar->barrier_flags, &dmar->lock, 0, 598 "dmarb", 0); 599 } 600 KASSERT((dmar->barrier_flags & f_done) != 0, 601 ("dmar%d barrier %d missing done", dmar->unit, barrier_id)); 602 DMAR_UNLOCK(dmar); 603 return (false); 604 } 605 606 dmar->barrier_flags |= f_inproc; 607 DMAR_UNLOCK(dmar); 608 return (true); 609 } 610 611 void 612 dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id) 613 { 614 BARRIER_F; 615 616 DMAR_ASSERT_LOCKED(dmar); 617 KASSERT((dmar->barrier_flags & (f_done | f_inproc)) == f_inproc, 618 ("dmar%d barrier %d missed entry", dmar->unit, barrier_id)); 619 dmar->barrier_flags |= f_done; 620 if ((dmar->barrier_flags & f_wakeup) != 0) 621 wakeup(&dmar->barrier_flags); 622 dmar->barrier_flags &= ~(f_inproc | f_wakeup); 623 DMAR_UNLOCK(dmar); 624 } 625 626 int dmar_match_verbose; 627 628 static SYSCTL_NODE(_hw, OID_AUTO, dmar, CTLFLAG_RD, NULL, ""); 629 SYSCTL_INT(_hw_dmar, OID_AUTO, tbl_pagecnt, CTLFLAG_RD, 630 &dmar_tbl_pagecnt, 0, 631 "Count of pages used for DMAR pagetables"); 632 SYSCTL_INT(_hw_dmar, OID_AUTO, match_verbose, CTLFLAG_RWTUN, 633 &dmar_match_verbose, 0, 634 "Verbose matching of the PCI devices to DMAR paths"); 635 #ifdef INVARIANTS 636 int dmar_check_free; 637 SYSCTL_INT(_hw_dmar, OID_AUTO, check_free, CTLFLAG_RWTUN, 638 &dmar_check_free, 0, 639 "Check the GPA RBtree for free_down and free_after validity"); 640 #endif 641 642