1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/memdesc.h> 37 #include <sys/mutex.h> 38 #include <sys/proc.h> 39 #include <sys/queue.h> 40 #include <sys/rman.h> 41 #include <sys/rwlock.h> 42 #include <sys/sched.h> 43 #include <sys/sf_buf.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 #include <sys/taskqueue.h> 47 #include <sys/time.h> 48 #include <sys/tree.h> 49 #include <sys/vmem.h> 50 #include <vm/vm.h> 51 #include <vm/vm_extern.h> 52 #include <vm/vm_kern.h> 53 #include <vm/vm_object.h> 54 #include <vm/vm_page.h> 55 #include <vm/vm_map.h> 56 #include <vm/vm_pageout.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 #include <machine/bus.h> 60 #include <machine/cpu.h> 61 #include <machine/intr_machdep.h> 62 #include <x86/include/apicvar.h> 63 #include <x86/include/busdma_impl.h> 64 #include <dev/iommu/busdma_iommu.h> 65 #include <x86/iommu/intel_reg.h> 66 #include <x86/iommu/x86_iommu.h> 67 #include <x86/iommu/intel_dmar.h> 68 69 u_int 70 dmar_nd2mask(u_int nd) 71 { 72 static const u_int masks[] = { 73 0x000f, /* nd == 0 */ 74 0x002f, /* nd == 1 */ 75 0x00ff, /* nd == 2 */ 76 0x02ff, /* nd == 3 */ 77 0x0fff, /* nd == 4 */ 78 0x2fff, /* nd == 5 */ 79 0xffff, /* nd == 6 */ 80 0x0000, /* nd == 7 reserved */ 81 }; 82 83 KASSERT(nd <= 6, ("number of domains %d", nd)); 84 return (masks[nd]); 85 } 86 87 static const struct sagaw_bits_tag { 88 int agaw; 89 int cap; 90 int awlvl; 91 int pglvl; 92 } sagaw_bits[] = { 93 {.agaw = 30, .cap = DMAR_CAP_SAGAW_2LVL, .awlvl = DMAR_CTX2_AW_2LVL, 94 .pglvl = 2}, 95 {.agaw = 39, .cap = DMAR_CAP_SAGAW_3LVL, .awlvl = DMAR_CTX2_AW_3LVL, 96 .pglvl = 3}, 97 {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL, 98 .pglvl = 4}, 99 {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL, 100 .pglvl = 5} 101 /* 102 * 6-level paging (DMAR_CAP_SAGAW_6LVL) is not supported on any 103 * current VT-d hardware and its SAGAW field value is listed as 104 * reserved in the VT-d spec. If support is added in the future, 105 * this structure and the logic in dmar_maxaddr2mgaw() will need 106 * to change to avoid attempted comparison against 1ULL << 64. 107 */ 108 }; 109 110 bool 111 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl) 112 { 113 int i; 114 115 for (i = 0; i < nitems(sagaw_bits); i++) { 116 if (sagaw_bits[i].pglvl != pglvl) 117 continue; 118 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) 119 return (true); 120 } 121 return (false); 122 } 123 124 int 125 domain_set_agaw(struct dmar_domain *domain, int mgaw) 126 { 127 int sagaw, i; 128 129 domain->mgaw = mgaw; 130 sagaw = DMAR_CAP_SAGAW(domain->dmar->hw_cap); 131 for (i = 0; i < nitems(sagaw_bits); i++) { 132 if (sagaw_bits[i].agaw >= mgaw) { 133 domain->agaw = sagaw_bits[i].agaw; 134 domain->pglvl = sagaw_bits[i].pglvl; 135 domain->awlvl = sagaw_bits[i].awlvl; 136 return (0); 137 } 138 } 139 device_printf(domain->dmar->iommu.dev, 140 "context request mgaw %d: no agaw found, sagaw %x\n", 141 mgaw, sagaw); 142 return (EINVAL); 143 } 144 145 /* 146 * Find a best fit mgaw for the given maxaddr: 147 * - if allow_less is false, must find sagaw which maps all requested 148 * addresses (used by identity mappings); 149 * - if allow_less is true, and no supported sagaw can map all requested 150 * address space, accept the biggest sagaw, whatever is it. 151 */ 152 int 153 dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, bool allow_less) 154 { 155 int i; 156 157 for (i = 0; i < nitems(sagaw_bits); i++) { 158 if ((1ULL << sagaw_bits[i].agaw) >= maxaddr && 159 (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) 160 break; 161 } 162 if (allow_less && i == nitems(sagaw_bits)) { 163 do { 164 i--; 165 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) 166 == 0); 167 } 168 if (i < nitems(sagaw_bits)) 169 return (sagaw_bits[i].agaw); 170 KASSERT(0, ("no mgaw for maxaddr %jx allow_less %d", 171 (uintmax_t) maxaddr, allow_less)); 172 return (-1); 173 } 174 175 /* 176 * Calculate the total amount of page table pages needed to map the 177 * whole bus address space on the context with the selected agaw. 178 */ 179 vm_pindex_t 180 pglvl_max_pages(int pglvl) 181 { 182 vm_pindex_t res; 183 int i; 184 185 for (res = 0, i = pglvl; i > 0; i--) { 186 res *= IOMMU_NPTEPG; 187 res++; 188 } 189 return (res); 190 } 191 192 /* 193 * Return true if the page table level lvl supports the superpage for 194 * the context ctx. 195 */ 196 int 197 domain_is_sp_lvl(struct dmar_domain *domain, int lvl) 198 { 199 int alvl, cap_sps; 200 static const int sagaw_sp[] = { 201 DMAR_CAP_SPS_2M, 202 DMAR_CAP_SPS_1G, 203 DMAR_CAP_SPS_512G, 204 DMAR_CAP_SPS_1T 205 }; 206 207 alvl = domain->pglvl - lvl - 1; 208 cap_sps = DMAR_CAP_SPS(domain->dmar->hw_cap); 209 return (alvl < nitems(sagaw_sp) && (sagaw_sp[alvl] & cap_sps) != 0); 210 } 211 212 iommu_gaddr_t 213 pglvl_page_size(int total_pglvl, int lvl) 214 { 215 int rlvl; 216 static const iommu_gaddr_t pg_sz[] = { 217 (iommu_gaddr_t)IOMMU_PAGE_SIZE, 218 (iommu_gaddr_t)IOMMU_PAGE_SIZE << IOMMU_NPTEPGSHIFT, 219 (iommu_gaddr_t)IOMMU_PAGE_SIZE << (2 * IOMMU_NPTEPGSHIFT), 220 (iommu_gaddr_t)IOMMU_PAGE_SIZE << (3 * IOMMU_NPTEPGSHIFT), 221 (iommu_gaddr_t)IOMMU_PAGE_SIZE << (4 * IOMMU_NPTEPGSHIFT), 222 (iommu_gaddr_t)IOMMU_PAGE_SIZE << (5 * IOMMU_NPTEPGSHIFT), 223 }; 224 225 KASSERT(lvl >= 0 && lvl < total_pglvl, 226 ("total %d lvl %d", total_pglvl, lvl)); 227 rlvl = total_pglvl - lvl - 1; 228 KASSERT(rlvl < nitems(pg_sz), ("sizeof pg_sz lvl %d", lvl)); 229 return (pg_sz[rlvl]); 230 } 231 232 iommu_gaddr_t 233 domain_page_size(struct dmar_domain *domain, int lvl) 234 { 235 236 return (pglvl_page_size(domain->pglvl, lvl)); 237 } 238 239 int 240 calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size, 241 iommu_gaddr_t *isizep) 242 { 243 iommu_gaddr_t isize; 244 int am; 245 246 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) { 247 isize = 1ULL << (am + IOMMU_PAGE_SHIFT); 248 if ((base & (isize - 1)) == 0 && size >= isize) 249 break; 250 if (am == 0) 251 break; 252 } 253 *isizep = isize; 254 return (am); 255 } 256 257 int haw; 258 int dmar_tbl_pagecnt; 259 260 static void 261 dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz) 262 { 263 264 if (DMAR_IS_COHERENT(unit)) 265 return; 266 /* 267 * If DMAR does not snoop paging structures accesses, flush 268 * CPU cache to memory. 269 */ 270 pmap_force_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz); 271 } 272 273 void 274 dmar_flush_pte_to_ram(struct dmar_unit *unit, iommu_pte_t *dst) 275 { 276 277 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 278 } 279 280 void 281 dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst) 282 { 283 284 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 285 } 286 287 void 288 dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst) 289 { 290 291 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 292 } 293 294 /* 295 * Load the root entry pointer into the hardware, busily waiting for 296 * the completion. 297 */ 298 int 299 dmar_load_root_entry_ptr(struct dmar_unit *unit) 300 { 301 vm_page_t root_entry; 302 int error; 303 304 /* 305 * Access to the GCMD register must be serialized while the 306 * command is submitted. 307 */ 308 DMAR_ASSERT_LOCKED(unit); 309 310 VM_OBJECT_RLOCK(unit->ctx_obj); 311 root_entry = vm_page_lookup(unit->ctx_obj, 0); 312 VM_OBJECT_RUNLOCK(unit->ctx_obj); 313 dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry)); 314 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP); 315 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS) 316 != 0)); 317 return (error); 318 } 319 320 /* 321 * Globally invalidate the context entries cache, busily waiting for 322 * the completion. 323 */ 324 int 325 dmar_inv_ctx_glob(struct dmar_unit *unit) 326 { 327 int error; 328 329 /* 330 * Access to the CCMD register must be serialized while the 331 * command is submitted. 332 */ 333 DMAR_ASSERT_LOCKED(unit); 334 KASSERT(!unit->qi_enabled, ("QI enabled")); 335 336 /* 337 * The DMAR_CCMD_ICC bit in the upper dword should be written 338 * after the low dword write is completed. Amd64 339 * dmar_write8() does not have this issue, i386 dmar_write8() 340 * writes the upper dword last. 341 */ 342 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB); 343 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32) 344 == 0)); 345 return (error); 346 } 347 348 /* 349 * Globally invalidate the IOTLB, busily waiting for the completion. 350 */ 351 int 352 dmar_inv_iotlb_glob(struct dmar_unit *unit) 353 { 354 int error, reg; 355 356 DMAR_ASSERT_LOCKED(unit); 357 KASSERT(!unit->qi_enabled, ("QI enabled")); 358 359 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap); 360 /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */ 361 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT | 362 DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW); 363 DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) & 364 DMAR_IOTLB_IVT32) == 0)); 365 return (error); 366 } 367 368 /* 369 * Flush the chipset write buffers. See 11.1 "Write Buffer Flushing" 370 * in the architecture specification. 371 */ 372 int 373 dmar_flush_write_bufs(struct dmar_unit *unit) 374 { 375 int error; 376 377 DMAR_ASSERT_LOCKED(unit); 378 379 /* 380 * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported. 381 */ 382 KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0, 383 ("dmar%d: no RWBF", unit->iommu.unit)); 384 385 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF); 386 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS) 387 != 0)); 388 return (error); 389 } 390 391 /* 392 * Some BIOSes protect memory region they reside in by using DMAR to 393 * prevent devices from doing any DMA transactions to that part of RAM. 394 * AMI refers to this as "DMA Control Guarantee". 395 * We need to disable this when address translation is enabled. 396 */ 397 int 398 dmar_disable_protected_regions(struct dmar_unit *unit) 399 { 400 uint32_t reg; 401 int error; 402 403 DMAR_ASSERT_LOCKED(unit); 404 405 /* Check if we support the feature. */ 406 if ((unit->hw_cap & (DMAR_CAP_PLMR | DMAR_CAP_PHMR)) == 0) 407 return (0); 408 409 reg = dmar_read4(unit, DMAR_PMEN_REG); 410 if ((reg & DMAR_PMEN_EPM) == 0) 411 return (0); 412 413 reg &= ~DMAR_PMEN_EPM; 414 dmar_write4(unit, DMAR_PMEN_REG, reg); 415 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_PMEN_REG) & DMAR_PMEN_PRS) 416 != 0)); 417 418 return (error); 419 } 420 421 int 422 dmar_enable_translation(struct dmar_unit *unit) 423 { 424 int error; 425 426 DMAR_ASSERT_LOCKED(unit); 427 unit->hw_gcmd |= DMAR_GCMD_TE; 428 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 429 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) 430 != 0)); 431 return (error); 432 } 433 434 int 435 dmar_disable_translation(struct dmar_unit *unit) 436 { 437 int error; 438 439 DMAR_ASSERT_LOCKED(unit); 440 unit->hw_gcmd &= ~DMAR_GCMD_TE; 441 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 442 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) 443 == 0)); 444 return (error); 445 } 446 447 int 448 dmar_load_irt_ptr(struct dmar_unit *unit) 449 { 450 uint64_t irta, s; 451 int error; 452 453 DMAR_ASSERT_LOCKED(unit); 454 irta = unit->irt_phys; 455 if (DMAR_X2APIC(unit)) 456 irta |= DMAR_IRTA_EIME; 457 s = fls(unit->irte_cnt) - 2; 458 KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK && 459 powerof2(unit->irte_cnt), 460 ("IRTA_REG_S overflow %x", unit->irte_cnt)); 461 irta |= s; 462 dmar_write8(unit, DMAR_IRTA_REG, irta); 463 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP); 464 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS) 465 != 0)); 466 return (error); 467 } 468 469 int 470 dmar_enable_ir(struct dmar_unit *unit) 471 { 472 int error; 473 474 DMAR_ASSERT_LOCKED(unit); 475 unit->hw_gcmd |= DMAR_GCMD_IRE; 476 unit->hw_gcmd &= ~DMAR_GCMD_CFI; 477 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 478 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) 479 != 0)); 480 return (error); 481 } 482 483 int 484 dmar_disable_ir(struct dmar_unit *unit) 485 { 486 int error; 487 488 DMAR_ASSERT_LOCKED(unit); 489 unit->hw_gcmd &= ~DMAR_GCMD_IRE; 490 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 491 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) 492 == 0)); 493 return (error); 494 } 495 496 #define BARRIER_F \ 497 u_int f_done, f_inproc, f_wakeup; \ 498 \ 499 f_done = 1 << (barrier_id * 3); \ 500 f_inproc = 1 << (barrier_id * 3 + 1); \ 501 f_wakeup = 1 << (barrier_id * 3 + 2) 502 503 bool 504 dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id) 505 { 506 BARRIER_F; 507 508 DMAR_LOCK(dmar); 509 if ((dmar->barrier_flags & f_done) != 0) { 510 DMAR_UNLOCK(dmar); 511 return (false); 512 } 513 514 if ((dmar->barrier_flags & f_inproc) != 0) { 515 while ((dmar->barrier_flags & f_inproc) != 0) { 516 dmar->barrier_flags |= f_wakeup; 517 msleep(&dmar->barrier_flags, &dmar->iommu.lock, 0, 518 "dmarb", 0); 519 } 520 KASSERT((dmar->barrier_flags & f_done) != 0, 521 ("dmar%d barrier %d missing done", dmar->iommu.unit, 522 barrier_id)); 523 DMAR_UNLOCK(dmar); 524 return (false); 525 } 526 527 dmar->barrier_flags |= f_inproc; 528 DMAR_UNLOCK(dmar); 529 return (true); 530 } 531 532 void 533 dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id) 534 { 535 BARRIER_F; 536 537 DMAR_ASSERT_LOCKED(dmar); 538 KASSERT((dmar->barrier_flags & (f_done | f_inproc)) == f_inproc, 539 ("dmar%d barrier %d missed entry", dmar->iommu.unit, barrier_id)); 540 dmar->barrier_flags |= f_done; 541 if ((dmar->barrier_flags & f_wakeup) != 0) 542 wakeup(&dmar->barrier_flags); 543 dmar->barrier_flags &= ~(f_inproc | f_wakeup); 544 DMAR_UNLOCK(dmar); 545 } 546 547 int dmar_batch_coalesce = 100; 548 struct timespec dmar_hw_timeout = { 549 .tv_sec = 0, 550 .tv_nsec = 1000000 551 }; 552 553 static const uint64_t d = 1000000000; 554 555 void 556 dmar_update_timeout(uint64_t newval) 557 { 558 559 /* XXXKIB not atomic */ 560 dmar_hw_timeout.tv_sec = newval / d; 561 dmar_hw_timeout.tv_nsec = newval % d; 562 } 563 564 uint64_t 565 dmar_get_timeout(void) 566 { 567 568 return ((uint64_t)dmar_hw_timeout.tv_sec * d + 569 dmar_hw_timeout.tv_nsec); 570 } 571 572 static int 573 dmar_timeout_sysctl(SYSCTL_HANDLER_ARGS) 574 { 575 uint64_t val; 576 int error; 577 578 val = dmar_get_timeout(); 579 error = sysctl_handle_long(oidp, &val, 0, req); 580 if (error != 0 || req->newptr == NULL) 581 return (error); 582 dmar_update_timeout(val); 583 return (error); 584 } 585 586 SYSCTL_INT(_hw_iommu_dmar, OID_AUTO, batch_coalesce, CTLFLAG_RWTUN, 587 &dmar_batch_coalesce, 0, 588 "Number of qi batches between interrupt"); 589 SYSCTL_PROC(_hw_iommu_dmar, OID_AUTO, timeout, 590 CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0, 591 dmar_timeout_sysctl, "QU", 592 "Timeout for command wait, in nanoseconds"); 593