xref: /freebsd/sys/x86/iommu/intel_utils.c (revision 7c1b51d6dc2e165ae7333373513b080f17cf79bd)
1 /*-
2  * Copyright (c) 2013 The FreeBSD Foundation
3  * All rights reserved.
4  *
5  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6  * under sponsorship from the FreeBSD Foundation.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/malloc.h>
38 #include <sys/memdesc.h>
39 #include <sys/mutex.h>
40 #include <sys/proc.h>
41 #include <sys/queue.h>
42 #include <sys/rman.h>
43 #include <sys/rwlock.h>
44 #include <sys/sched.h>
45 #include <sys/sf_buf.h>
46 #include <sys/sysctl.h>
47 #include <sys/systm.h>
48 #include <sys/taskqueue.h>
49 #include <sys/time.h>
50 #include <sys/tree.h>
51 #include <sys/vmem.h>
52 #include <dev/pci/pcivar.h>
53 #include <vm/vm.h>
54 #include <vm/vm_extern.h>
55 #include <vm/vm_kern.h>
56 #include <vm/vm_object.h>
57 #include <vm/vm_page.h>
58 #include <vm/vm_map.h>
59 #include <vm/vm_pageout.h>
60 #include <machine/bus.h>
61 #include <machine/cpu.h>
62 #include <machine/intr_machdep.h>
63 #include <x86/include/apicvar.h>
64 #include <x86/include/busdma_impl.h>
65 #include <x86/iommu/intel_reg.h>
66 #include <x86/iommu/busdma_dmar.h>
67 #include <x86/iommu/intel_dmar.h>
68 
69 u_int
70 dmar_nd2mask(u_int nd)
71 {
72 	static const u_int masks[] = {
73 		0x000f,	/* nd == 0 */
74 		0x002f,	/* nd == 1 */
75 		0x00ff,	/* nd == 2 */
76 		0x02ff,	/* nd == 3 */
77 		0x0fff,	/* nd == 4 */
78 		0x2fff,	/* nd == 5 */
79 		0xffff,	/* nd == 6 */
80 		0x0000,	/* nd == 7 reserved */
81 	};
82 
83 	KASSERT(nd <= 6, ("number of domains %d", nd));
84 	return (masks[nd]);
85 }
86 
87 static const struct sagaw_bits_tag {
88 	int agaw;
89 	int cap;
90 	int awlvl;
91 	int pglvl;
92 } sagaw_bits[] = {
93 	{.agaw = 30, .cap = DMAR_CAP_SAGAW_2LVL, .awlvl = DMAR_CTX2_AW_2LVL,
94 	    .pglvl = 2},
95 	{.agaw = 39, .cap = DMAR_CAP_SAGAW_3LVL, .awlvl = DMAR_CTX2_AW_3LVL,
96 	    .pglvl = 3},
97 	{.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL,
98 	    .pglvl = 4},
99 	{.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL,
100 	    .pglvl = 5},
101 	{.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL,
102 	    .pglvl = 6}
103 };
104 
105 bool
106 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl)
107 {
108 	int i;
109 
110 	for (i = 0; i < nitems(sagaw_bits); i++) {
111 		if (sagaw_bits[i].pglvl != pglvl)
112 			continue;
113 		if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
114 			return (true);
115 	}
116 	return (false);
117 }
118 
119 int
120 domain_set_agaw(struct dmar_domain *domain, int mgaw)
121 {
122 	int sagaw, i;
123 
124 	domain->mgaw = mgaw;
125 	sagaw = DMAR_CAP_SAGAW(domain->dmar->hw_cap);
126 	for (i = 0; i < nitems(sagaw_bits); i++) {
127 		if (sagaw_bits[i].agaw >= mgaw) {
128 			domain->agaw = sagaw_bits[i].agaw;
129 			domain->pglvl = sagaw_bits[i].pglvl;
130 			domain->awlvl = sagaw_bits[i].awlvl;
131 			return (0);
132 		}
133 	}
134 	device_printf(domain->dmar->dev,
135 	    "context request mgaw %d: no agaw found, sagaw %x\n",
136 	    mgaw, sagaw);
137 	return (EINVAL);
138 }
139 
140 /*
141  * Find a best fit mgaw for the given maxaddr:
142  *   - if allow_less is false, must find sagaw which maps all requested
143  *     addresses (used by identity mappings);
144  *   - if allow_less is true, and no supported sagaw can map all requested
145  *     address space, accept the biggest sagaw, whatever is it.
146  */
147 int
148 dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr, bool allow_less)
149 {
150 	int i;
151 
152 	for (i = 0; i < nitems(sagaw_bits); i++) {
153 		if ((1ULL << sagaw_bits[i].agaw) >= maxaddr &&
154 		    (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
155 			break;
156 	}
157 	if (allow_less && i == nitems(sagaw_bits)) {
158 		do {
159 			i--;
160 		} while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap)
161 		    == 0);
162 	}
163 	if (i < nitems(sagaw_bits))
164 		return (sagaw_bits[i].agaw);
165 	KASSERT(0, ("no mgaw for maxaddr %jx allow_less %d",
166 	    (uintmax_t) maxaddr, allow_less));
167 	return (-1);
168 }
169 
170 /*
171  * Calculate the total amount of page table pages needed to map the
172  * whole bus address space on the context with the selected agaw.
173  */
174 vm_pindex_t
175 pglvl_max_pages(int pglvl)
176 {
177 	vm_pindex_t res;
178 	int i;
179 
180 	for (res = 0, i = pglvl; i > 0; i--) {
181 		res *= DMAR_NPTEPG;
182 		res++;
183 	}
184 	return (res);
185 }
186 
187 /*
188  * Return true if the page table level lvl supports the superpage for
189  * the context ctx.
190  */
191 int
192 domain_is_sp_lvl(struct dmar_domain *domain, int lvl)
193 {
194 	int alvl, cap_sps;
195 	static const int sagaw_sp[] = {
196 		DMAR_CAP_SPS_2M,
197 		DMAR_CAP_SPS_1G,
198 		DMAR_CAP_SPS_512G,
199 		DMAR_CAP_SPS_1T
200 	};
201 
202 	alvl = domain->pglvl - lvl - 1;
203 	cap_sps = DMAR_CAP_SPS(domain->dmar->hw_cap);
204 	return (alvl < nitems(sagaw_sp) && (sagaw_sp[alvl] & cap_sps) != 0);
205 }
206 
207 dmar_gaddr_t
208 pglvl_page_size(int total_pglvl, int lvl)
209 {
210 	int rlvl;
211 	static const dmar_gaddr_t pg_sz[] = {
212 		(dmar_gaddr_t)DMAR_PAGE_SIZE,
213 		(dmar_gaddr_t)DMAR_PAGE_SIZE << DMAR_NPTEPGSHIFT,
214 		(dmar_gaddr_t)DMAR_PAGE_SIZE << (2 * DMAR_NPTEPGSHIFT),
215 		(dmar_gaddr_t)DMAR_PAGE_SIZE << (3 * DMAR_NPTEPGSHIFT),
216 		(dmar_gaddr_t)DMAR_PAGE_SIZE << (4 * DMAR_NPTEPGSHIFT),
217 		(dmar_gaddr_t)DMAR_PAGE_SIZE << (5 * DMAR_NPTEPGSHIFT)
218 	};
219 
220 	KASSERT(lvl >= 0 && lvl < total_pglvl,
221 	    ("total %d lvl %d", total_pglvl, lvl));
222 	rlvl = total_pglvl - lvl - 1;
223 	KASSERT(rlvl < nitems(pg_sz), ("sizeof pg_sz lvl %d", lvl));
224 	return (pg_sz[rlvl]);
225 }
226 
227 dmar_gaddr_t
228 domain_page_size(struct dmar_domain *domain, int lvl)
229 {
230 
231 	return (pglvl_page_size(domain->pglvl, lvl));
232 }
233 
234 int
235 calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size,
236     dmar_gaddr_t *isizep)
237 {
238 	dmar_gaddr_t isize;
239 	int am;
240 
241 	for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) {
242 		isize = 1ULL << (am + DMAR_PAGE_SHIFT);
243 		if ((base & (isize - 1)) == 0 && size >= isize)
244 			break;
245 		if (am == 0)
246 			break;
247 	}
248 	*isizep = isize;
249 	return (am);
250 }
251 
252 dmar_haddr_t dmar_high;
253 int haw;
254 int dmar_tbl_pagecnt;
255 
256 vm_page_t
257 dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags)
258 {
259 	vm_page_t m;
260 	int zeroed;
261 
262 	zeroed = (flags & DMAR_PGF_ZERO) != 0 ? VM_ALLOC_ZERO : 0;
263 	for (;;) {
264 		if ((flags & DMAR_PGF_OBJL) == 0)
265 			VM_OBJECT_WLOCK(obj);
266 		m = vm_page_lookup(obj, idx);
267 		if ((flags & DMAR_PGF_NOALLOC) != 0 || m != NULL) {
268 			if ((flags & DMAR_PGF_OBJL) == 0)
269 				VM_OBJECT_WUNLOCK(obj);
270 			break;
271 		}
272 		m = vm_page_alloc_contig(obj, idx, VM_ALLOC_NOBUSY |
273 		    VM_ALLOC_SYSTEM | VM_ALLOC_NODUMP | zeroed, 1, 0,
274 		    dmar_high, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
275 		if ((flags & DMAR_PGF_OBJL) == 0)
276 			VM_OBJECT_WUNLOCK(obj);
277 		if (m != NULL) {
278 			if (zeroed && (m->flags & PG_ZERO) == 0)
279 				pmap_zero_page(m);
280 			atomic_add_int(&dmar_tbl_pagecnt, 1);
281 			break;
282 		}
283 		if ((flags & DMAR_PGF_WAITOK) == 0)
284 			break;
285 		if ((flags & DMAR_PGF_OBJL) != 0)
286 			VM_OBJECT_WUNLOCK(obj);
287 		VM_WAIT;
288 		if ((flags & DMAR_PGF_OBJL) != 0)
289 			VM_OBJECT_WLOCK(obj);
290 	}
291 	return (m);
292 }
293 
294 void
295 dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags)
296 {
297 	vm_page_t m;
298 
299 	if ((flags & DMAR_PGF_OBJL) == 0)
300 		VM_OBJECT_WLOCK(obj);
301 	m = vm_page_lookup(obj, idx);
302 	if (m != NULL) {
303 		vm_page_free(m);
304 		atomic_subtract_int(&dmar_tbl_pagecnt, 1);
305 	}
306 	if ((flags & DMAR_PGF_OBJL) == 0)
307 		VM_OBJECT_WUNLOCK(obj);
308 }
309 
310 void *
311 dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
312     struct sf_buf **sf)
313 {
314 	vm_page_t m;
315 	bool allocated;
316 
317 	if ((flags & DMAR_PGF_OBJL) == 0)
318 		VM_OBJECT_WLOCK(obj);
319 	m = vm_page_lookup(obj, idx);
320 	if (m == NULL && (flags & DMAR_PGF_ALLOC) != 0) {
321 		m = dmar_pgalloc(obj, idx, flags | DMAR_PGF_OBJL);
322 		allocated = true;
323 	} else
324 		allocated = false;
325 	if (m == NULL) {
326 		if ((flags & DMAR_PGF_OBJL) == 0)
327 			VM_OBJECT_WUNLOCK(obj);
328 		return (NULL);
329 	}
330 	/* Sleepable allocations cannot fail. */
331 	if ((flags & DMAR_PGF_WAITOK) != 0)
332 		VM_OBJECT_WUNLOCK(obj);
333 	sched_pin();
334 	*sf = sf_buf_alloc(m, SFB_CPUPRIVATE | ((flags & DMAR_PGF_WAITOK)
335 	    == 0 ? SFB_NOWAIT : 0));
336 	if (*sf == NULL) {
337 		sched_unpin();
338 		if (allocated) {
339 			VM_OBJECT_ASSERT_WLOCKED(obj);
340 			dmar_pgfree(obj, m->pindex, flags | DMAR_PGF_OBJL);
341 		}
342 		if ((flags & DMAR_PGF_OBJL) == 0)
343 			VM_OBJECT_WUNLOCK(obj);
344 		return (NULL);
345 	}
346 	if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) ==
347 	    (DMAR_PGF_WAITOK | DMAR_PGF_OBJL))
348 		VM_OBJECT_WLOCK(obj);
349 	else if ((flags & (DMAR_PGF_WAITOK | DMAR_PGF_OBJL)) == 0)
350 		VM_OBJECT_WUNLOCK(obj);
351 	return ((void *)sf_buf_kva(*sf));
352 }
353 
354 void
355 dmar_unmap_pgtbl(struct sf_buf *sf)
356 {
357 
358 	sf_buf_free(sf);
359 	sched_unpin();
360 }
361 
362 static void
363 dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz)
364 {
365 
366 	if (DMAR_IS_COHERENT(unit))
367 		return;
368 	/*
369 	 * If DMAR does not snoop paging structures accesses, flush
370 	 * CPU cache to memory.
371 	 */
372 	pmap_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz,
373 	    TRUE);
374 }
375 
376 void
377 dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst)
378 {
379 
380 	dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
381 }
382 
383 void
384 dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst)
385 {
386 
387 	dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
388 }
389 
390 void
391 dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst)
392 {
393 
394 	dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
395 }
396 
397 /*
398  * Load the root entry pointer into the hardware, busily waiting for
399  * the completion.
400  */
401 int
402 dmar_load_root_entry_ptr(struct dmar_unit *unit)
403 {
404 	vm_page_t root_entry;
405 	int error;
406 
407 	/*
408 	 * Access to the GCMD register must be serialized while the
409 	 * command is submitted.
410 	 */
411 	DMAR_ASSERT_LOCKED(unit);
412 
413 	VM_OBJECT_RLOCK(unit->ctx_obj);
414 	root_entry = vm_page_lookup(unit->ctx_obj, 0);
415 	VM_OBJECT_RUNLOCK(unit->ctx_obj);
416 	dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry));
417 	dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP);
418 	DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS)
419 	    != 0));
420 	return (error);
421 }
422 
423 /*
424  * Globally invalidate the context entries cache, busily waiting for
425  * the completion.
426  */
427 int
428 dmar_inv_ctx_glob(struct dmar_unit *unit)
429 {
430 	int error;
431 
432 	/*
433 	 * Access to the CCMD register must be serialized while the
434 	 * command is submitted.
435 	 */
436 	DMAR_ASSERT_LOCKED(unit);
437 	KASSERT(!unit->qi_enabled, ("QI enabled"));
438 
439 	/*
440 	 * The DMAR_CCMD_ICC bit in the upper dword should be written
441 	 * after the low dword write is completed.  Amd64
442 	 * dmar_write8() does not have this issue, i386 dmar_write8()
443 	 * writes the upper dword last.
444 	 */
445 	dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB);
446 	DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32)
447 	    == 0));
448 	return (error);
449 }
450 
451 /*
452  * Globally invalidate the IOTLB, busily waiting for the completion.
453  */
454 int
455 dmar_inv_iotlb_glob(struct dmar_unit *unit)
456 {
457 	int error, reg;
458 
459 	DMAR_ASSERT_LOCKED(unit);
460 	KASSERT(!unit->qi_enabled, ("QI enabled"));
461 
462 	reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap);
463 	/* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */
464 	dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT |
465 	    DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW);
466 	DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) &
467 	    DMAR_IOTLB_IVT32) == 0));
468 	return (error);
469 }
470 
471 /*
472  * Flush the chipset write buffers.  See 11.1 "Write Buffer Flushing"
473  * in the architecture specification.
474  */
475 int
476 dmar_flush_write_bufs(struct dmar_unit *unit)
477 {
478 	int error;
479 
480 	DMAR_ASSERT_LOCKED(unit);
481 
482 	/*
483 	 * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported.
484 	 */
485 	KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0,
486 	    ("dmar%d: no RWBF", unit->unit));
487 
488 	dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF);
489 	DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS)
490 	    != 0));
491 	return (error);
492 }
493 
494 int
495 dmar_enable_translation(struct dmar_unit *unit)
496 {
497 	int error;
498 
499 	DMAR_ASSERT_LOCKED(unit);
500 	unit->hw_gcmd |= DMAR_GCMD_TE;
501 	dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
502 	DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES)
503 	    != 0));
504 	return (error);
505 }
506 
507 int
508 dmar_disable_translation(struct dmar_unit *unit)
509 {
510 	int error;
511 
512 	DMAR_ASSERT_LOCKED(unit);
513 	unit->hw_gcmd &= ~DMAR_GCMD_TE;
514 	dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
515 	DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES)
516 	    == 0));
517 	return (error);
518 }
519 
520 int
521 dmar_load_irt_ptr(struct dmar_unit *unit)
522 {
523 	uint64_t irta, s;
524 	int error;
525 
526 	DMAR_ASSERT_LOCKED(unit);
527 	irta = unit->irt_phys;
528 	if (DMAR_X2APIC(unit))
529 		irta |= DMAR_IRTA_EIME;
530 	s = fls(unit->irte_cnt) - 2;
531 	KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK &&
532 	    powerof2(unit->irte_cnt),
533 	    ("IRTA_REG_S overflow %x", unit->irte_cnt));
534 	irta |= s;
535 	dmar_write8(unit, DMAR_IRTA_REG, irta);
536 	dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP);
537 	DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS)
538 	    != 0));
539 	return (error);
540 }
541 
542 int
543 dmar_enable_ir(struct dmar_unit *unit)
544 {
545 	int error;
546 
547 	DMAR_ASSERT_LOCKED(unit);
548 	unit->hw_gcmd |= DMAR_GCMD_IRE;
549 	unit->hw_gcmd &= ~DMAR_GCMD_CFI;
550 	dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
551 	DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES)
552 	    != 0));
553 	return (error);
554 }
555 
556 int
557 dmar_disable_ir(struct dmar_unit *unit)
558 {
559 	int error;
560 
561 	DMAR_ASSERT_LOCKED(unit);
562 	unit->hw_gcmd &= ~DMAR_GCMD_IRE;
563 	dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
564 	DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES)
565 	    == 0));
566 	return (error);
567 }
568 
569 #define BARRIER_F				\
570 	u_int f_done, f_inproc, f_wakeup;	\
571 						\
572 	f_done = 1 << (barrier_id * 3);		\
573 	f_inproc = 1 << (barrier_id * 3 + 1);	\
574 	f_wakeup = 1 << (barrier_id * 3 + 2)
575 
576 bool
577 dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id)
578 {
579 	BARRIER_F;
580 
581 	DMAR_LOCK(dmar);
582 	if ((dmar->barrier_flags & f_done) != 0) {
583 		DMAR_UNLOCK(dmar);
584 		return (false);
585 	}
586 
587 	if ((dmar->barrier_flags & f_inproc) != 0) {
588 		while ((dmar->barrier_flags & f_inproc) != 0) {
589 			dmar->barrier_flags |= f_wakeup;
590 			msleep(&dmar->barrier_flags, &dmar->lock, 0,
591 			    "dmarb", 0);
592 		}
593 		KASSERT((dmar->barrier_flags & f_done) != 0,
594 		    ("dmar%d barrier %d missing done", dmar->unit, barrier_id));
595 		DMAR_UNLOCK(dmar);
596 		return (false);
597 	}
598 
599 	dmar->barrier_flags |= f_inproc;
600 	DMAR_UNLOCK(dmar);
601 	return (true);
602 }
603 
604 void
605 dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id)
606 {
607 	BARRIER_F;
608 
609 	DMAR_ASSERT_LOCKED(dmar);
610 	KASSERT((dmar->barrier_flags & (f_done | f_inproc)) == f_inproc,
611 	    ("dmar%d barrier %d missed entry", dmar->unit, barrier_id));
612 	dmar->barrier_flags |= f_done;
613 	if ((dmar->barrier_flags & f_wakeup) != 0)
614 		wakeup(&dmar->barrier_flags);
615 	dmar->barrier_flags &= ~(f_inproc | f_wakeup);
616 	DMAR_UNLOCK(dmar);
617 }
618 
619 int dmar_match_verbose;
620 int dmar_batch_coalesce = 100;
621 struct timespec dmar_hw_timeout = {
622 	.tv_sec = 0,
623 	.tv_nsec = 1000000
624 };
625 
626 static const uint64_t d = 1000000000;
627 
628 void
629 dmar_update_timeout(uint64_t newval)
630 {
631 
632 	/* XXXKIB not atomic */
633 	dmar_hw_timeout.tv_sec = newval / d;
634 	dmar_hw_timeout.tv_nsec = newval % d;
635 }
636 
637 uint64_t
638 dmar_get_timeout(void)
639 {
640 
641 	return ((uint64_t)dmar_hw_timeout.tv_sec * d +
642 	    dmar_hw_timeout.tv_nsec);
643 }
644 
645 static int
646 dmar_timeout_sysctl(SYSCTL_HANDLER_ARGS)
647 {
648 	uint64_t val;
649 	int error;
650 
651 	val = dmar_get_timeout();
652 	error = sysctl_handle_long(oidp, &val, 0, req);
653 	if (error != 0 || req->newptr == NULL)
654 		return (error);
655 	dmar_update_timeout(val);
656 	return (error);
657 }
658 
659 static SYSCTL_NODE(_hw, OID_AUTO, dmar, CTLFLAG_RD, NULL, "");
660 SYSCTL_INT(_hw_dmar, OID_AUTO, tbl_pagecnt, CTLFLAG_RD,
661     &dmar_tbl_pagecnt, 0,
662     "Count of pages used for DMAR pagetables");
663 SYSCTL_INT(_hw_dmar, OID_AUTO, match_verbose, CTLFLAG_RWTUN,
664     &dmar_match_verbose, 0,
665     "Verbose matching of the PCI devices to DMAR paths");
666 SYSCTL_INT(_hw_dmar, OID_AUTO, batch_coalesce, CTLFLAG_RWTUN,
667     &dmar_batch_coalesce, 0,
668     "Number of qi batches between interrupt");
669 SYSCTL_PROC(_hw_dmar, OID_AUTO, timeout,
670     CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0,
671     dmar_timeout_sysctl, "QU",
672     "Timeout for command wait, in nanoseconds");
673 #ifdef INVARIANTS
674 int dmar_check_free;
675 SYSCTL_INT(_hw_dmar, OID_AUTO, check_free, CTLFLAG_RWTUN,
676     &dmar_check_free, 0,
677     "Check the GPA RBtree for free_down and free_after validity");
678 #endif
679 
680