1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/memdesc.h> 40 #include <sys/mutex.h> 41 #include <sys/proc.h> 42 #include <sys/queue.h> 43 #include <sys/rman.h> 44 #include <sys/rwlock.h> 45 #include <sys/sched.h> 46 #include <sys/sf_buf.h> 47 #include <sys/sysctl.h> 48 #include <sys/systm.h> 49 #include <sys/taskqueue.h> 50 #include <sys/time.h> 51 #include <sys/tree.h> 52 #include <sys/vmem.h> 53 #include <vm/vm.h> 54 #include <vm/vm_extern.h> 55 #include <vm/vm_kern.h> 56 #include <vm/vm_object.h> 57 #include <vm/vm_page.h> 58 #include <vm/vm_map.h> 59 #include <vm/vm_pageout.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <machine/bus.h> 63 #include <machine/cpu.h> 64 #include <machine/intr_machdep.h> 65 #include <x86/include/apicvar.h> 66 #include <x86/include/busdma_impl.h> 67 #include <dev/iommu/busdma_iommu.h> 68 #include <x86/iommu/intel_reg.h> 69 #include <x86/iommu/intel_dmar.h> 70 71 u_int 72 dmar_nd2mask(u_int nd) 73 { 74 static const u_int masks[] = { 75 0x000f, /* nd == 0 */ 76 0x002f, /* nd == 1 */ 77 0x00ff, /* nd == 2 */ 78 0x02ff, /* nd == 3 */ 79 0x0fff, /* nd == 4 */ 80 0x2fff, /* nd == 5 */ 81 0xffff, /* nd == 6 */ 82 0x0000, /* nd == 7 reserved */ 83 }; 84 85 KASSERT(nd <= 6, ("number of domains %d", nd)); 86 return (masks[nd]); 87 } 88 89 static const struct sagaw_bits_tag { 90 int agaw; 91 int cap; 92 int awlvl; 93 int pglvl; 94 } sagaw_bits[] = { 95 {.agaw = 30, .cap = DMAR_CAP_SAGAW_2LVL, .awlvl = DMAR_CTX2_AW_2LVL, 96 .pglvl = 2}, 97 {.agaw = 39, .cap = DMAR_CAP_SAGAW_3LVL, .awlvl = DMAR_CTX2_AW_3LVL, 98 .pglvl = 3}, 99 {.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL, 100 .pglvl = 4}, 101 {.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL, 102 .pglvl = 5}, 103 {.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL, 104 .pglvl = 6} 105 }; 106 107 bool 108 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl) 109 { 110 int i; 111 112 for (i = 0; i < nitems(sagaw_bits); i++) { 113 if (sagaw_bits[i].pglvl != pglvl) 114 continue; 115 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) 116 return (true); 117 } 118 return (false); 119 } 120 121 int 122 domain_set_agaw(struct dmar_domain *domain, int mgaw) 123 { 124 int sagaw, i; 125 126 domain->mgaw = mgaw; 127 sagaw = DMAR_CAP_SAGAW(domain->dmar->hw_cap); 128 for (i = 0; i < nitems(sagaw_bits); i++) { 129 if (sagaw_bits[i].agaw >= mgaw) { 130 domain->agaw = sagaw_bits[i].agaw; 131 domain->pglvl = sagaw_bits[i].pglvl; 132 domain->awlvl = sagaw_bits[i].awlvl; 133 return (0); 134 } 135 } 136 device_printf(domain->dmar->dev, 137 "context request mgaw %d: no agaw found, sagaw %x\n", 138 mgaw, sagaw); 139 return (EINVAL); 140 } 141 142 /* 143 * Find a best fit mgaw for the given maxaddr: 144 * - if allow_less is false, must find sagaw which maps all requested 145 * addresses (used by identity mappings); 146 * - if allow_less is true, and no supported sagaw can map all requested 147 * address space, accept the biggest sagaw, whatever is it. 148 */ 149 int 150 dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, bool allow_less) 151 { 152 int i; 153 154 for (i = 0; i < nitems(sagaw_bits); i++) { 155 if ((1ULL << sagaw_bits[i].agaw) >= maxaddr && 156 (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) 157 break; 158 } 159 if (allow_less && i == nitems(sagaw_bits)) { 160 do { 161 i--; 162 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) 163 == 0); 164 } 165 if (i < nitems(sagaw_bits)) 166 return (sagaw_bits[i].agaw); 167 KASSERT(0, ("no mgaw for maxaddr %jx allow_less %d", 168 (uintmax_t) maxaddr, allow_less)); 169 return (-1); 170 } 171 172 /* 173 * Calculate the total amount of page table pages needed to map the 174 * whole bus address space on the context with the selected agaw. 175 */ 176 vm_pindex_t 177 pglvl_max_pages(int pglvl) 178 { 179 vm_pindex_t res; 180 int i; 181 182 for (res = 0, i = pglvl; i > 0; i--) { 183 res *= DMAR_NPTEPG; 184 res++; 185 } 186 return (res); 187 } 188 189 /* 190 * Return true if the page table level lvl supports the superpage for 191 * the context ctx. 192 */ 193 int 194 domain_is_sp_lvl(struct dmar_domain *domain, int lvl) 195 { 196 int alvl, cap_sps; 197 static const int sagaw_sp[] = { 198 DMAR_CAP_SPS_2M, 199 DMAR_CAP_SPS_1G, 200 DMAR_CAP_SPS_512G, 201 DMAR_CAP_SPS_1T 202 }; 203 204 alvl = domain->pglvl - lvl - 1; 205 cap_sps = DMAR_CAP_SPS(domain->dmar->hw_cap); 206 return (alvl < nitems(sagaw_sp) && (sagaw_sp[alvl] & cap_sps) != 0); 207 } 208 209 iommu_gaddr_t 210 pglvl_page_size(int total_pglvl, int lvl) 211 { 212 int rlvl; 213 static const iommu_gaddr_t pg_sz[] = { 214 (iommu_gaddr_t)DMAR_PAGE_SIZE, 215 (iommu_gaddr_t)DMAR_PAGE_SIZE << DMAR_NPTEPGSHIFT, 216 (iommu_gaddr_t)DMAR_PAGE_SIZE << (2 * DMAR_NPTEPGSHIFT), 217 (iommu_gaddr_t)DMAR_PAGE_SIZE << (3 * DMAR_NPTEPGSHIFT), 218 (iommu_gaddr_t)DMAR_PAGE_SIZE << (4 * DMAR_NPTEPGSHIFT), 219 (iommu_gaddr_t)DMAR_PAGE_SIZE << (5 * DMAR_NPTEPGSHIFT) 220 }; 221 222 KASSERT(lvl >= 0 && lvl < total_pglvl, 223 ("total %d lvl %d", total_pglvl, lvl)); 224 rlvl = total_pglvl - lvl - 1; 225 KASSERT(rlvl < nitems(pg_sz), ("sizeof pg_sz lvl %d", lvl)); 226 return (pg_sz[rlvl]); 227 } 228 229 iommu_gaddr_t 230 domain_page_size(struct dmar_domain *domain, int lvl) 231 { 232 233 return (pglvl_page_size(domain->pglvl, lvl)); 234 } 235 236 int 237 calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size, 238 iommu_gaddr_t *isizep) 239 { 240 iommu_gaddr_t isize; 241 int am; 242 243 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) { 244 isize = 1ULL << (am + DMAR_PAGE_SHIFT); 245 if ((base & (isize - 1)) == 0 && size >= isize) 246 break; 247 if (am == 0) 248 break; 249 } 250 *isizep = isize; 251 return (am); 252 } 253 254 iommu_haddr_t dmar_high; 255 int haw; 256 int dmar_tbl_pagecnt; 257 258 vm_page_t 259 dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags) 260 { 261 vm_page_t m; 262 int zeroed, aflags; 263 264 zeroed = (flags & IOMMU_PGF_ZERO) != 0 ? VM_ALLOC_ZERO : 0; 265 aflags = zeroed | VM_ALLOC_NOBUSY | VM_ALLOC_SYSTEM | VM_ALLOC_NODUMP | 266 ((flags & IOMMU_PGF_WAITOK) != 0 ? VM_ALLOC_WAITFAIL : 267 VM_ALLOC_NOWAIT); 268 for (;;) { 269 if ((flags & IOMMU_PGF_OBJL) == 0) 270 VM_OBJECT_WLOCK(obj); 271 m = vm_page_lookup(obj, idx); 272 if ((flags & IOMMU_PGF_NOALLOC) != 0 || m != NULL) { 273 if ((flags & IOMMU_PGF_OBJL) == 0) 274 VM_OBJECT_WUNLOCK(obj); 275 break; 276 } 277 m = vm_page_alloc_contig(obj, idx, aflags, 1, 0, 278 dmar_high, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 279 if ((flags & IOMMU_PGF_OBJL) == 0) 280 VM_OBJECT_WUNLOCK(obj); 281 if (m != NULL) { 282 if (zeroed && (m->flags & PG_ZERO) == 0) 283 pmap_zero_page(m); 284 atomic_add_int(&dmar_tbl_pagecnt, 1); 285 break; 286 } 287 if ((flags & IOMMU_PGF_WAITOK) == 0) 288 break; 289 } 290 return (m); 291 } 292 293 void 294 dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags) 295 { 296 vm_page_t m; 297 298 if ((flags & IOMMU_PGF_OBJL) == 0) 299 VM_OBJECT_WLOCK(obj); 300 m = vm_page_grab(obj, idx, VM_ALLOC_NOCREAT); 301 if (m != NULL) { 302 vm_page_free(m); 303 atomic_subtract_int(&dmar_tbl_pagecnt, 1); 304 } 305 if ((flags & IOMMU_PGF_OBJL) == 0) 306 VM_OBJECT_WUNLOCK(obj); 307 } 308 309 void * 310 dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 311 struct sf_buf **sf) 312 { 313 vm_page_t m; 314 bool allocated; 315 316 if ((flags & IOMMU_PGF_OBJL) == 0) 317 VM_OBJECT_WLOCK(obj); 318 m = vm_page_lookup(obj, idx); 319 if (m == NULL && (flags & IOMMU_PGF_ALLOC) != 0) { 320 m = dmar_pgalloc(obj, idx, flags | IOMMU_PGF_OBJL); 321 allocated = true; 322 } else 323 allocated = false; 324 if (m == NULL) { 325 if ((flags & IOMMU_PGF_OBJL) == 0) 326 VM_OBJECT_WUNLOCK(obj); 327 return (NULL); 328 } 329 /* Sleepable allocations cannot fail. */ 330 if ((flags & IOMMU_PGF_WAITOK) != 0) 331 VM_OBJECT_WUNLOCK(obj); 332 sched_pin(); 333 *sf = sf_buf_alloc(m, SFB_CPUPRIVATE | ((flags & IOMMU_PGF_WAITOK) 334 == 0 ? SFB_NOWAIT : 0)); 335 if (*sf == NULL) { 336 sched_unpin(); 337 if (allocated) { 338 VM_OBJECT_ASSERT_WLOCKED(obj); 339 dmar_pgfree(obj, m->pindex, flags | IOMMU_PGF_OBJL); 340 } 341 if ((flags & IOMMU_PGF_OBJL) == 0) 342 VM_OBJECT_WUNLOCK(obj); 343 return (NULL); 344 } 345 if ((flags & (IOMMU_PGF_WAITOK | IOMMU_PGF_OBJL)) == 346 (IOMMU_PGF_WAITOK | IOMMU_PGF_OBJL)) 347 VM_OBJECT_WLOCK(obj); 348 else if ((flags & (IOMMU_PGF_WAITOK | IOMMU_PGF_OBJL)) == 0) 349 VM_OBJECT_WUNLOCK(obj); 350 return ((void *)sf_buf_kva(*sf)); 351 } 352 353 void 354 dmar_unmap_pgtbl(struct sf_buf *sf) 355 { 356 357 sf_buf_free(sf); 358 sched_unpin(); 359 } 360 361 static void 362 dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz) 363 { 364 365 if (DMAR_IS_COHERENT(unit)) 366 return; 367 /* 368 * If DMAR does not snoop paging structures accesses, flush 369 * CPU cache to memory. 370 */ 371 pmap_force_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz); 372 } 373 374 void 375 dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst) 376 { 377 378 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 379 } 380 381 void 382 dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst) 383 { 384 385 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 386 } 387 388 void 389 dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst) 390 { 391 392 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); 393 } 394 395 /* 396 * Load the root entry pointer into the hardware, busily waiting for 397 * the completion. 398 */ 399 int 400 dmar_load_root_entry_ptr(struct dmar_unit *unit) 401 { 402 vm_page_t root_entry; 403 int error; 404 405 /* 406 * Access to the GCMD register must be serialized while the 407 * command is submitted. 408 */ 409 DMAR_ASSERT_LOCKED(unit); 410 411 VM_OBJECT_RLOCK(unit->ctx_obj); 412 root_entry = vm_page_lookup(unit->ctx_obj, 0); 413 VM_OBJECT_RUNLOCK(unit->ctx_obj); 414 dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry)); 415 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP); 416 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS) 417 != 0)); 418 return (error); 419 } 420 421 /* 422 * Globally invalidate the context entries cache, busily waiting for 423 * the completion. 424 */ 425 int 426 dmar_inv_ctx_glob(struct dmar_unit *unit) 427 { 428 int error; 429 430 /* 431 * Access to the CCMD register must be serialized while the 432 * command is submitted. 433 */ 434 DMAR_ASSERT_LOCKED(unit); 435 KASSERT(!unit->qi_enabled, ("QI enabled")); 436 437 /* 438 * The DMAR_CCMD_ICC bit in the upper dword should be written 439 * after the low dword write is completed. Amd64 440 * dmar_write8() does not have this issue, i386 dmar_write8() 441 * writes the upper dword last. 442 */ 443 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB); 444 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32) 445 == 0)); 446 return (error); 447 } 448 449 /* 450 * Globally invalidate the IOTLB, busily waiting for the completion. 451 */ 452 int 453 dmar_inv_iotlb_glob(struct dmar_unit *unit) 454 { 455 int error, reg; 456 457 DMAR_ASSERT_LOCKED(unit); 458 KASSERT(!unit->qi_enabled, ("QI enabled")); 459 460 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap); 461 /* See a comment about DMAR_CCMD_ICC in dmar_inv_ctx_glob. */ 462 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT | 463 DMAR_IOTLB_IIRG_GLB | DMAR_IOTLB_DR | DMAR_IOTLB_DW); 464 DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) & 465 DMAR_IOTLB_IVT32) == 0)); 466 return (error); 467 } 468 469 /* 470 * Flush the chipset write buffers. See 11.1 "Write Buffer Flushing" 471 * in the architecture specification. 472 */ 473 int 474 dmar_flush_write_bufs(struct dmar_unit *unit) 475 { 476 int error; 477 478 DMAR_ASSERT_LOCKED(unit); 479 480 /* 481 * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported. 482 */ 483 KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0, 484 ("dmar%d: no RWBF", unit->iommu.unit)); 485 486 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF); 487 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS) 488 != 0)); 489 return (error); 490 } 491 492 /* 493 * Some BIOSes protect memory region they reside in by using DMAR to 494 * prevent devices from doing any DMA transactions to that part of RAM. 495 * AMI refers to this as "DMA Control Guarantee". 496 * We need to disable this when address translation is enabled. 497 */ 498 int 499 dmar_disable_protected_regions(struct dmar_unit *unit) 500 { 501 uint32_t reg; 502 int error; 503 504 DMAR_ASSERT_LOCKED(unit); 505 506 /* Check if we support the feature. */ 507 if ((unit->hw_cap & (DMAR_CAP_PLMR | DMAR_CAP_PHMR)) == 0) 508 return (0); 509 510 reg = dmar_read4(unit, DMAR_PMEN_REG); 511 if ((reg & DMAR_PMEN_EPM) == 0) 512 return (0); 513 514 reg &= ~DMAR_PMEN_EPM; 515 dmar_write4(unit, DMAR_PMEN_REG, reg); 516 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_PMEN_REG) & DMAR_PMEN_PRS) 517 != 0)); 518 519 return (error); 520 } 521 522 int 523 dmar_enable_translation(struct dmar_unit *unit) 524 { 525 int error; 526 527 DMAR_ASSERT_LOCKED(unit); 528 unit->hw_gcmd |= DMAR_GCMD_TE; 529 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 530 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) 531 != 0)); 532 return (error); 533 } 534 535 int 536 dmar_disable_translation(struct dmar_unit *unit) 537 { 538 int error; 539 540 DMAR_ASSERT_LOCKED(unit); 541 unit->hw_gcmd &= ~DMAR_GCMD_TE; 542 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 543 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) 544 == 0)); 545 return (error); 546 } 547 548 int 549 dmar_load_irt_ptr(struct dmar_unit *unit) 550 { 551 uint64_t irta, s; 552 int error; 553 554 DMAR_ASSERT_LOCKED(unit); 555 irta = unit->irt_phys; 556 if (DMAR_X2APIC(unit)) 557 irta |= DMAR_IRTA_EIME; 558 s = fls(unit->irte_cnt) - 2; 559 KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK && 560 powerof2(unit->irte_cnt), 561 ("IRTA_REG_S overflow %x", unit->irte_cnt)); 562 irta |= s; 563 dmar_write8(unit, DMAR_IRTA_REG, irta); 564 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP); 565 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS) 566 != 0)); 567 return (error); 568 } 569 570 int 571 dmar_enable_ir(struct dmar_unit *unit) 572 { 573 int error; 574 575 DMAR_ASSERT_LOCKED(unit); 576 unit->hw_gcmd |= DMAR_GCMD_IRE; 577 unit->hw_gcmd &= ~DMAR_GCMD_CFI; 578 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 579 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) 580 != 0)); 581 return (error); 582 } 583 584 int 585 dmar_disable_ir(struct dmar_unit *unit) 586 { 587 int error; 588 589 DMAR_ASSERT_LOCKED(unit); 590 unit->hw_gcmd &= ~DMAR_GCMD_IRE; 591 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); 592 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) 593 == 0)); 594 return (error); 595 } 596 597 #define BARRIER_F \ 598 u_int f_done, f_inproc, f_wakeup; \ 599 \ 600 f_done = 1 << (barrier_id * 3); \ 601 f_inproc = 1 << (barrier_id * 3 + 1); \ 602 f_wakeup = 1 << (barrier_id * 3 + 2) 603 604 bool 605 dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id) 606 { 607 BARRIER_F; 608 609 DMAR_LOCK(dmar); 610 if ((dmar->barrier_flags & f_done) != 0) { 611 DMAR_UNLOCK(dmar); 612 return (false); 613 } 614 615 if ((dmar->barrier_flags & f_inproc) != 0) { 616 while ((dmar->barrier_flags & f_inproc) != 0) { 617 dmar->barrier_flags |= f_wakeup; 618 msleep(&dmar->barrier_flags, &dmar->iommu.lock, 0, 619 "dmarb", 0); 620 } 621 KASSERT((dmar->barrier_flags & f_done) != 0, 622 ("dmar%d barrier %d missing done", dmar->iommu.unit, 623 barrier_id)); 624 DMAR_UNLOCK(dmar); 625 return (false); 626 } 627 628 dmar->barrier_flags |= f_inproc; 629 DMAR_UNLOCK(dmar); 630 return (true); 631 } 632 633 void 634 dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id) 635 { 636 BARRIER_F; 637 638 DMAR_ASSERT_LOCKED(dmar); 639 KASSERT((dmar->barrier_flags & (f_done | f_inproc)) == f_inproc, 640 ("dmar%d barrier %d missed entry", dmar->iommu.unit, barrier_id)); 641 dmar->barrier_flags |= f_done; 642 if ((dmar->barrier_flags & f_wakeup) != 0) 643 wakeup(&dmar->barrier_flags); 644 dmar->barrier_flags &= ~(f_inproc | f_wakeup); 645 DMAR_UNLOCK(dmar); 646 } 647 648 int dmar_batch_coalesce = 100; 649 struct timespec dmar_hw_timeout = { 650 .tv_sec = 0, 651 .tv_nsec = 1000000 652 }; 653 654 static const uint64_t d = 1000000000; 655 656 void 657 dmar_update_timeout(uint64_t newval) 658 { 659 660 /* XXXKIB not atomic */ 661 dmar_hw_timeout.tv_sec = newval / d; 662 dmar_hw_timeout.tv_nsec = newval % d; 663 } 664 665 uint64_t 666 dmar_get_timeout(void) 667 { 668 669 return ((uint64_t)dmar_hw_timeout.tv_sec * d + 670 dmar_hw_timeout.tv_nsec); 671 } 672 673 static int 674 dmar_timeout_sysctl(SYSCTL_HANDLER_ARGS) 675 { 676 uint64_t val; 677 int error; 678 679 val = dmar_get_timeout(); 680 error = sysctl_handle_long(oidp, &val, 0, req); 681 if (error != 0 || req->newptr == NULL) 682 return (error); 683 dmar_update_timeout(val); 684 return (error); 685 } 686 687 static SYSCTL_NODE(_hw_iommu, OID_AUTO, dmar, CTLFLAG_RD | CTLFLAG_MPSAFE, 688 NULL, ""); 689 SYSCTL_INT(_hw_iommu_dmar, OID_AUTO, tbl_pagecnt, CTLFLAG_RD, 690 &dmar_tbl_pagecnt, 0, 691 "Count of pages used for DMAR pagetables"); 692 SYSCTL_INT(_hw_iommu_dmar, OID_AUTO, batch_coalesce, CTLFLAG_RWTUN, 693 &dmar_batch_coalesce, 0, 694 "Number of qi batches between interrupt"); 695 SYSCTL_PROC(_hw_iommu_dmar, OID_AUTO, timeout, 696 CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0, 697 dmar_timeout_sysctl, "QU", 698 "Timeout for command wait, in nanoseconds"); 699