1 /*- 2 * Copyright (c) 2013-2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef __X86_IOMMU_INTEL_REG_H 33 #define __X86_IOMMU_INTEL_REG_H 34 35 #define DMAR_PAGE_SIZE PAGE_SIZE 36 #define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1) 37 #define DMAR_PAGE_SHIFT PAGE_SHIFT 38 #define DMAR_NPTEPG (DMAR_PAGE_SIZE / sizeof(dmar_pte_t)) 39 #define DMAR_NPTEPGSHIFT 9 40 #define DMAR_PTEMASK (DMAR_NPTEPG - 1) 41 42 typedef struct dmar_root_entry { 43 uint64_t r1; 44 uint64_t r2; 45 } dmar_root_entry_t; 46 #define DMAR_ROOT_R1_P 1 /* Present */ 47 #define DMAR_ROOT_R1_CTP_MASK 0xfffffffffffff000 /* Mask for Context-Entry 48 Table Pointer */ 49 50 #define DMAR_CTX_CNT (DMAR_PAGE_SIZE / sizeof(dmar_root_entry_t)) 51 52 typedef struct dmar_ctx_entry { 53 uint64_t ctx1; 54 uint64_t ctx2; 55 } dmar_ctx_entry_t; 56 #define DMAR_CTX1_P 1 /* Present */ 57 #define DMAR_CTX1_FPD 2 /* Fault Processing Disable */ 58 /* Translation Type: */ 59 #define DMAR_CTX1_T_UNTR 0 /* only Untranslated */ 60 #define DMAR_CTX1_T_TR 4 /* both Untranslated 61 and Translated */ 62 #define DMAR_CTX1_T_PASS 8 /* Pass-Through */ 63 #define DMAR_CTX1_ASR_MASK 0xfffffffffffff000 /* Mask for the Address 64 Space Root */ 65 #define DMAR_CTX2_AW_2LVL 0 /* 2-level page tables */ 66 #define DMAR_CTX2_AW_3LVL 1 /* 3-level page tables */ 67 #define DMAR_CTX2_AW_4LVL 2 /* 4-level page tables */ 68 #define DMAR_CTX2_AW_5LVL 3 /* 5-level page tables */ 69 #define DMAR_CTX2_AW_6LVL 4 /* 6-level page tables */ 70 #define DMAR_CTX2_DID_MASK 0xffff0 71 #define DMAR_CTX2_DID(x) ((x) << 8) /* Domain Identifier */ 72 #define DMAR_CTX2_GET_DID(ctx2) (((ctx2) & DMAR_CTX2_DID_MASK) >> 8) 73 74 typedef struct dmar_pte { 75 uint64_t pte; 76 } dmar_pte_t; 77 #define DMAR_PTE_R 1 /* Read */ 78 #define DMAR_PTE_W (1 << 1) /* Write */ 79 #define DMAR_PTE_SP (1 << 7) /* Super Page */ 80 #define DMAR_PTE_SNP (1 << 11) /* Snoop Behaviour */ 81 #define DMAR_PTE_ADDR_MASK 0xffffffffff000 /* Address Mask */ 82 #define DMAR_PTE_TM (1ULL << 62) /* Transient Mapping */ 83 84 typedef struct dmar_irte { 85 uint64_t irte1; 86 uint64_t irte2; 87 } dmar_irte_t; 88 /* Source Validation Type */ 89 #define DMAR_IRTE2_SVT_NONE (0ULL << (82 - 64)) 90 #define DMAR_IRTE2_SVT_RID (1ULL << (82 - 64)) 91 #define DMAR_IRTE2_SVT_BUS (2ULL << (82 - 64)) 92 /* Source-id Qualifier */ 93 #define DMAR_IRTE2_SQ_RID (0ULL << (80 - 64)) 94 #define DMAR_IRTE2_SQ_RID_N2 (1ULL << (80 - 64)) 95 #define DMAR_IRTE2_SQ_RID_N21 (2ULL << (80 - 64)) 96 #define DMAR_IRTE2_SQ_RID_N210 (3ULL << (80 - 64)) 97 /* Source Identifier */ 98 #define DMAR_IRTE2_SID_RID(x) ((uint64_t)(x)) 99 #define DMAR_IRTE2_SID_BUS(start, end) ((((uint64_t)(start)) << 8) | (end)) 100 /* Destination Id */ 101 #define DMAR_IRTE1_DST_xAPIC(x) (((uint64_t)(x)) << 40) 102 #define DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32) 103 /* Vector */ 104 #define DMAR_IRTE1_V(x) (((uint64_t)x) << 16) 105 #define DMAR_IRTE1_IM_POSTED (1ULL << 15) /* Posted */ 106 /* Delivery Mode */ 107 #define DMAR_IRTE1_DLM_FM (0ULL << 5) 108 #define DMAR_IRTE1_DLM_LP (1ULL << 5) 109 #define DMAR_IRTE1_DLM_SMI (2ULL << 5) 110 #define DMAR_IRTE1_DLM_NMI (4ULL << 5) 111 #define DMAR_IRTE1_DLM_INIT (5ULL << 5) 112 #define DMAR_IRTE1_DLM_ExtINT (7ULL << 5) 113 /* Trigger Mode */ 114 #define DMAR_IRTE1_TM_EDGE (0ULL << 4) 115 #define DMAR_IRTE1_TM_LEVEL (1ULL << 4) 116 /* Redirection Hint */ 117 #define DMAR_IRTE1_RH_DIRECT (0ULL << 3) 118 #define DMAR_IRTE1_RH_SELECT (1ULL << 3) 119 /* Destination Mode */ 120 #define DMAR_IRTE1_DM_PHYSICAL (0ULL << 2) 121 #define DMAR_IRTE1_DM_LOGICAL (1ULL << 2) 122 #define DMAR_IRTE1_FPD (1ULL << 1) /* Fault Processing Disable */ 123 #define DMAR_IRTE1_P (1ULL) /* Present */ 124 125 /* Version register */ 126 #define DMAR_VER_REG 0 127 #define DMAR_MAJOR_VER(x) (((x) >> 4) & 0xf) 128 #define DMAR_MINOR_VER(x) ((x) & 0xf) 129 130 /* Capabilities register */ 131 #define DMAR_CAP_REG 0x8 132 #define DMAR_CAP_PI (1ULL << 59) /* Posted Interrupts */ 133 #define DMAR_CAP_FL1GP (1ULL << 56) /* First Level 1GByte Page */ 134 #define DMAR_CAP_DRD (1ULL << 55) /* DMA Read Draining */ 135 #define DMAR_CAP_DWD (1ULL << 54) /* DMA Write Draining */ 136 #define DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f)) 137 /* Maximum Address Mask */ 138 #define DMAR_CAP_NFR(x) ((u_int)(((x) >> 40) & 0xff) + 1) 139 /* Num of Fault-recording regs */ 140 #define DMAR_CAP_PSI (1ULL << 39) /* Page Selective Invalidation */ 141 #define DMAR_CAP_SPS(x) ((u_int)(((x) >> 34) & 0xf)) /* Super-Page Support */ 142 #define DMAR_CAP_SPS_2M 0x1 143 #define DMAR_CAP_SPS_1G 0x2 144 #define DMAR_CAP_SPS_512G 0x4 145 #define DMAR_CAP_SPS_1T 0x8 146 #define DMAR_CAP_FRO(x) ((u_int)(((x) >> 24) & 0x1ff)) 147 /* Fault-recording reg offset */ 148 #define DMAR_CAP_ISOCH (1 << 23) /* Isochrony */ 149 #define DMAR_CAP_ZLR (1 << 22) /* Zero-length reads */ 150 #define DMAR_CAP_MGAW(x) ((u_int)(((x) >> 16) & 0x3f)) 151 /* Max Guest Address Width */ 152 #define DMAR_CAP_SAGAW(x) ((u_int)(((x) >> 8) & 0x1f)) 153 /* Adjusted Guest Address Width */ 154 #define DMAR_CAP_SAGAW_2LVL 0x01 155 #define DMAR_CAP_SAGAW_3LVL 0x02 156 #define DMAR_CAP_SAGAW_4LVL 0x04 157 #define DMAR_CAP_SAGAW_5LVL 0x08 158 #define DMAR_CAP_SAGAW_6LVL 0x10 159 #define DMAR_CAP_CM (1 << 7) /* Caching mode */ 160 #define DMAR_CAP_PHMR (1 << 6) /* Protected High-mem Region */ 161 #define DMAR_CAP_PLMR (1 << 5) /* Protected Low-mem Region */ 162 #define DMAR_CAP_RWBF (1 << 4) /* Required Write-Buffer Flushing */ 163 #define DMAR_CAP_AFL (1 << 3) /* Advanced Fault Logging */ 164 #define DMAR_CAP_ND(x) ((u_int)((x) & 0x3)) /* Number of domains */ 165 166 /* Extended Capabilities register */ 167 #define DMAR_ECAP_REG 0x10 168 #define DMAR_ECAP_PSS(x) (((x) >> 35) & 0xf) /* PASID Size Supported */ 169 #define DMAR_ECAP_EAFS (1ULL << 34) /* Extended Accessed Flag */ 170 #define DMAR_ECAP_NWFS (1ULL << 33) /* No Write Flag */ 171 #define DMAR_ECAP_SRS (1ULL << 31) /* Supervisor Request */ 172 #define DMAR_ECAP_ERS (1ULL << 30) /* Execute Request */ 173 #define DMAR_ECAP_PRS (1ULL << 29) /* Page Request */ 174 #define DMAR_ECAP_PASID (1ULL << 28) /* Process Address Space Id */ 175 #define DMAR_ECAP_DIS (1ULL << 27) /* Deferred Invalidate */ 176 #define DMAR_ECAP_NEST (1ULL << 26) /* Nested Translation */ 177 #define DMAR_ECAP_MTS (1ULL << 25) /* Memory Type */ 178 #define DMAR_ECAP_ECS (1ULL << 24) /* Extended Context */ 179 #define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf)) 180 /* Maximum Handle Mask Value */ 181 #define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff)) 182 /* IOTLB Register Offset */ 183 #define DMAR_ECAP_SC (1 << 7) /* Snoop Control */ 184 #define DMAR_ECAP_PT (1 << 6) /* Pass Through */ 185 #define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode (x2APIC) */ 186 #define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */ 187 #define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */ 188 #define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */ 189 #define DMAR_ECAP_C (1 << 0) /* Coherency */ 190 191 /* Global Command register */ 192 #define DMAR_GCMD_REG 0x18 193 #define DMAR_GCMD_TE (1U << 31) /* Translation Enable */ 194 #define DMAR_GCMD_SRTP (1 << 30) /* Set Root Table Pointer */ 195 #define DMAR_GCMD_SFL (1 << 29) /* Set Fault Log */ 196 #define DMAR_GCMD_EAFL (1 << 28) /* Enable Advanced Fault Logging */ 197 #define DMAR_GCMD_WBF (1 << 27) /* Write Buffer Flush */ 198 #define DMAR_GCMD_QIE (1 << 26) /* Queued Invalidation Enable */ 199 #define DMAR_GCMD_IRE (1 << 25) /* Interrupt Remapping Enable */ 200 #define DMAR_GCMD_SIRTP (1 << 24) /* Set Interrupt Remap Table Pointer */ 201 #define DMAR_GCMD_CFI (1 << 23) /* Compatibility Format Interrupt */ 202 203 /* Global Status register */ 204 #define DMAR_GSTS_REG 0x1c 205 #define DMAR_GSTS_TES (1U << 31) /* Translation Enable Status */ 206 #define DMAR_GSTS_RTPS (1 << 30) /* Root Table Pointer Status */ 207 #define DMAR_GSTS_FLS (1 << 29) /* Fault Log Status */ 208 #define DMAR_GSTS_AFLS (1 << 28) /* Advanced Fault Logging Status */ 209 #define DMAR_GSTS_WBFS (1 << 27) /* Write Buffer Flush Status */ 210 #define DMAR_GSTS_QIES (1 << 26) /* Queued Invalidation Enable Status */ 211 #define DMAR_GSTS_IRES (1 << 25) /* Interrupt Remapping Enable Status */ 212 #define DMAR_GSTS_IRTPS (1 << 24) /* Interrupt Remapping Table 213 Pointer Status */ 214 #define DMAR_GSTS_CFIS (1 << 23) /* Compatibility Format 215 Interrupt Status */ 216 217 /* Root-Entry Table Address register */ 218 #define DMAR_RTADDR_REG 0x20 219 #define DMAR_RTADDR_RTT (1 << 11) /* Root Table Type */ 220 #define DMAR_RTADDR_RTA_MASK 0xfffffffffffff000 221 222 /* Context Command register */ 223 #define DMAR_CCMD_REG 0x28 224 #define DMAR_CCMD_ICC (1ULL << 63) /* Invalidate Context-Cache */ 225 #define DMAR_CCMD_ICC32 (1U << 31) 226 #define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation 227 Request Granularity */ 228 #define DMAR_CCMD_CIRG_GLOB (0x1ULL << 61) /* Global */ 229 #define DMAR_CCMD_CIRG_DOM (0x2ULL << 61) /* Domain */ 230 #define DMAR_CCMD_CIRG_DEV (0x3ULL << 61) /* Device */ 231 #define DMAR_CCMD_CAIG(x) (((x) >> 59) & 0x3) /* Context Actual 232 Invalidation Granularity */ 233 #define DMAR_CCMD_CAIG_GLOB 0x1 /* Global */ 234 #define DMAR_CCMD_CAIG_DOM 0x2 /* Domain */ 235 #define DMAR_CCMD_CAIG_DEV 0x3 /* Device */ 236 #define DMAR_CCMD_FM (0x3UUL << 32) /* Function Mask */ 237 #define DMAR_CCMD_SID(x) (((x) & 0xffff) << 16) /* Source-ID */ 238 #define DMAR_CCMD_DID(x) ((x) & 0xffff) /* Domain-ID */ 239 240 /* Invalidate Address register */ 241 #define DMAR_IVA_REG_OFF 0 242 #define DMAR_IVA_IH (1 << 6) /* Invalidation Hint */ 243 #define DMAR_IVA_AM(x) ((x) & 0x1f) /* Address Mask */ 244 #define DMAR_IVA_ADDR(x) ((x) & ~0xfffULL) /* Address */ 245 246 /* IOTLB Invalidate register */ 247 #define DMAR_IOTLB_REG_OFF 0x8 248 #define DMAR_IOTLB_IVT (1ULL << 63) /* Invalidate IOTLB */ 249 #define DMAR_IOTLB_IVT32 (1U << 31) 250 #define DMAR_IOTLB_IIRG_MASK (0x3ULL << 60) /* Invalidation Request 251 Granularity */ 252 #define DMAR_IOTLB_IIRG_GLB (0x1ULL << 60) /* Global */ 253 #define DMAR_IOTLB_IIRG_DOM (0x2ULL << 60) /* Domain-selective */ 254 #define DMAR_IOTLB_IIRG_PAGE (0x3ULL << 60) /* Page-selective */ 255 #define DMAR_IOTLB_IAIG_MASK (0x3ULL << 57) /* Actual Invalidation 256 Granularity */ 257 #define DMAR_IOTLB_IAIG_INVLD 0 /* Hw detected error */ 258 #define DMAR_IOTLB_IAIG_GLB (0x1ULL << 57) /* Global */ 259 #define DMAR_IOTLB_IAIG_DOM (0x2ULL << 57) /* Domain-selective */ 260 #define DMAR_IOTLB_IAIG_PAGE (0x3ULL << 57) /* Page-selective */ 261 #define DMAR_IOTLB_DR (0x1ULL << 49) /* Drain Reads */ 262 #define DMAR_IOTLB_DW (0x1ULL << 48) /* Drain Writes */ 263 #define DMAR_IOTLB_DID(x) (((uint64_t)(x) & 0xffff) << 32) /* Domain Id */ 264 265 /* Fault Status register */ 266 #define DMAR_FSTS_REG 0x34 267 #define DMAR_FSTS_FRI(x) (((x) >> 8) & 0xff) /* Fault Record Index */ 268 #define DMAR_FSTS_ITE (1 << 6) /* Invalidation Time-out */ 269 #define DMAR_FSTS_ICE (1 << 5) /* Invalidation Completion */ 270 #define DMAR_FSTS_IQE (1 << 4) /* Invalidation Queue */ 271 #define DMAR_FSTS_APF (1 << 3) /* Advanced Pending Fault */ 272 #define DMAR_FSTS_AFO (1 << 2) /* Advanced Fault Overflow */ 273 #define DMAR_FSTS_PPF (1 << 1) /* Primary Pending Fault */ 274 #define DMAR_FSTS_PFO 1 /* Fault Overflow */ 275 276 /* Fault Event Control register */ 277 #define DMAR_FECTL_REG 0x38 278 #define DMAR_FECTL_IM (1U << 31) /* Interrupt Mask */ 279 #define DMAR_FECTL_IP (1 << 30) /* Interrupt Pending */ 280 281 /* Fault Event Data register */ 282 #define DMAR_FEDATA_REG 0x3c 283 284 /* Fault Event Address register */ 285 #define DMAR_FEADDR_REG 0x40 286 287 /* Fault Event Upper Address register */ 288 #define DMAR_FEUADDR_REG 0x44 289 290 /* Advanced Fault Log register */ 291 #define DMAR_AFLOG_REG 0x58 292 293 /* Fault Recording Register, also usable for Advanced Fault Log records */ 294 #define DMAR_FRCD2_F (1ULL << 63) /* Fault */ 295 #define DMAR_FRCD2_F32 (1U << 31) 296 #define DMAR_FRCD2_T(x) ((int)((x >> 62) & 1)) /* Type */ 297 #define DMAR_FRCD2_T_W 0 /* Write request */ 298 #define DMAR_FRCD2_T_R 1 /* Read or AtomicOp */ 299 #define DMAR_FRCD2_AT(x) ((int)((x >> 60) & 0x3)) /* Address Type */ 300 #define DMAR_FRCD2_FR(x) ((int)((x >> 32) & 0xff)) /* Fault Reason */ 301 #define DMAR_FRCD2_SID(x) ((int)(x & 0xffff)) /* Source Identifier */ 302 #define DMAR_FRCS1_FI_MASK 0xffffffffff000 /* Fault Info, Address Mask */ 303 304 /* Protected Memory Enable register */ 305 #define DMAR_PMEN_REG 0x64 306 #define DMAR_PMEN_EPM (1U << 31) /* Enable Protected Memory */ 307 #define DMAR_PMEN_PRS 1 /* Protected Region Status */ 308 309 /* Protected Low-Memory Base register */ 310 #define DMAR_PLMBASE_REG 0x68 311 312 /* Protected Low-Memory Limit register */ 313 #define DMAR_PLMLIMIT_REG 0x6c 314 315 /* Protected High-Memory Base register */ 316 #define DMAR_PHMBASE_REG 0x70 317 318 /* Protected High-Memory Limit register */ 319 #define DMAR_PHMLIMIT_REG 0x78 320 321 /* Queued Invalidation Descriptors */ 322 #define DMAR_IQ_DESCR_SZ_SHIFT 4 /* Shift for descriptor count 323 to ring offset */ 324 #define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT) 325 /* Descriptor size */ 326 327 /* Context-cache Invalidate Descriptor */ 328 #define DMAR_IQ_DESCR_CTX_INV 0x1 329 #define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */ 330 #define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */ 331 #define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */ 332 #define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ 333 #define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */ 334 #define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */ 335 336 /* IOTLB Invalidate Descriptor */ 337 #define DMAR_IQ_DESCR_IOTLB_INV 0x2 338 #define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */ 339 #define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */ 340 #define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */ 341 #define DMAR_IQ_DESCR_IOTLB_DW (1 << 6) /* Drain Writes */ 342 #define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */ 343 #define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ 344 345 /* Device-TLB Invalidate Descriptor */ 346 #define DMAR_IQ_DESCR_DTLB_INV 0x3 347 348 /* Invalidate Interrupt Entry Cache */ 349 #define DMAR_IQ_DESCR_IEC_INV 0x4 350 #define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */ 351 #define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */ 352 #define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */ 353 354 /* Invalidation Wait Descriptor */ 355 #define DMAR_IQ_DESCR_WAIT_ID 0x5 356 #define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */ 357 #define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */ 358 #define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */ 359 #define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */ 360 361 /* Extended IOTLB Invalidate Descriptor */ 362 #define DMAR_IQ_DESCR_EIOTLB_INV 0x6 363 364 /* PASID-Cache Invalidate Descriptor */ 365 #define DMAR_IQ_DESCR_PASIDC_INV 0x7 366 367 /* Extended Device-TLB Invalidate Descriptor */ 368 #define DMAR_IQ_DESCR_EDTLB_INV 0x8 369 370 /* Invalidation Queue Head register */ 371 #define DMAR_IQH_REG 0x80 372 #define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */ 373 374 /* Invalidation Queue Tail register */ 375 #define DMAR_IQT_REG 0x88 376 #define DMAR_IQT_MASK 0x7fff0 377 378 /* Invalidation Queue Address register */ 379 #define DMAR_IQA_REG 0x90 380 #define DMAR_IQA_IQA_MASK 0xfffffffffffff000 /* Invalidation Queue 381 Base Address mask */ 382 #define DMAR_IQA_QS_MASK 0x7 /* Queue Size in pages */ 383 #define DMAR_IQA_QS_MAX 0x7 /* Max Queue size */ 384 #define DMAR_IQA_QS_DEF 3 385 386 /* Invalidation Completion Status register */ 387 #define DMAR_ICS_REG 0x9c 388 #define DMAR_ICS_IWC 1 /* Invalidation Wait 389 Descriptor Complete */ 390 391 /* Invalidation Event Control register */ 392 #define DMAR_IECTL_REG 0xa0 393 #define DMAR_IECTL_IM (1U << 31) /* Interrupt Mask */ 394 #define DMAR_IECTL_IP (1 << 30) /* Interrupt Pending */ 395 396 /* Invalidation Event Data register */ 397 #define DMAR_IEDATA_REG 0xa4 398 399 /* Invalidation Event Address register */ 400 #define DMAR_IEADDR_REG 0xa8 401 402 /* Invalidation Event Upper Address register */ 403 #define DMAR_IEUADDR_REG 0xac 404 405 /* Interrupt Remapping Table Address register */ 406 #define DMAR_IRTA_REG 0xb8 407 #define DMAR_IRTA_EIME (1 << 11) /* Extended Interrupt Mode 408 Enable */ 409 #define DMAR_IRTA_S_MASK 0xf /* Size Mask */ 410 411 #endif 412