xref: /freebsd/sys/x86/iommu/intel_quirks.c (revision dd41de95a84d979615a2ef11df6850622bf6184e)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2013, 2015 The FreeBSD Foundation
5  * All rights reserved.
6  *
7  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
8  * under sponsorship from the FreeBSD Foundation.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34 
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/kernel.h>
38 #include <sys/lock.h>
39 #include <sys/malloc.h>
40 #include <sys/memdesc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/rman.h>
44 #include <sys/rwlock.h>
45 #include <sys/smp.h>
46 #include <sys/taskqueue.h>
47 #include <sys/tree.h>
48 #include <sys/vmem.h>
49 #include <vm/vm.h>
50 #include <vm/vm_extern.h>
51 #include <vm/vm_kern.h>
52 #include <vm/vm_object.h>
53 #include <vm/vm_page.h>
54 #include <vm/vm_pager.h>
55 #include <vm/vm_map.h>
56 #include <contrib/dev/acpica/include/acpi.h>
57 #include <contrib/dev/acpica/include/accommon.h>
58 #include <dev/acpica/acpivar.h>
59 #include <dev/pci/pcireg.h>
60 #include <dev/pci/pcivar.h>
61 #include <machine/bus.h>
62 #include <x86/include/busdma_impl.h>
63 #include <dev/iommu/busdma_iommu.h>
64 #include <x86/iommu/intel_reg.h>
65 #include <x86/iommu/intel_dmar.h>
66 
67 typedef void (*dmar_quirk_cpu_fun)(struct dmar_unit *);
68 
69 struct intel_dmar_quirk_cpu {
70 	u_int ext_family;
71 	u_int ext_model;
72 	u_int family_code;
73 	u_int model;
74 	u_int stepping;
75 	dmar_quirk_cpu_fun quirk;
76 	const char *descr;
77 };
78 
79 typedef void (*dmar_quirk_nb_fun)(struct dmar_unit *, device_t nb);
80 
81 struct intel_dmar_quirk_nb {
82 	u_int dev_id;
83 	u_int rev_no;
84 	dmar_quirk_nb_fun quirk;
85 	const char *descr;
86 };
87 
88 #define	QUIRK_NB_ALL_REV	0xffffffff
89 
90 static void
91 dmar_match_quirks(struct dmar_unit *dmar,
92     const struct intel_dmar_quirk_nb *nb_quirks, int nb_quirks_len,
93     const struct intel_dmar_quirk_cpu *cpu_quirks, int cpu_quirks_len)
94 {
95 	device_t nb;
96 	const struct intel_dmar_quirk_nb *nb_quirk;
97 	const struct intel_dmar_quirk_cpu *cpu_quirk;
98 	u_int p[4];
99 	u_int dev_id, rev_no;
100 	u_int ext_family, ext_model, family_code, model, stepping;
101 	int i;
102 
103 	if (nb_quirks != NULL) {
104 		nb = pci_find_bsf(0, 0, 0);
105 		if (nb != NULL) {
106 			dev_id = pci_get_device(nb);
107 			rev_no = pci_get_revid(nb);
108 			for (i = 0; i < nb_quirks_len; i++) {
109 				nb_quirk = &nb_quirks[i];
110 				if (nb_quirk->dev_id == dev_id &&
111 				    (nb_quirk->rev_no == rev_no ||
112 				    nb_quirk->rev_no == QUIRK_NB_ALL_REV)) {
113 					if (bootverbose) {
114 						device_printf(dmar->dev,
115 						    "NB IOMMU quirk %s\n",
116 						    nb_quirk->descr);
117 					}
118 					nb_quirk->quirk(dmar, nb);
119 				}
120 			}
121 		} else {
122 			device_printf(dmar->dev, "cannot find northbridge\n");
123 		}
124 	}
125 	if (cpu_quirks != NULL) {
126 		do_cpuid(1, p);
127 		ext_family = (p[0] & CPUID_EXT_FAMILY) >> 20;
128 		ext_model = (p[0] & CPUID_EXT_MODEL) >> 16;
129 		family_code = (p[0] & CPUID_FAMILY) >> 8;
130 		model = (p[0] & CPUID_MODEL) >> 4;
131 		stepping = p[0] & CPUID_STEPPING;
132 		for (i = 0; i < cpu_quirks_len; i++) {
133 			cpu_quirk = &cpu_quirks[i];
134 			if (cpu_quirk->ext_family == ext_family &&
135 			    cpu_quirk->ext_model == ext_model &&
136 			    cpu_quirk->family_code == family_code &&
137 			    cpu_quirk->model == model &&
138 			    (cpu_quirk->stepping == -1 ||
139 			    cpu_quirk->stepping == stepping)) {
140 				if (bootverbose) {
141 					device_printf(dmar->dev,
142 					    "CPU IOMMU quirk %s\n",
143 					    cpu_quirk->descr);
144 				}
145 				cpu_quirk->quirk(dmar);
146 			}
147 		}
148 	}
149 }
150 
151 static void
152 nb_5400_no_low_high_prot_mem(struct dmar_unit *unit, device_t nb __unused)
153 {
154 
155 	unit->hw_cap &= ~(DMAR_CAP_PHMR | DMAR_CAP_PLMR);
156 }
157 
158 static void
159 nb_no_ir(struct dmar_unit *unit, device_t nb __unused)
160 {
161 
162 	unit->hw_ecap &= ~(DMAR_ECAP_IR | DMAR_ECAP_EIM);
163 }
164 
165 static void
166 nb_5500_no_ir_rev13(struct dmar_unit *unit, device_t nb)
167 {
168 	u_int rev_no;
169 
170 	rev_no = pci_get_revid(nb);
171 	if (rev_no <= 0x13)
172 		nb_no_ir(unit, nb);
173 }
174 
175 static const struct intel_dmar_quirk_nb pre_use_nb[] = {
176 	{
177 	    .dev_id = 0x4001, .rev_no = 0x20,
178 	    .quirk = nb_5400_no_low_high_prot_mem,
179 	    .descr = "5400 E23" /* no low/high protected memory */
180 	},
181 	{
182 	    .dev_id = 0x4003, .rev_no = 0x20,
183 	    .quirk = nb_5400_no_low_high_prot_mem,
184 	    .descr = "5400 E23" /* no low/high protected memory */
185 	},
186 	{
187 	    .dev_id = 0x3403, .rev_no = QUIRK_NB_ALL_REV,
188 	    .quirk = nb_5500_no_ir_rev13,
189 	    .descr = "5500 E47, E53" /* interrupt remapping does not work */
190 	},
191 	{
192 	    .dev_id = 0x3405, .rev_no = QUIRK_NB_ALL_REV,
193 	    .quirk = nb_5500_no_ir_rev13,
194 	    .descr = "5500 E47, E53" /* interrupt remapping does not work */
195 	},
196 	{
197 	    .dev_id = 0x3405, .rev_no = 0x22,
198 	    .quirk = nb_no_ir,
199 	    .descr = "5500 E47, E53" /* interrupt remapping does not work */
200 	},
201 	{
202 	    .dev_id = 0x3406, .rev_no = QUIRK_NB_ALL_REV,
203 	    .quirk = nb_5500_no_ir_rev13,
204 	    .descr = "5500 E47, E53" /* interrupt remapping does not work */
205 	},
206 };
207 
208 static void
209 cpu_e5_am9(struct dmar_unit *unit)
210 {
211 
212 	unit->hw_cap &= ~(0x3fULL << 48);
213 	unit->hw_cap |= (9ULL << 48);
214 }
215 
216 static const struct intel_dmar_quirk_cpu post_ident_cpu[] = {
217 	{
218 	    .ext_family = 0, .ext_model = 2, .family_code = 6, .model = 13,
219 	    .stepping = 6, .quirk = cpu_e5_am9,
220 	    .descr = "E5 BT176" /* AM should be at most 9 */
221 	},
222 };
223 
224 void
225 dmar_quirks_pre_use(struct iommu_unit *unit)
226 {
227 	struct dmar_unit *dmar;
228 
229 	dmar = IOMMU2DMAR(unit);
230 
231 	if (!dmar_barrier_enter(dmar, DMAR_BARRIER_USEQ))
232 		return;
233 	DMAR_LOCK(dmar);
234 	dmar_match_quirks(dmar, pre_use_nb, nitems(pre_use_nb),
235 	    NULL, 0);
236 	dmar_barrier_exit(dmar, DMAR_BARRIER_USEQ);
237 }
238 
239 void
240 dmar_quirks_post_ident(struct dmar_unit *dmar)
241 {
242 
243 	dmar_match_quirks(dmar, NULL, 0, post_ident_cpu,
244 	    nitems(post_ident_cpu));
245 }
246