xref: /freebsd/sys/x86/iommu/intel_quirks.c (revision 9bc300465e48e19d794d88d0c158a2adb92c7197)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2013, 2015 The FreeBSD Foundation
5  *
6  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
7  * under sponsorship from the FreeBSD Foundation.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  */
30 
31 #include <sys/param.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/malloc.h>
36 #include <sys/memdesc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/rman.h>
40 #include <sys/rwlock.h>
41 #include <sys/smp.h>
42 #include <sys/taskqueue.h>
43 #include <sys/tree.h>
44 #include <sys/vmem.h>
45 #include <vm/vm.h>
46 #include <vm/vm_extern.h>
47 #include <vm/vm_kern.h>
48 #include <vm/vm_object.h>
49 #include <vm/vm_page.h>
50 #include <vm/vm_pager.h>
51 #include <vm/vm_map.h>
52 #include <contrib/dev/acpica/include/acpi.h>
53 #include <contrib/dev/acpica/include/accommon.h>
54 #include <dev/acpica/acpivar.h>
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcivar.h>
57 #include <machine/bus.h>
58 #include <x86/include/busdma_impl.h>
59 #include <dev/iommu/busdma_iommu.h>
60 #include <x86/iommu/intel_reg.h>
61 #include <x86/iommu/x86_iommu.h>
62 #include <x86/iommu/intel_dmar.h>
63 
64 typedef void (*dmar_quirk_cpu_fun)(struct dmar_unit *);
65 
66 struct intel_dmar_quirk_cpu {
67 	u_int ext_family;
68 	u_int ext_model;
69 	u_int family_code;
70 	u_int model;
71 	u_int stepping;
72 	dmar_quirk_cpu_fun quirk;
73 	const char *descr;
74 };
75 
76 typedef void (*dmar_quirk_nb_fun)(struct dmar_unit *, device_t nb);
77 
78 struct intel_dmar_quirk_nb {
79 	u_int dev_id;
80 	u_int rev_no;
81 	dmar_quirk_nb_fun quirk;
82 	const char *descr;
83 };
84 
85 #define	QUIRK_NB_ALL_REV	0xffffffff
86 
87 static void
88 dmar_match_quirks(struct dmar_unit *dmar,
89     const struct intel_dmar_quirk_nb *nb_quirks, int nb_quirks_len,
90     const struct intel_dmar_quirk_cpu *cpu_quirks, int cpu_quirks_len)
91 {
92 	device_t nb;
93 	const struct intel_dmar_quirk_nb *nb_quirk;
94 	const struct intel_dmar_quirk_cpu *cpu_quirk;
95 	u_int p[4];
96 	u_int dev_id, rev_no;
97 	u_int ext_family, ext_model, family_code, model, stepping;
98 	int i;
99 
100 	if (nb_quirks != NULL) {
101 		nb = pci_find_bsf(0, 0, 0);
102 		if (nb != NULL) {
103 			dev_id = pci_get_device(nb);
104 			rev_no = pci_get_revid(nb);
105 			for (i = 0; i < nb_quirks_len; i++) {
106 				nb_quirk = &nb_quirks[i];
107 				if (nb_quirk->dev_id == dev_id &&
108 				    (nb_quirk->rev_no == rev_no ||
109 				    nb_quirk->rev_no == QUIRK_NB_ALL_REV)) {
110 					if (bootverbose) {
111 						device_printf(dmar->iommu.dev,
112 						    "NB IOMMU quirk %s\n",
113 						    nb_quirk->descr);
114 					}
115 					nb_quirk->quirk(dmar, nb);
116 				}
117 			}
118 		} else {
119 			device_printf(dmar->iommu.dev,
120 			    "cannot find northbridge\n");
121 		}
122 	}
123 	if (cpu_quirks != NULL) {
124 		do_cpuid(1, p);
125 		ext_family = (p[0] & CPUID_EXT_FAMILY) >> 20;
126 		ext_model = (p[0] & CPUID_EXT_MODEL) >> 16;
127 		family_code = (p[0] & CPUID_FAMILY) >> 8;
128 		model = (p[0] & CPUID_MODEL) >> 4;
129 		stepping = p[0] & CPUID_STEPPING;
130 		for (i = 0; i < cpu_quirks_len; i++) {
131 			cpu_quirk = &cpu_quirks[i];
132 			if (cpu_quirk->ext_family == ext_family &&
133 			    cpu_quirk->ext_model == ext_model &&
134 			    cpu_quirk->family_code == family_code &&
135 			    cpu_quirk->model == model &&
136 			    (cpu_quirk->stepping == -1 ||
137 			    cpu_quirk->stepping == stepping)) {
138 				if (bootverbose) {
139 					device_printf(dmar->iommu.dev,
140 					    "CPU IOMMU quirk %s\n",
141 					    cpu_quirk->descr);
142 				}
143 				cpu_quirk->quirk(dmar);
144 			}
145 		}
146 	}
147 }
148 
149 static void
150 nb_5400_no_low_high_prot_mem(struct dmar_unit *unit, device_t nb __unused)
151 {
152 
153 	unit->hw_cap &= ~(DMAR_CAP_PHMR | DMAR_CAP_PLMR);
154 }
155 
156 static void
157 nb_no_ir(struct dmar_unit *unit, device_t nb __unused)
158 {
159 
160 	unit->hw_ecap &= ~(DMAR_ECAP_IR | DMAR_ECAP_EIM);
161 }
162 
163 static void
164 nb_5500_no_ir_rev13(struct dmar_unit *unit, device_t nb)
165 {
166 	u_int rev_no;
167 
168 	rev_no = pci_get_revid(nb);
169 	if (rev_no <= 0x13)
170 		nb_no_ir(unit, nb);
171 }
172 
173 static const struct intel_dmar_quirk_nb pre_use_nb[] = {
174 	{
175 	    .dev_id = 0x4001, .rev_no = 0x20,
176 	    .quirk = nb_5400_no_low_high_prot_mem,
177 	    .descr = "5400 E23" /* no low/high protected memory */
178 	},
179 	{
180 	    .dev_id = 0x4003, .rev_no = 0x20,
181 	    .quirk = nb_5400_no_low_high_prot_mem,
182 	    .descr = "5400 E23" /* no low/high protected memory */
183 	},
184 	{
185 	    .dev_id = 0x3403, .rev_no = QUIRK_NB_ALL_REV,
186 	    .quirk = nb_5500_no_ir_rev13,
187 	    .descr = "5500 E47, E53" /* interrupt remapping does not work */
188 	},
189 	{
190 	    .dev_id = 0x3405, .rev_no = QUIRK_NB_ALL_REV,
191 	    .quirk = nb_5500_no_ir_rev13,
192 	    .descr = "5500 E47, E53" /* interrupt remapping does not work */
193 	},
194 	{
195 	    .dev_id = 0x3405, .rev_no = 0x22,
196 	    .quirk = nb_no_ir,
197 	    .descr = "5500 E47, E53" /* interrupt remapping does not work */
198 	},
199 	{
200 	    .dev_id = 0x3406, .rev_no = QUIRK_NB_ALL_REV,
201 	    .quirk = nb_5500_no_ir_rev13,
202 	    .descr = "5500 E47, E53" /* interrupt remapping does not work */
203 	},
204 };
205 
206 static void
207 cpu_e5_am9(struct dmar_unit *unit)
208 {
209 
210 	unit->hw_cap &= ~(0x3fULL << 48);
211 	unit->hw_cap |= (9ULL << 48);
212 }
213 
214 static const struct intel_dmar_quirk_cpu post_ident_cpu[] = {
215 	{
216 	    .ext_family = 0, .ext_model = 2, .family_code = 6, .model = 13,
217 	    .stepping = 6, .quirk = cpu_e5_am9,
218 	    .descr = "E5 BT176" /* AM should be at most 9 */
219 	},
220 };
221 
222 void
223 dmar_quirks_pre_use(struct iommu_unit *unit)
224 {
225 	struct dmar_unit *dmar;
226 
227 	dmar = IOMMU2DMAR(unit);
228 
229 	if (!dmar_barrier_enter(dmar, DMAR_BARRIER_USEQ))
230 		return;
231 	DMAR_LOCK(dmar);
232 	dmar_match_quirks(dmar, pre_use_nb, nitems(pre_use_nb),
233 	    NULL, 0);
234 	dmar_barrier_exit(dmar, DMAR_BARRIER_USEQ);
235 }
236 
237 void
238 dmar_quirks_post_ident(struct dmar_unit *dmar)
239 {
240 
241 	dmar_match_quirks(dmar, NULL, 0, post_ident_cpu,
242 	    nitems(post_ident_cpu));
243 }
244