xref: /freebsd/sys/x86/iommu/intel_idpgtbl.c (revision 119b75925c562202145d7bac7b676b98029c6cb9)
1 /*-
2  * Copyright (c) 2013 The FreeBSD Foundation
3  * All rights reserved.
4  *
5  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6  * under sponsorship from the FreeBSD Foundation.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
36 #include <sys/bus.h>
37 #include <sys/interrupt.h>
38 #include <sys/kernel.h>
39 #include <sys/ktr.h>
40 #include <sys/lock.h>
41 #include <sys/memdesc.h>
42 #include <sys/mutex.h>
43 #include <sys/proc.h>
44 #include <sys/rwlock.h>
45 #include <sys/rman.h>
46 #include <sys/sf_buf.h>
47 #include <sys/sysctl.h>
48 #include <sys/taskqueue.h>
49 #include <sys/tree.h>
50 #include <sys/uio.h>
51 #include <sys/vmem.h>
52 #include <vm/vm.h>
53 #include <vm/vm_extern.h>
54 #include <vm/vm_kern.h>
55 #include <vm/vm_object.h>
56 #include <vm/vm_page.h>
57 #include <vm/vm_pager.h>
58 #include <vm/vm_map.h>
59 #include <machine/atomic.h>
60 #include <machine/bus.h>
61 #include <machine/cpu.h>
62 #include <machine/md_var.h>
63 #include <machine/specialreg.h>
64 #include <x86/include/busdma_impl.h>
65 #include <x86/iommu/intel_reg.h>
66 #include <x86/iommu/busdma_dmar.h>
67 #include <x86/iommu/intel_dmar.h>
68 
69 static int domain_unmap_buf_locked(struct dmar_domain *domain,
70     dmar_gaddr_t base, dmar_gaddr_t size, int flags);
71 
72 /*
73  * The cache of the identity mapping page tables for the DMARs.  Using
74  * the cache saves significant amount of memory for page tables by
75  * reusing the page tables, since usually DMARs are identical and have
76  * the same capabilities.  Still, cache records the information needed
77  * to match DMAR capabilities and page table format, to correctly
78  * handle different DMARs.
79  */
80 
81 struct idpgtbl {
82 	dmar_gaddr_t maxaddr;	/* Page table covers the guest address
83 				   range [0..maxaddr) */
84 	int pglvl;		/* Total page table levels ignoring
85 				   superpages */
86 	int leaf;		/* The last materialized page table
87 				   level, it is non-zero if superpages
88 				   are supported */
89 	vm_object_t pgtbl_obj;	/* The page table pages */
90 	LIST_ENTRY(idpgtbl) link;
91 };
92 
93 static struct sx idpgtbl_lock;
94 SX_SYSINIT(idpgtbl, &idpgtbl_lock, "idpgtbl");
95 static LIST_HEAD(, idpgtbl) idpgtbls = LIST_HEAD_INITIALIZER(idpgtbls);
96 static MALLOC_DEFINE(M_DMAR_IDPGTBL, "dmar_idpgtbl",
97     "Intel DMAR Identity mappings cache elements");
98 
99 /*
100  * Build the next level of the page tables for the identity mapping.
101  * - lvl is the level to build;
102  * - idx is the index of the page table page in the pgtbl_obj, which is
103  *   being allocated filled now;
104  * - addr is the starting address in the bus address space which is
105  *   mapped by the page table page.
106  */
107 static void
108 domain_idmap_nextlvl(struct idpgtbl *tbl, int lvl, vm_pindex_t idx,
109     dmar_gaddr_t addr)
110 {
111 	vm_page_t m1;
112 	dmar_pte_t *pte;
113 	struct sf_buf *sf;
114 	dmar_gaddr_t f, pg_sz;
115 	vm_pindex_t base;
116 	int i;
117 
118 	VM_OBJECT_ASSERT_LOCKED(tbl->pgtbl_obj);
119 	if (addr >= tbl->maxaddr)
120 		return;
121 	(void)dmar_pgalloc(tbl->pgtbl_obj, idx, DMAR_PGF_OBJL | DMAR_PGF_WAITOK |
122 	    DMAR_PGF_ZERO);
123 	base = idx * DMAR_NPTEPG + 1; /* Index of the first child page of idx */
124 	pg_sz = pglvl_page_size(tbl->pglvl, lvl);
125 	if (lvl != tbl->leaf) {
126 		for (i = 0, f = addr; i < DMAR_NPTEPG; i++, f += pg_sz)
127 			domain_idmap_nextlvl(tbl, lvl + 1, base + i, f);
128 	}
129 	VM_OBJECT_WUNLOCK(tbl->pgtbl_obj);
130 	pte = dmar_map_pgtbl(tbl->pgtbl_obj, idx, DMAR_PGF_WAITOK, &sf);
131 	if (lvl == tbl->leaf) {
132 		for (i = 0, f = addr; i < DMAR_NPTEPG; i++, f += pg_sz) {
133 			if (f >= tbl->maxaddr)
134 				break;
135 			pte[i].pte = (DMAR_PTE_ADDR_MASK & f) |
136 			    DMAR_PTE_R | DMAR_PTE_W;
137 		}
138 	} else {
139 		for (i = 0, f = addr; i < DMAR_NPTEPG; i++, f += pg_sz) {
140 			if (f >= tbl->maxaddr)
141 				break;
142 			m1 = dmar_pgalloc(tbl->pgtbl_obj, base + i,
143 			    DMAR_PGF_NOALLOC);
144 			KASSERT(m1 != NULL, ("lost page table page"));
145 			pte[i].pte = (DMAR_PTE_ADDR_MASK &
146 			    VM_PAGE_TO_PHYS(m1)) | DMAR_PTE_R | DMAR_PTE_W;
147 		}
148 	}
149 	/* domain_get_idmap_pgtbl flushes CPU cache if needed. */
150 	dmar_unmap_pgtbl(sf);
151 	VM_OBJECT_WLOCK(tbl->pgtbl_obj);
152 }
153 
154 /*
155  * Find a ready and compatible identity-mapping page table in the
156  * cache. If not found, populate the identity-mapping page table for
157  * the context, up to the maxaddr. The maxaddr byte is allowed to be
158  * not mapped, which is aligned with the definition of Maxmem as the
159  * highest usable physical address + 1.  If superpages are used, the
160  * maxaddr is typically mapped.
161  */
162 vm_object_t
163 domain_get_idmap_pgtbl(struct dmar_domain *domain, dmar_gaddr_t maxaddr)
164 {
165 	struct dmar_unit *unit;
166 	struct idpgtbl *tbl;
167 	vm_object_t res;
168 	vm_page_t m;
169 	int leaf, i;
170 
171 	leaf = 0; /* silence gcc */
172 
173 	/*
174 	 * First, determine where to stop the paging structures.
175 	 */
176 	for (i = 0; i < domain->pglvl; i++) {
177 		if (i == domain->pglvl - 1 || domain_is_sp_lvl(domain, i)) {
178 			leaf = i;
179 			break;
180 		}
181 	}
182 
183 	/*
184 	 * Search the cache for a compatible page table.  Qualified
185 	 * page table must map up to maxaddr, its level must be
186 	 * supported by the DMAR and leaf should be equal to the
187 	 * calculated value.  The later restriction could be lifted
188 	 * but I believe it is currently impossible to have any
189 	 * deviations for existing hardware.
190 	 */
191 	sx_slock(&idpgtbl_lock);
192 	LIST_FOREACH(tbl, &idpgtbls, link) {
193 		if (tbl->maxaddr >= maxaddr &&
194 		    dmar_pglvl_supported(domain->dmar, tbl->pglvl) &&
195 		    tbl->leaf == leaf) {
196 			res = tbl->pgtbl_obj;
197 			vm_object_reference(res);
198 			sx_sunlock(&idpgtbl_lock);
199 			domain->pglvl = tbl->pglvl; /* XXXKIB ? */
200 			goto end;
201 		}
202 	}
203 
204 	/*
205 	 * Not found in cache, relock the cache into exclusive mode to
206 	 * be able to add element, and recheck cache again after the
207 	 * relock.
208 	 */
209 	sx_sunlock(&idpgtbl_lock);
210 	sx_xlock(&idpgtbl_lock);
211 	LIST_FOREACH(tbl, &idpgtbls, link) {
212 		if (tbl->maxaddr >= maxaddr &&
213 		    dmar_pglvl_supported(domain->dmar, tbl->pglvl) &&
214 		    tbl->leaf == leaf) {
215 			res = tbl->pgtbl_obj;
216 			vm_object_reference(res);
217 			sx_xunlock(&idpgtbl_lock);
218 			domain->pglvl = tbl->pglvl; /* XXXKIB ? */
219 			return (res);
220 		}
221 	}
222 
223 	/*
224 	 * Still not found, create new page table.
225 	 */
226 	tbl = malloc(sizeof(*tbl), M_DMAR_IDPGTBL, M_WAITOK);
227 	tbl->pglvl = domain->pglvl;
228 	tbl->leaf = leaf;
229 	tbl->maxaddr = maxaddr;
230 	tbl->pgtbl_obj = vm_pager_allocate(OBJT_PHYS, NULL,
231 	    IDX_TO_OFF(pglvl_max_pages(tbl->pglvl)), 0, 0, NULL);
232 	VM_OBJECT_WLOCK(tbl->pgtbl_obj);
233 	domain_idmap_nextlvl(tbl, 0, 0, 0);
234 	VM_OBJECT_WUNLOCK(tbl->pgtbl_obj);
235 	LIST_INSERT_HEAD(&idpgtbls, tbl, link);
236 	res = tbl->pgtbl_obj;
237 	vm_object_reference(res);
238 	sx_xunlock(&idpgtbl_lock);
239 
240 end:
241 	/*
242 	 * Table was found or created.
243 	 *
244 	 * If DMAR does not snoop paging structures accesses, flush
245 	 * CPU cache to memory.  Note that dmar_unmap_pgtbl() coherent
246 	 * argument was possibly invalid at the time of the identity
247 	 * page table creation, since DMAR which was passed at the
248 	 * time of creation could be coherent, while current DMAR is
249 	 * not.
250 	 *
251 	 * If DMAR cannot look into the chipset write buffer, flush it
252 	 * as well.
253 	 */
254 	unit = domain->dmar;
255 	if (!DMAR_IS_COHERENT(unit)) {
256 		VM_OBJECT_WLOCK(res);
257 		for (m = vm_page_lookup(res, 0); m != NULL;
258 		     m = vm_page_next(m))
259 			pmap_invalidate_cache_pages(&m, 1);
260 		VM_OBJECT_WUNLOCK(res);
261 	}
262 	if ((unit->hw_cap & DMAR_CAP_RWBF) != 0) {
263 		DMAR_LOCK(unit);
264 		dmar_flush_write_bufs(unit);
265 		DMAR_UNLOCK(unit);
266 	}
267 
268 	return (res);
269 }
270 
271 /*
272  * Return a reference to the identity mapping page table to the cache.
273  */
274 void
275 put_idmap_pgtbl(vm_object_t obj)
276 {
277 	struct idpgtbl *tbl, *tbl1;
278 	vm_object_t rmobj;
279 
280 	sx_slock(&idpgtbl_lock);
281 	KASSERT(obj->ref_count >= 2, ("lost cache reference"));
282 	vm_object_deallocate(obj);
283 
284 	/*
285 	 * Cache always owns one last reference on the page table object.
286 	 * If there is an additional reference, object must stay.
287 	 */
288 	if (obj->ref_count > 1) {
289 		sx_sunlock(&idpgtbl_lock);
290 		return;
291 	}
292 
293 	/*
294 	 * Cache reference is the last, remove cache element and free
295 	 * page table object, returning the page table pages to the
296 	 * system.
297 	 */
298 	sx_sunlock(&idpgtbl_lock);
299 	sx_xlock(&idpgtbl_lock);
300 	LIST_FOREACH_SAFE(tbl, &idpgtbls, link, tbl1) {
301 		rmobj = tbl->pgtbl_obj;
302 		if (rmobj->ref_count == 1) {
303 			LIST_REMOVE(tbl, link);
304 			atomic_subtract_int(&dmar_tbl_pagecnt,
305 			    rmobj->resident_page_count);
306 			vm_object_deallocate(rmobj);
307 			free(tbl, M_DMAR_IDPGTBL);
308 		}
309 	}
310 	sx_xunlock(&idpgtbl_lock);
311 }
312 
313 /*
314  * The core routines to map and unmap host pages at the given guest
315  * address.  Support superpages.
316  */
317 
318 /*
319  * Index of the pte for the guest address base in the page table at
320  * the level lvl.
321  */
322 static int
323 domain_pgtbl_pte_off(struct dmar_domain *domain, dmar_gaddr_t base, int lvl)
324 {
325 
326 	base >>= DMAR_PAGE_SHIFT + (domain->pglvl - lvl - 1) *
327 	    DMAR_NPTEPGSHIFT;
328 	return (base & DMAR_PTEMASK);
329 }
330 
331 /*
332  * Returns the page index of the page table page in the page table
333  * object, which maps the given address base at the page table level
334  * lvl.
335  */
336 static vm_pindex_t
337 domain_pgtbl_get_pindex(struct dmar_domain *domain, dmar_gaddr_t base, int lvl)
338 {
339 	vm_pindex_t idx, pidx;
340 	int i;
341 
342 	KASSERT(lvl >= 0 && lvl < domain->pglvl,
343 	    ("wrong lvl %p %d", domain, lvl));
344 
345 	for (pidx = idx = 0, i = 0; i < lvl; i++, pidx = idx) {
346 		idx = domain_pgtbl_pte_off(domain, base, i) +
347 		    pidx * DMAR_NPTEPG + 1;
348 	}
349 	return (idx);
350 }
351 
352 static dmar_pte_t *
353 domain_pgtbl_map_pte(struct dmar_domain *domain, dmar_gaddr_t base, int lvl,
354     int flags, vm_pindex_t *idxp, struct sf_buf **sf)
355 {
356 	vm_page_t m;
357 	struct sf_buf *sfp;
358 	dmar_pte_t *pte, *ptep;
359 	vm_pindex_t idx, idx1;
360 
361 	DMAR_DOMAIN_ASSERT_PGLOCKED(domain);
362 	KASSERT((flags & DMAR_PGF_OBJL) != 0, ("lost PGF_OBJL"));
363 
364 	idx = domain_pgtbl_get_pindex(domain, base, lvl);
365 	if (*sf != NULL && idx == *idxp) {
366 		pte = (dmar_pte_t *)sf_buf_kva(*sf);
367 	} else {
368 		if (*sf != NULL)
369 			dmar_unmap_pgtbl(*sf);
370 		*idxp = idx;
371 retry:
372 		pte = dmar_map_pgtbl(domain->pgtbl_obj, idx, flags, sf);
373 		if (pte == NULL) {
374 			KASSERT(lvl > 0,
375 			    ("lost root page table page %p", domain));
376 			/*
377 			 * Page table page does not exists, allocate
378 			 * it and create pte in the up level.
379 			 */
380 			m = dmar_pgalloc(domain->pgtbl_obj, idx, flags |
381 			    DMAR_PGF_ZERO);
382 			if (m == NULL)
383 				return (NULL);
384 
385 			/*
386 			 * Prevent potential free while pgtbl_obj is
387 			 * unlocked in the recursive call to
388 			 * domain_pgtbl_map_pte(), if other thread did
389 			 * pte write and clean while the lock is
390 			 * dropped.
391 			 */
392 			m->wire_count++;
393 
394 			sfp = NULL;
395 			ptep = domain_pgtbl_map_pte(domain, base, lvl - 1,
396 			    flags, &idx1, &sfp);
397 			if (ptep == NULL) {
398 				KASSERT(m->pindex != 0,
399 				    ("loosing root page %p", domain));
400 				m->wire_count--;
401 				dmar_pgfree(domain->pgtbl_obj, m->pindex,
402 				    flags);
403 				return (NULL);
404 			}
405 			dmar_pte_store(&ptep->pte, DMAR_PTE_R | DMAR_PTE_W |
406 			    VM_PAGE_TO_PHYS(m));
407 			dmar_flush_pte_to_ram(domain->dmar, ptep);
408 			sf_buf_page(sfp)->wire_count += 1;
409 			m->wire_count--;
410 			dmar_unmap_pgtbl(sfp);
411 			/* Only executed once. */
412 			goto retry;
413 		}
414 	}
415 	pte += domain_pgtbl_pte_off(domain, base, lvl);
416 	return (pte);
417 }
418 
419 static int
420 domain_map_buf_locked(struct dmar_domain *domain, dmar_gaddr_t base,
421     dmar_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags)
422 {
423 	dmar_pte_t *pte;
424 	struct sf_buf *sf;
425 	dmar_gaddr_t pg_sz, base1, size1;
426 	vm_pindex_t pi, c, idx, run_sz;
427 	int lvl;
428 	bool superpage;
429 
430 	DMAR_DOMAIN_ASSERT_PGLOCKED(domain);
431 
432 	base1 = base;
433 	size1 = size;
434 	flags |= DMAR_PGF_OBJL;
435 	TD_PREP_PINNED_ASSERT;
436 
437 	for (sf = NULL, pi = 0; size > 0; base += pg_sz, size -= pg_sz,
438 	    pi += run_sz) {
439 		for (lvl = 0, c = 0, superpage = false;; lvl++) {
440 			pg_sz = domain_page_size(domain, lvl);
441 			run_sz = pg_sz >> DMAR_PAGE_SHIFT;
442 			if (lvl == domain->pglvl - 1)
443 				break;
444 			/*
445 			 * Check if the current base suitable for the
446 			 * superpage mapping.  First, verify the level.
447 			 */
448 			if (!domain_is_sp_lvl(domain, lvl))
449 				continue;
450 			/*
451 			 * Next, look at the size of the mapping and
452 			 * alignment of both guest and host addresses.
453 			 */
454 			if (size < pg_sz || (base & (pg_sz - 1)) != 0 ||
455 			    (VM_PAGE_TO_PHYS(ma[pi]) & (pg_sz - 1)) != 0)
456 				continue;
457 			/* All passed, check host pages contiguouty. */
458 			if (c == 0) {
459 				for (c = 1; c < run_sz; c++) {
460 					if (VM_PAGE_TO_PHYS(ma[pi + c]) !=
461 					    VM_PAGE_TO_PHYS(ma[pi + c - 1]) +
462 					    PAGE_SIZE)
463 						break;
464 				}
465 			}
466 			if (c >= run_sz) {
467 				superpage = true;
468 				break;
469 			}
470 		}
471 		KASSERT(size >= pg_sz,
472 		    ("mapping loop overflow %p %jx %jx %jx", domain,
473 		    (uintmax_t)base, (uintmax_t)size, (uintmax_t)pg_sz));
474 		KASSERT(pg_sz > 0, ("pg_sz 0 lvl %d", lvl));
475 		pte = domain_pgtbl_map_pte(domain, base, lvl, flags, &idx, &sf);
476 		if (pte == NULL) {
477 			KASSERT((flags & DMAR_PGF_WAITOK) == 0,
478 			    ("failed waitable pte alloc %p", domain));
479 			if (sf != NULL)
480 				dmar_unmap_pgtbl(sf);
481 			domain_unmap_buf_locked(domain, base1, base - base1,
482 			    flags);
483 			TD_PINNED_ASSERT;
484 			return (ENOMEM);
485 		}
486 		dmar_pte_store(&pte->pte, VM_PAGE_TO_PHYS(ma[pi]) | pflags |
487 		    (superpage ? DMAR_PTE_SP : 0));
488 		dmar_flush_pte_to_ram(domain->dmar, pte);
489 		sf_buf_page(sf)->wire_count += 1;
490 	}
491 	if (sf != NULL)
492 		dmar_unmap_pgtbl(sf);
493 	TD_PINNED_ASSERT;
494 	return (0);
495 }
496 
497 int
498 domain_map_buf(struct dmar_domain *domain, dmar_gaddr_t base, dmar_gaddr_t size,
499     vm_page_t *ma, uint64_t pflags, int flags)
500 {
501 	struct dmar_unit *unit;
502 	int error;
503 
504 	unit = domain->dmar;
505 
506 	KASSERT((domain->flags & DMAR_DOMAIN_IDMAP) == 0,
507 	    ("modifying idmap pagetable domain %p", domain));
508 	KASSERT((base & DMAR_PAGE_MASK) == 0,
509 	    ("non-aligned base %p %jx %jx", domain, (uintmax_t)base,
510 	    (uintmax_t)size));
511 	KASSERT((size & DMAR_PAGE_MASK) == 0,
512 	    ("non-aligned size %p %jx %jx", domain, (uintmax_t)base,
513 	    (uintmax_t)size));
514 	KASSERT(size > 0, ("zero size %p %jx %jx", domain, (uintmax_t)base,
515 	    (uintmax_t)size));
516 	KASSERT(base < (1ULL << domain->agaw),
517 	    ("base too high %p %jx %jx agaw %d", domain, (uintmax_t)base,
518 	    (uintmax_t)size, domain->agaw));
519 	KASSERT(base + size < (1ULL << domain->agaw),
520 	    ("end too high %p %jx %jx agaw %d", domain, (uintmax_t)base,
521 	    (uintmax_t)size, domain->agaw));
522 	KASSERT(base + size > base,
523 	    ("size overflow %p %jx %jx", domain, (uintmax_t)base,
524 	    (uintmax_t)size));
525 	KASSERT((pflags & (DMAR_PTE_R | DMAR_PTE_W)) != 0,
526 	    ("neither read nor write %jx", (uintmax_t)pflags));
527 	KASSERT((pflags & ~(DMAR_PTE_R | DMAR_PTE_W | DMAR_PTE_SNP |
528 	    DMAR_PTE_TM)) == 0,
529 	    ("invalid pte flags %jx", (uintmax_t)pflags));
530 	KASSERT((pflags & DMAR_PTE_SNP) == 0 ||
531 	    (unit->hw_ecap & DMAR_ECAP_SC) != 0,
532 	    ("PTE_SNP for dmar without snoop control %p %jx",
533 	    domain, (uintmax_t)pflags));
534 	KASSERT((pflags & DMAR_PTE_TM) == 0 ||
535 	    (unit->hw_ecap & DMAR_ECAP_DI) != 0,
536 	    ("PTE_TM for dmar without DIOTLB %p %jx",
537 	    domain, (uintmax_t)pflags));
538 	KASSERT((flags & ~DMAR_PGF_WAITOK) == 0, ("invalid flags %x", flags));
539 
540 	DMAR_DOMAIN_PGLOCK(domain);
541 	error = domain_map_buf_locked(domain, base, size, ma, pflags, flags);
542 	DMAR_DOMAIN_PGUNLOCK(domain);
543 	if (error != 0)
544 		return (error);
545 
546 	if ((unit->hw_cap & DMAR_CAP_CM) != 0)
547 		domain_flush_iotlb_sync(domain, base, size);
548 	else if ((unit->hw_cap & DMAR_CAP_RWBF) != 0) {
549 		/* See 11.1 Write Buffer Flushing. */
550 		DMAR_LOCK(unit);
551 		dmar_flush_write_bufs(unit);
552 		DMAR_UNLOCK(unit);
553 	}
554 	return (0);
555 }
556 
557 static void domain_unmap_clear_pte(struct dmar_domain *domain,
558     dmar_gaddr_t base, int lvl, int flags, dmar_pte_t *pte,
559     struct sf_buf **sf, bool free_fs);
560 
561 static void
562 domain_free_pgtbl_pde(struct dmar_domain *domain, dmar_gaddr_t base,
563     int lvl, int flags)
564 {
565 	struct sf_buf *sf;
566 	dmar_pte_t *pde;
567 	vm_pindex_t idx;
568 
569 	sf = NULL;
570 	pde = domain_pgtbl_map_pte(domain, base, lvl, flags, &idx, &sf);
571 	domain_unmap_clear_pte(domain, base, lvl, flags, pde, &sf, true);
572 }
573 
574 static void
575 domain_unmap_clear_pte(struct dmar_domain *domain, dmar_gaddr_t base, int lvl,
576     int flags, dmar_pte_t *pte, struct sf_buf **sf, bool free_sf)
577 {
578 	vm_page_t m;
579 
580 	dmar_pte_clear(&pte->pte);
581 	dmar_flush_pte_to_ram(domain->dmar, pte);
582 	m = sf_buf_page(*sf);
583 	if (free_sf) {
584 		dmar_unmap_pgtbl(*sf);
585 		*sf = NULL;
586 	}
587 	m->wire_count--;
588 	if (m->wire_count != 0)
589 		return;
590 	KASSERT(lvl != 0,
591 	    ("lost reference (lvl) on root pg domain %p base %jx lvl %d",
592 	    domain, (uintmax_t)base, lvl));
593 	KASSERT(m->pindex != 0,
594 	    ("lost reference (idx) on root pg domain %p base %jx lvl %d",
595 	    domain, (uintmax_t)base, lvl));
596 	dmar_pgfree(domain->pgtbl_obj, m->pindex, flags);
597 	domain_free_pgtbl_pde(domain, base, lvl - 1, flags);
598 }
599 
600 /*
601  * Assumes that the unmap is never partial.
602  */
603 static int
604 domain_unmap_buf_locked(struct dmar_domain *domain, dmar_gaddr_t base,
605     dmar_gaddr_t size, int flags)
606 {
607 	dmar_pte_t *pte;
608 	struct sf_buf *sf;
609 	vm_pindex_t idx;
610 	dmar_gaddr_t pg_sz;
611 	int lvl;
612 
613 	DMAR_DOMAIN_ASSERT_PGLOCKED(domain);
614 	if (size == 0)
615 		return (0);
616 
617 	KASSERT((domain->flags & DMAR_DOMAIN_IDMAP) == 0,
618 	    ("modifying idmap pagetable domain %p", domain));
619 	KASSERT((base & DMAR_PAGE_MASK) == 0,
620 	    ("non-aligned base %p %jx %jx", domain, (uintmax_t)base,
621 	    (uintmax_t)size));
622 	KASSERT((size & DMAR_PAGE_MASK) == 0,
623 	    ("non-aligned size %p %jx %jx", domain, (uintmax_t)base,
624 	    (uintmax_t)size));
625 	KASSERT(base < (1ULL << domain->agaw),
626 	    ("base too high %p %jx %jx agaw %d", domain, (uintmax_t)base,
627 	    (uintmax_t)size, domain->agaw));
628 	KASSERT(base + size < (1ULL << domain->agaw),
629 	    ("end too high %p %jx %jx agaw %d", domain, (uintmax_t)base,
630 	    (uintmax_t)size, domain->agaw));
631 	KASSERT(base + size > base,
632 	    ("size overflow %p %jx %jx", domain, (uintmax_t)base,
633 	    (uintmax_t)size));
634 	KASSERT((flags & ~DMAR_PGF_WAITOK) == 0, ("invalid flags %x", flags));
635 
636 	pg_sz = 0; /* silence gcc */
637 	flags |= DMAR_PGF_OBJL;
638 	TD_PREP_PINNED_ASSERT;
639 
640 	for (sf = NULL; size > 0; base += pg_sz, size -= pg_sz) {
641 		for (lvl = 0; lvl < domain->pglvl; lvl++) {
642 			if (lvl != domain->pglvl - 1 &&
643 			    !domain_is_sp_lvl(domain, lvl))
644 				continue;
645 			pg_sz = domain_page_size(domain, lvl);
646 			if (pg_sz > size)
647 				continue;
648 			pte = domain_pgtbl_map_pte(domain, base, lvl, flags,
649 			    &idx, &sf);
650 			KASSERT(pte != NULL,
651 			    ("sleeping or page missed %p %jx %d 0x%x",
652 			    domain, (uintmax_t)base, lvl, flags));
653 			if ((pte->pte & DMAR_PTE_SP) != 0 ||
654 			    lvl == domain->pglvl - 1) {
655 				domain_unmap_clear_pte(domain, base, lvl,
656 				    flags, pte, &sf, false);
657 				break;
658 			}
659 		}
660 		KASSERT(size >= pg_sz,
661 		    ("unmapping loop overflow %p %jx %jx %jx", domain,
662 		    (uintmax_t)base, (uintmax_t)size, (uintmax_t)pg_sz));
663 	}
664 	if (sf != NULL)
665 		dmar_unmap_pgtbl(sf);
666 	/*
667 	 * See 11.1 Write Buffer Flushing for an explanation why RWBF
668 	 * can be ignored there.
669 	 */
670 
671 	TD_PINNED_ASSERT;
672 	return (0);
673 }
674 
675 int
676 domain_unmap_buf(struct dmar_domain *domain, dmar_gaddr_t base,
677     dmar_gaddr_t size, int flags)
678 {
679 	int error;
680 
681 	DMAR_DOMAIN_PGLOCK(domain);
682 	error = domain_unmap_buf_locked(domain, base, size, flags);
683 	DMAR_DOMAIN_PGUNLOCK(domain);
684 	return (error);
685 }
686 
687 int
688 domain_alloc_pgtbl(struct dmar_domain *domain)
689 {
690 	vm_page_t m;
691 
692 	KASSERT(domain->pgtbl_obj == NULL,
693 	    ("already initialized %p", domain));
694 
695 	domain->pgtbl_obj = vm_pager_allocate(OBJT_PHYS, NULL,
696 	    IDX_TO_OFF(pglvl_max_pages(domain->pglvl)), 0, 0, NULL);
697 	DMAR_DOMAIN_PGLOCK(domain);
698 	m = dmar_pgalloc(domain->pgtbl_obj, 0, DMAR_PGF_WAITOK |
699 	    DMAR_PGF_ZERO | DMAR_PGF_OBJL);
700 	/* No implicit free of the top level page table page. */
701 	m->wire_count = 1;
702 	DMAR_DOMAIN_PGUNLOCK(domain);
703 	DMAR_LOCK(domain->dmar);
704 	domain->flags |= DMAR_DOMAIN_PGTBL_INITED;
705 	DMAR_UNLOCK(domain->dmar);
706 	return (0);
707 }
708 
709 void
710 domain_free_pgtbl(struct dmar_domain *domain)
711 {
712 	vm_object_t obj;
713 	vm_page_t m;
714 
715 	obj = domain->pgtbl_obj;
716 	if (obj == NULL) {
717 		KASSERT((domain->dmar->hw_ecap & DMAR_ECAP_PT) != 0 &&
718 		    (domain->flags & DMAR_DOMAIN_IDMAP) != 0,
719 		    ("lost pagetable object domain %p", domain));
720 		return;
721 	}
722 	DMAR_DOMAIN_ASSERT_PGLOCKED(domain);
723 	domain->pgtbl_obj = NULL;
724 
725 	if ((domain->flags & DMAR_DOMAIN_IDMAP) != 0) {
726 		put_idmap_pgtbl(obj);
727 		domain->flags &= ~DMAR_DOMAIN_IDMAP;
728 		return;
729 	}
730 
731 	/* Obliterate wire_counts */
732 	VM_OBJECT_ASSERT_WLOCKED(obj);
733 	for (m = vm_page_lookup(obj, 0); m != NULL; m = vm_page_next(m))
734 		m->wire_count = 0;
735 	VM_OBJECT_WUNLOCK(obj);
736 	vm_object_deallocate(obj);
737 }
738 
739 static inline uint64_t
740 domain_wait_iotlb_flush(struct dmar_unit *unit, uint64_t wt, int iro)
741 {
742 	uint64_t iotlbr;
743 
744 	dmar_write8(unit, iro + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT |
745 	    DMAR_IOTLB_DR | DMAR_IOTLB_DW | wt);
746 	for (;;) {
747 		iotlbr = dmar_read8(unit, iro + DMAR_IOTLB_REG_OFF);
748 		if ((iotlbr & DMAR_IOTLB_IVT) == 0)
749 			break;
750 		cpu_spinwait();
751 	}
752 	return (iotlbr);
753 }
754 
755 void
756 domain_flush_iotlb_sync(struct dmar_domain *domain, dmar_gaddr_t base,
757     dmar_gaddr_t size)
758 {
759 	struct dmar_unit *unit;
760 	dmar_gaddr_t isize;
761 	uint64_t iotlbr;
762 	int am, iro;
763 
764 	unit = domain->dmar;
765 	KASSERT(!unit->qi_enabled, ("dmar%d: sync iotlb flush call",
766 	    unit->unit));
767 	iro = DMAR_ECAP_IRO(unit->hw_ecap) * 16;
768 	DMAR_LOCK(unit);
769 	if ((unit->hw_cap & DMAR_CAP_PSI) == 0 || size > 2 * 1024 * 1024) {
770 		iotlbr = domain_wait_iotlb_flush(unit, DMAR_IOTLB_IIRG_DOM |
771 		    DMAR_IOTLB_DID(domain->domain), iro);
772 		KASSERT((iotlbr & DMAR_IOTLB_IAIG_MASK) !=
773 		    DMAR_IOTLB_IAIG_INVLD,
774 		    ("dmar%d: invalidation failed %jx", unit->unit,
775 		    (uintmax_t)iotlbr));
776 	} else {
777 		for (; size > 0; base += isize, size -= isize) {
778 			am = calc_am(unit, base, size, &isize);
779 			dmar_write8(unit, iro, base | am);
780 			iotlbr = domain_wait_iotlb_flush(unit,
781 			    DMAR_IOTLB_IIRG_PAGE |
782 			    DMAR_IOTLB_DID(domain->domain), iro);
783 			KASSERT((iotlbr & DMAR_IOTLB_IAIG_MASK) !=
784 			    DMAR_IOTLB_IAIG_INVLD,
785 			    ("dmar%d: PSI invalidation failed "
786 			    "iotlbr 0x%jx base 0x%jx size 0x%jx am %d",
787 			    unit->unit, (uintmax_t)iotlbr,
788 			    (uintmax_t)base, (uintmax_t)size, am));
789 			/*
790 			 * Any non-page granularity covers whole guest
791 			 * address space for the domain.
792 			 */
793 			if ((iotlbr & DMAR_IOTLB_IAIG_MASK) !=
794 			    DMAR_IOTLB_IAIG_PAGE)
795 				break;
796 		}
797 	}
798 	DMAR_UNLOCK(unit);
799 }
800