1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_acpi.h" 36 #if defined(__amd64__) 37 #define DEV_APIC 38 #else 39 #include "opt_apic.h" 40 #endif 41 #include "opt_ddb.h" 42 43 #include <sys/param.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/malloc.h> 48 #include <sys/memdesc.h> 49 #include <sys/module.h> 50 #include <sys/rman.h> 51 #include <sys/rwlock.h> 52 #include <sys/smp.h> 53 #include <sys/taskqueue.h> 54 #include <sys/tree.h> 55 #include <sys/vmem.h> 56 #include <machine/bus.h> 57 #include <contrib/dev/acpica/include/acpi.h> 58 #include <contrib/dev/acpica/include/accommon.h> 59 #include <dev/acpica/acpivar.h> 60 #include <vm/vm.h> 61 #include <vm/vm_extern.h> 62 #include <vm/vm_kern.h> 63 #include <vm/vm_object.h> 64 #include <vm/vm_page.h> 65 #include <vm/vm_pager.h> 66 #include <vm/vm_map.h> 67 #include <x86/include/busdma_impl.h> 68 #include <x86/iommu/intel_reg.h> 69 #include <x86/iommu/busdma_dmar.h> 70 #include <x86/iommu/intel_dmar.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #ifdef DEV_APIC 75 #include "pcib_if.h" 76 #include <machine/intr_machdep.h> 77 #include <x86/apicreg.h> 78 #include <x86/apicvar.h> 79 #endif 80 81 #define DMAR_FAULT_IRQ_RID 0 82 #define DMAR_QI_IRQ_RID 1 83 #define DMAR_REG_RID 2 84 85 static devclass_t dmar_devclass; 86 static device_t *dmar_devs; 87 static int dmar_devcnt; 88 89 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 90 91 static void 92 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 93 { 94 ACPI_TABLE_DMAR *dmartbl; 95 ACPI_DMAR_HEADER *dmarh; 96 char *ptr, *ptrend; 97 ACPI_STATUS status; 98 99 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 100 if (ACPI_FAILURE(status)) 101 return; 102 ptr = (char *)dmartbl + sizeof(*dmartbl); 103 ptrend = (char *)dmartbl + dmartbl->Header.Length; 104 for (;;) { 105 if (ptr >= ptrend) 106 break; 107 dmarh = (ACPI_DMAR_HEADER *)ptr; 108 if (dmarh->Length <= 0) { 109 printf("dmar_identify: corrupted DMAR table, l %d\n", 110 dmarh->Length); 111 break; 112 } 113 ptr += dmarh->Length; 114 if (!iter(dmarh, arg)) 115 break; 116 } 117 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 118 } 119 120 struct find_iter_args { 121 int i; 122 ACPI_DMAR_HARDWARE_UNIT *res; 123 }; 124 125 static int 126 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 127 { 128 struct find_iter_args *fia; 129 130 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 131 return (1); 132 133 fia = arg; 134 if (fia->i == 0) { 135 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 136 return (0); 137 } 138 fia->i--; 139 return (1); 140 } 141 142 static ACPI_DMAR_HARDWARE_UNIT * 143 dmar_find_by_index(int idx) 144 { 145 struct find_iter_args fia; 146 147 fia.i = idx; 148 fia.res = NULL; 149 dmar_iterate_tbl(dmar_find_iter, &fia); 150 return (fia.res); 151 } 152 153 static int 154 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 155 { 156 157 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 158 dmar_devcnt++; 159 return (1); 160 } 161 162 static int dmar_enable = 0; 163 static void 164 dmar_identify(driver_t *driver, device_t parent) 165 { 166 ACPI_TABLE_DMAR *dmartbl; 167 ACPI_DMAR_HARDWARE_UNIT *dmarh; 168 ACPI_STATUS status; 169 int i, error; 170 171 if (acpi_disabled("dmar")) 172 return; 173 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 174 if (!dmar_enable) 175 return; 176 #ifdef INVARIANTS 177 TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free); 178 #endif 179 TUNABLE_INT_FETCH("hw.dmar.match_verbose", &dmar_match_verbose); 180 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 181 if (ACPI_FAILURE(status)) 182 return; 183 haw = dmartbl->Width + 1; 184 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 185 dmar_high = BUS_SPACE_MAXADDR; 186 else 187 dmar_high = 1ULL << (haw + 1); 188 if (bootverbose) { 189 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 190 (unsigned)dmartbl->Flags, 191 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 192 } 193 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 194 195 dmar_iterate_tbl(dmar_count_iter, NULL); 196 if (dmar_devcnt == 0) 197 return; 198 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 199 M_WAITOK | M_ZERO); 200 for (i = 0; i < dmar_devcnt; i++) { 201 dmarh = dmar_find_by_index(i); 202 if (dmarh == NULL) { 203 printf("dmar_identify: cannot find HWUNIT %d\n", i); 204 continue; 205 } 206 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 207 if (dmar_devs[i] == NULL) { 208 printf("dmar_identify: cannot create instance %d\n", i); 209 continue; 210 } 211 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 212 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 213 if (error != 0) { 214 printf( 215 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 216 i, (uintmax_t)dmarh->Address, error); 217 device_delete_child(parent, dmar_devs[i]); 218 dmar_devs[i] = NULL; 219 } 220 } 221 } 222 223 static int 224 dmar_probe(device_t dev) 225 { 226 227 if (acpi_get_handle(dev) != NULL) 228 return (ENXIO); 229 device_set_desc(dev, "DMA remap"); 230 return (BUS_PROBE_NOWILDCARD); 231 } 232 233 static void 234 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx) 235 { 236 struct dmar_msi_data *dmd; 237 238 dmd = &unit->intrs[idx]; 239 if (dmd->irq == -1) 240 return; 241 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 242 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 243 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 244 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)), 245 dev, dmd->irq); 246 dmd->irq = -1; 247 } 248 249 static void 250 dmar_release_resources(device_t dev, struct dmar_unit *unit) 251 { 252 int i; 253 254 dmar_fini_busdma(unit); 255 dmar_fini_irt(unit); 256 dmar_fini_qi(unit); 257 dmar_fini_fault_log(unit); 258 for (i = 0; i < DMAR_INTR_TOTAL; i++) 259 dmar_release_intr(dev, unit, i); 260 if (unit->regs != NULL) { 261 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 262 unit->regs); 263 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 264 unit->regs); 265 unit->regs = NULL; 266 } 267 if (unit->domids != NULL) { 268 delete_unrhdr(unit->domids); 269 unit->domids = NULL; 270 } 271 if (unit->ctx_obj != NULL) { 272 vm_object_deallocate(unit->ctx_obj); 273 unit->ctx_obj = NULL; 274 } 275 } 276 277 static int 278 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx) 279 { 280 device_t pcib; 281 struct dmar_msi_data *dmd; 282 uint64_t msi_addr; 283 uint32_t msi_data; 284 int error; 285 286 dmd = &unit->intrs[idx]; 287 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */ 288 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq); 289 if (error != 0) { 290 device_printf(dev, "cannot allocate %s interrupt, %d\n", 291 dmd->name, error); 292 goto err1; 293 } 294 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid, 295 dmd->irq, 1); 296 if (error != 0) { 297 device_printf(dev, "cannot set %s interrupt resource, %d\n", 298 dmd->name, error); 299 goto err2; 300 } 301 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 302 &dmd->irq_rid, RF_ACTIVE); 303 if (dmd->irq_res == NULL) { 304 device_printf(dev, 305 "cannot allocate resource for %s interrupt\n", dmd->name); 306 error = ENXIO; 307 goto err3; 308 } 309 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC, 310 dmd->handler, NULL, unit, &dmd->intr_handle); 311 if (error != 0) { 312 device_printf(dev, "cannot setup %s interrupt, %d\n", 313 dmd->name, error); 314 goto err4; 315 } 316 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name); 317 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data); 318 if (error != 0) { 319 device_printf(dev, "cannot map %s interrupt, %d\n", 320 dmd->name, error); 321 goto err5; 322 } 323 dmar_write4(unit, dmd->msi_data_reg, msi_data); 324 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 325 /* Only for xAPIC mode */ 326 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 327 return (0); 328 329 err5: 330 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 331 err4: 332 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 333 err3: 334 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 335 err2: 336 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq); 337 dmd->irq = -1; 338 err1: 339 return (error); 340 } 341 342 #ifdef DEV_APIC 343 static int 344 dmar_remap_intr(device_t dev, device_t child, u_int irq) 345 { 346 struct dmar_unit *unit; 347 struct dmar_msi_data *dmd; 348 uint64_t msi_addr; 349 uint32_t msi_data; 350 int i, error; 351 352 unit = device_get_softc(dev); 353 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 354 dmd = &unit->intrs[i]; 355 if (irq == dmd->irq) { 356 error = PCIB_MAP_MSI(device_get_parent( 357 device_get_parent(dev)), 358 dev, irq, &msi_addr, &msi_data); 359 if (error != 0) 360 return (error); 361 DMAR_LOCK(unit); 362 (dmd->disable_intr)(unit); 363 dmar_write4(unit, dmd->msi_data_reg, msi_data); 364 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 365 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 366 (dmd->enable_intr)(unit); 367 DMAR_UNLOCK(unit); 368 return (0); 369 } 370 } 371 return (ENOENT); 372 } 373 #endif 374 375 static void 376 dmar_print_caps(device_t dev, struct dmar_unit *unit, 377 ACPI_DMAR_HARDWARE_UNIT *dmaru) 378 { 379 uint32_t caphi, ecaphi; 380 381 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 382 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 383 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 384 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 385 caphi = unit->hw_cap >> 32; 386 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 387 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 388 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 389 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 390 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 391 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 392 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 393 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 394 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 395 printf("\n"); 396 ecaphi = unit->hw_ecap >> 32; 397 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 398 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 399 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 400 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 401 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 402 DMAR_ECAP_IRO(unit->hw_ecap)); 403 } 404 405 static int 406 dmar_attach(device_t dev) 407 { 408 struct dmar_unit *unit; 409 ACPI_DMAR_HARDWARE_UNIT *dmaru; 410 uint64_t timeout; 411 int i, error; 412 413 unit = device_get_softc(dev); 414 unit->dev = dev; 415 unit->unit = device_get_unit(dev); 416 dmaru = dmar_find_by_index(unit->unit); 417 if (dmaru == NULL) 418 return (EINVAL); 419 unit->segment = dmaru->Segment; 420 unit->base = dmaru->Address; 421 unit->reg_rid = DMAR_REG_RID; 422 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 423 &unit->reg_rid, RF_ACTIVE); 424 if (unit->regs == NULL) { 425 device_printf(dev, "cannot allocate register window\n"); 426 return (ENOMEM); 427 } 428 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 429 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 430 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 431 if (bootverbose) 432 dmar_print_caps(dev, unit, dmaru); 433 dmar_quirks_post_ident(unit); 434 435 timeout = dmar_get_timeout(); 436 TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout); 437 dmar_update_timeout(timeout); 438 439 for (i = 0; i < DMAR_INTR_TOTAL; i++) 440 unit->intrs[i].irq = -1; 441 442 unit->intrs[DMAR_INTR_FAULT].name = "fault"; 443 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; 444 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; 445 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; 446 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; 447 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; 448 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr; 449 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr; 450 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT); 451 if (error != 0) { 452 dmar_release_resources(dev, unit); 453 return (error); 454 } 455 if (DMAR_HAS_QI(unit)) { 456 unit->intrs[DMAR_INTR_QI].name = "qi"; 457 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID; 458 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr; 459 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG; 460 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG; 461 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG; 462 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr; 463 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr; 464 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI); 465 if (error != 0) { 466 dmar_release_resources(dev, unit); 467 return (error); 468 } 469 } 470 471 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF); 472 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 473 &unit->lock); 474 LIST_INIT(&unit->domains); 475 476 /* 477 * 9.2 "Context Entry": 478 * When Caching Mode (CM) field is reported as Set, the 479 * domain-id value of zero is architecturally reserved. 480 * Software must not use domain-id value of zero 481 * when CM is Set. 482 */ 483 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 484 alloc_unr_specific(unit->domids, 0); 485 486 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 487 DMAR_CTX_CNT), 0, 0, NULL); 488 489 /* 490 * Allocate and load the root entry table pointer. Enable the 491 * address translation after the required invalidations are 492 * done. 493 */ 494 dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO); 495 DMAR_LOCK(unit); 496 error = dmar_load_root_entry_ptr(unit); 497 if (error != 0) { 498 DMAR_UNLOCK(unit); 499 dmar_release_resources(dev, unit); 500 return (error); 501 } 502 error = dmar_inv_ctx_glob(unit); 503 if (error != 0) { 504 DMAR_UNLOCK(unit); 505 dmar_release_resources(dev, unit); 506 return (error); 507 } 508 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 509 error = dmar_inv_iotlb_glob(unit); 510 if (error != 0) { 511 DMAR_UNLOCK(unit); 512 dmar_release_resources(dev, unit); 513 return (error); 514 } 515 } 516 517 DMAR_UNLOCK(unit); 518 error = dmar_init_fault_log(unit); 519 if (error != 0) { 520 dmar_release_resources(dev, unit); 521 return (error); 522 } 523 error = dmar_init_qi(unit); 524 if (error != 0) { 525 dmar_release_resources(dev, unit); 526 return (error); 527 } 528 error = dmar_init_irt(unit); 529 if (error != 0) { 530 dmar_release_resources(dev, unit); 531 return (error); 532 } 533 error = dmar_init_busdma(unit); 534 if (error != 0) { 535 dmar_release_resources(dev, unit); 536 return (error); 537 } 538 539 #ifdef NOTYET 540 DMAR_LOCK(unit); 541 error = dmar_enable_translation(unit); 542 if (error != 0) { 543 DMAR_UNLOCK(unit); 544 dmar_release_resources(dev, unit); 545 return (error); 546 } 547 DMAR_UNLOCK(unit); 548 #endif 549 550 return (0); 551 } 552 553 static int 554 dmar_detach(device_t dev) 555 { 556 557 return (EBUSY); 558 } 559 560 static int 561 dmar_suspend(device_t dev) 562 { 563 564 return (0); 565 } 566 567 static int 568 dmar_resume(device_t dev) 569 { 570 571 /* XXXKIB */ 572 return (0); 573 } 574 575 static device_method_t dmar_methods[] = { 576 DEVMETHOD(device_identify, dmar_identify), 577 DEVMETHOD(device_probe, dmar_probe), 578 DEVMETHOD(device_attach, dmar_attach), 579 DEVMETHOD(device_detach, dmar_detach), 580 DEVMETHOD(device_suspend, dmar_suspend), 581 DEVMETHOD(device_resume, dmar_resume), 582 #ifdef DEV_APIC 583 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 584 #endif 585 DEVMETHOD_END 586 }; 587 588 static driver_t dmar_driver = { 589 "dmar", 590 dmar_methods, 591 sizeof(struct dmar_unit), 592 }; 593 594 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0); 595 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 596 597 static void 598 dmar_print_path(device_t dev, const char *banner, int busno, int depth, 599 const ACPI_DMAR_PCI_PATH *path) 600 { 601 int i; 602 603 device_printf(dev, "%s [%d, ", banner, busno); 604 for (i = 0; i < depth; i++) { 605 if (i != 0) 606 printf(", "); 607 printf("(%d, %d)", path[i].Device, path[i].Function); 608 } 609 printf("]\n"); 610 } 611 612 static int 613 dmar_dev_depth(device_t child) 614 { 615 devclass_t pci_class; 616 device_t bus, pcib; 617 int depth; 618 619 pci_class = devclass_find("pci"); 620 for (depth = 1; ; depth++) { 621 bus = device_get_parent(child); 622 pcib = device_get_parent(bus); 623 if (device_get_devclass(device_get_parent(pcib)) != 624 pci_class) 625 return (depth); 626 child = pcib; 627 } 628 } 629 630 static void 631 dmar_dev_path(device_t child, int *busno, ACPI_DMAR_PCI_PATH *path, int depth) 632 { 633 devclass_t pci_class; 634 device_t bus, pcib; 635 636 pci_class = devclass_find("pci"); 637 for (depth--; depth != -1; depth--) { 638 path[depth].Device = pci_get_slot(child); 639 path[depth].Function = pci_get_function(child); 640 bus = device_get_parent(child); 641 pcib = device_get_parent(bus); 642 if (device_get_devclass(device_get_parent(pcib)) != 643 pci_class) { 644 /* reached a host bridge */ 645 *busno = pcib_get_bus(bus); 646 return; 647 } 648 child = pcib; 649 } 650 panic("wrong depth"); 651 } 652 653 static int 654 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 655 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 656 enum AcpiDmarScopeType scope_type) 657 { 658 int i, depth; 659 660 if (busno1 != busno2) 661 return (0); 662 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 663 return (0); 664 depth = depth1; 665 if (depth2 < depth) 666 depth = depth2; 667 for (i = 0; i < depth; i++) { 668 if (path1[i].Device != path2[i].Device || 669 path1[i].Function != path2[i].Function) 670 return (0); 671 } 672 return (1); 673 } 674 675 static int 676 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, device_t dev, 677 int dev_busno, const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 678 { 679 ACPI_DMAR_PCI_PATH *path; 680 int path_len; 681 682 if (devscope->Length < sizeof(*devscope)) { 683 printf("dmar_find: corrupted DMAR table, dl %d\n", 684 devscope->Length); 685 return (-1); 686 } 687 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 688 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 689 return (0); 690 path_len = devscope->Length - sizeof(*devscope); 691 if (path_len % 2 != 0) { 692 printf("dmar_find_bsf: corrupted DMAR table, dl %d\n", 693 devscope->Length); 694 return (-1); 695 } 696 path_len /= 2; 697 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 698 if (path_len == 0) { 699 printf("dmar_find: corrupted DMAR table, dl %d\n", 700 devscope->Length); 701 return (-1); 702 } 703 if (dmar_match_verbose) 704 dmar_print_path(dev, "DMAR", devscope->Bus, path_len, path); 705 706 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 707 dev_path, dev_path_len, devscope->EntryType)); 708 } 709 710 struct dmar_unit * 711 dmar_find(device_t dev) 712 { 713 device_t dmar_dev; 714 ACPI_DMAR_HARDWARE_UNIT *dmarh; 715 ACPI_DMAR_DEVICE_SCOPE *devscope; 716 char *ptr, *ptrend; 717 int i, match, dev_domain, dev_busno, dev_path_len; 718 719 dmar_dev = NULL; 720 dev_domain = pci_get_domain(dev); 721 dev_path_len = dmar_dev_depth(dev); 722 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 723 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 724 if (dmar_match_verbose) 725 dmar_print_path(dev, "PCI", dev_busno, dev_path_len, dev_path); 726 727 for (i = 0; i < dmar_devcnt; i++) { 728 if (dmar_devs[i] == NULL) 729 continue; 730 dmarh = dmar_find_by_index(i); 731 if (dmarh == NULL) 732 continue; 733 if (dmarh->Segment != dev_domain) 734 continue; 735 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 736 dmar_dev = dmar_devs[i]; 737 if (dmar_match_verbose) { 738 device_printf(dev, 739 "pci%d:%d:%d:%d matched dmar%d INCLUDE_ALL\n", 740 dev_domain, pci_get_bus(dev), 741 pci_get_slot(dev), 742 pci_get_function(dev), 743 ((struct dmar_unit *)device_get_softc( 744 dmar_dev))->unit); 745 } 746 goto found; 747 } 748 ptr = (char *)dmarh + sizeof(*dmarh); 749 ptrend = (char *)dmarh + dmarh->Header.Length; 750 for (;;) { 751 if (ptr >= ptrend) 752 break; 753 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 754 ptr += devscope->Length; 755 if (dmar_match_verbose) { 756 device_printf(dev, 757 "pci%d:%d:%d:%d matching dmar%d\n", 758 dev_domain, pci_get_bus(dev), 759 pci_get_slot(dev), 760 pci_get_function(dev), 761 ((struct dmar_unit *)device_get_softc( 762 dmar_devs[i]))->unit); 763 } 764 match = dmar_match_devscope(devscope, dev, dev_busno, 765 dev_path, dev_path_len); 766 if (dmar_match_verbose) { 767 if (match == -1) 768 printf("table error\n"); 769 else if (match == 0) 770 printf("not matched\n"); 771 else 772 printf("matched\n"); 773 } 774 if (match == -1) 775 return (NULL); 776 else if (match == 1) { 777 dmar_dev = dmar_devs[i]; 778 goto found; 779 } 780 } 781 } 782 return (NULL); 783 found: 784 return (device_get_softc(dmar_dev)); 785 } 786 787 static struct dmar_unit * 788 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 789 { 790 device_t dmar_dev; 791 struct dmar_unit *unit; 792 ACPI_DMAR_HARDWARE_UNIT *dmarh; 793 ACPI_DMAR_DEVICE_SCOPE *devscope; 794 ACPI_DMAR_PCI_PATH *path; 795 char *ptr, *ptrend; 796 #ifdef DEV_APIC 797 int error; 798 #endif 799 int i; 800 801 for (i = 0; i < dmar_devcnt; i++) { 802 dmar_dev = dmar_devs[i]; 803 if (dmar_dev == NULL) 804 continue; 805 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 806 dmarh = dmar_find_by_index(i); 807 if (dmarh == NULL) 808 continue; 809 ptr = (char *)dmarh + sizeof(*dmarh); 810 ptrend = (char *)dmarh + dmarh->Header.Length; 811 for (;;) { 812 if (ptr >= ptrend) 813 break; 814 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 815 ptr += devscope->Length; 816 if (devscope->EntryType != entry_type) 817 continue; 818 if (devscope->EnumerationId != id) 819 continue; 820 #ifdef DEV_APIC 821 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 822 error = ioapic_get_rid(id, rid); 823 /* 824 * If our IOAPIC has PCI bindings then 825 * use the PCI device rid. 826 */ 827 if (error == 0) 828 return (unit); 829 } 830 #endif 831 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 832 == 2) { 833 if (rid != NULL) { 834 path = (ACPI_DMAR_PCI_PATH *) 835 (devscope + 1); 836 *rid = PCI_RID(devscope->Bus, 837 path->Device, path->Function); 838 } 839 return (unit); 840 } 841 printf( 842 "dmar_find_nonpci: id %d type %d path length != 2\n", 843 id, entry_type); 844 break; 845 } 846 } 847 return (NULL); 848 } 849 850 851 struct dmar_unit * 852 dmar_find_hpet(device_t dev, uint16_t *rid) 853 { 854 855 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 856 rid)); 857 } 858 859 struct dmar_unit * 860 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 861 { 862 863 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 864 } 865 866 struct rmrr_iter_args { 867 struct dmar_domain *domain; 868 device_t dev; 869 int dev_domain; 870 int dev_busno; 871 ACPI_DMAR_PCI_PATH *dev_path; 872 int dev_path_len; 873 struct dmar_map_entries_tailq *rmrr_entries; 874 }; 875 876 static int 877 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 878 { 879 struct rmrr_iter_args *ria; 880 ACPI_DMAR_RESERVED_MEMORY *resmem; 881 ACPI_DMAR_DEVICE_SCOPE *devscope; 882 struct dmar_map_entry *entry; 883 char *ptr, *ptrend; 884 int match; 885 886 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 887 return (1); 888 889 ria = arg; 890 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 891 if (dmar_match_verbose) { 892 printf("RMRR [%jx,%jx] segment %d\n", 893 (uintmax_t)resmem->BaseAddress, 894 (uintmax_t)resmem->EndAddress, 895 resmem->Segment); 896 } 897 if (resmem->Segment != ria->dev_domain) 898 return (1); 899 900 ptr = (char *)resmem + sizeof(*resmem); 901 ptrend = (char *)resmem + resmem->Header.Length; 902 for (;;) { 903 if (ptr >= ptrend) 904 break; 905 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 906 ptr += devscope->Length; 907 match = dmar_match_devscope(devscope, ria->dev, ria->dev_busno, 908 ria->dev_path, ria->dev_path_len); 909 if (match == 1) { 910 if (dmar_match_verbose) 911 printf("matched\n"); 912 entry = dmar_gas_alloc_entry(ria->domain, 913 DMAR_PGF_WAITOK); 914 entry->start = resmem->BaseAddress; 915 /* The RMRR entry end address is inclusive. */ 916 entry->end = resmem->EndAddress; 917 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 918 unroll_link); 919 } else if (dmar_match_verbose) { 920 printf("not matched, err %d\n", match); 921 } 922 } 923 924 return (1); 925 } 926 927 void 928 dmar_dev_parse_rmrr(struct dmar_domain *domain, device_t dev, 929 struct dmar_map_entries_tailq *rmrr_entries) 930 { 931 struct rmrr_iter_args ria; 932 933 ria.dev_domain = pci_get_domain(dev); 934 ria.dev_path_len = dmar_dev_depth(dev); 935 ACPI_DMAR_PCI_PATH dev_path[ria.dev_path_len]; 936 dmar_dev_path(dev, &ria.dev_busno, dev_path, ria.dev_path_len); 937 938 if (dmar_match_verbose) { 939 device_printf(dev, "parsing RMRR entries for "); 940 dmar_print_path(dev, "PCI", ria.dev_busno, ria.dev_path_len, 941 dev_path); 942 } 943 944 ria.domain = domain; 945 ria.dev = dev; 946 ria.dev_path = dev_path; 947 ria.rmrr_entries = rmrr_entries; 948 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 949 } 950 951 struct inst_rmrr_iter_args { 952 struct dmar_unit *dmar; 953 }; 954 955 static device_t 956 dmar_path_dev(int segment, int path_len, int busno, 957 const ACPI_DMAR_PCI_PATH *path) 958 { 959 devclass_t pci_class; 960 device_t bus, pcib, dev; 961 int i; 962 963 pci_class = devclass_find("pci"); 964 dev = NULL; 965 for (i = 0; i < path_len; i++, path++) { 966 dev = pci_find_dbsf(segment, busno, path->Device, 967 path->Function); 968 if (dev == NULL) 969 break; 970 if (i != path_len - 1) { 971 bus = device_get_parent(dev); 972 pcib = device_get_parent(bus); 973 if (device_get_devclass(device_get_parent(pcib)) != 974 pci_class) 975 return (NULL); 976 } 977 busno = pcib_get_bus(dev); 978 } 979 return (dev); 980 } 981 982 static int 983 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 984 { 985 const ACPI_DMAR_RESERVED_MEMORY *resmem; 986 const ACPI_DMAR_DEVICE_SCOPE *devscope; 987 struct inst_rmrr_iter_args *iria; 988 const char *ptr, *ptrend; 989 struct dmar_unit *dev_dmar; 990 device_t dev; 991 992 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 993 return (1); 994 995 iria = arg; 996 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 997 if (resmem->Segment != iria->dmar->segment) 998 return (1); 999 if (dmar_match_verbose) { 1000 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit, 1001 (uintmax_t)resmem->BaseAddress, 1002 (uintmax_t)resmem->EndAddress); 1003 } 1004 1005 ptr = (const char *)resmem + sizeof(*resmem); 1006 ptrend = (const char *)resmem + resmem->Header.Length; 1007 for (;;) { 1008 if (ptr >= ptrend) 1009 break; 1010 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 1011 ptr += devscope->Length; 1012 /* XXXKIB bridge */ 1013 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 1014 continue; 1015 if (dmar_match_verbose) { 1016 dmar_print_path(iria->dmar->dev, "RMRR scope", 1017 devscope->Bus, (devscope->Length - 1018 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, 1019 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1020 } 1021 dev = dmar_path_dev(resmem->Segment, (devscope->Length - 1022 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, devscope->Bus, 1023 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1024 if (dev == NULL) { 1025 if (dmar_match_verbose) 1026 printf("null dev\n"); 1027 continue; 1028 } 1029 dev_dmar = dmar_find(dev); 1030 if (dev_dmar != iria->dmar) { 1031 if (dmar_match_verbose) { 1032 printf("dmar%d matched, skipping\n", 1033 dev_dmar->unit); 1034 } 1035 continue; 1036 } 1037 if (dmar_match_verbose) 1038 printf("matched, instantiating RMRR context\n"); 1039 dmar_instantiate_ctx(iria->dmar, dev, true); 1040 } 1041 1042 return (1); 1043 1044 } 1045 1046 /* 1047 * Pre-create all contexts for the DMAR which have RMRR entries. 1048 */ 1049 int 1050 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar) 1051 { 1052 struct inst_rmrr_iter_args iria; 1053 int error; 1054 1055 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1056 return (0); 1057 1058 error = 0; 1059 iria.dmar = dmar; 1060 if (dmar_match_verbose) 1061 printf("dmar%d: instantiating RMRR contexts\n", dmar->unit); 1062 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1063 DMAR_LOCK(dmar); 1064 if (!LIST_EMPTY(&dmar->domains)) { 1065 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1066 ("dmar%d: RMRR not handled but translation is already enabled", 1067 dmar->unit)); 1068 error = dmar_enable_translation(dmar); 1069 } 1070 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1071 return (error); 1072 } 1073 1074 #ifdef DDB 1075 #include <ddb/ddb.h> 1076 #include <ddb/db_lex.h> 1077 1078 static void 1079 dmar_print_domain_entry(const struct dmar_map_entry *entry) 1080 { 1081 struct dmar_map_entry *l, *r; 1082 1083 db_printf( 1084 " start %jx end %jx free_after %jx free_down %jx flags %x ", 1085 entry->start, entry->end, entry->free_after, entry->free_down, 1086 entry->flags); 1087 db_printf("left "); 1088 l = RB_LEFT(entry, rb_entry); 1089 if (l == NULL) 1090 db_printf("NULL "); 1091 else 1092 db_printf("%jx ", l->start); 1093 db_printf("right "); 1094 r = RB_RIGHT(entry, rb_entry); 1095 if (r == NULL) 1096 db_printf("NULL"); 1097 else 1098 db_printf("%jx", r->start); 1099 db_printf("\n"); 1100 } 1101 1102 static void 1103 dmar_print_ctx(struct dmar_ctx *ctx) 1104 { 1105 1106 db_printf( 1107 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n", 1108 ctx, pci_get_bus(ctx->ctx_tag.owner), 1109 pci_get_slot(ctx->ctx_tag.owner), 1110 pci_get_function(ctx->ctx_tag.owner), ctx->refs, ctx->flags, 1111 ctx->loads, ctx->unloads); 1112 } 1113 1114 static void 1115 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1116 { 1117 struct dmar_map_entry *entry; 1118 struct dmar_ctx *ctx; 1119 1120 db_printf( 1121 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1122 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1123 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1124 (uintmax_t)domain->end, domain->refs, domain->ctx_cnt, 1125 domain->flags, domain->pgtbl_obj, domain->entries_cnt); 1126 if (!LIST_EMPTY(&domain->contexts)) { 1127 db_printf(" Contexts:\n"); 1128 LIST_FOREACH(ctx, &domain->contexts, link) 1129 dmar_print_ctx(ctx); 1130 } 1131 if (!show_mappings) 1132 return; 1133 db_printf(" mapped:\n"); 1134 RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) { 1135 dmar_print_domain_entry(entry); 1136 if (db_pager_quit) 1137 break; 1138 } 1139 if (db_pager_quit) 1140 return; 1141 db_printf(" unloading:\n"); 1142 TAILQ_FOREACH(entry, &domain->unload_entries, dmamap_link) { 1143 dmar_print_domain_entry(entry); 1144 if (db_pager_quit) 1145 break; 1146 } 1147 } 1148 1149 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL) 1150 { 1151 struct dmar_unit *unit; 1152 struct dmar_domain *domain; 1153 struct dmar_ctx *ctx; 1154 bool show_mappings, valid; 1155 int pci_domain, bus, device, function, i, t; 1156 db_expr_t radix; 1157 1158 valid = false; 1159 radix = db_radix; 1160 db_radix = 10; 1161 t = db_read_token(); 1162 if (t == tSLASH) { 1163 t = db_read_token(); 1164 if (t != tIDENT) { 1165 db_printf("Bad modifier\n"); 1166 db_radix = radix; 1167 db_skip_to_eol(); 1168 return; 1169 } 1170 show_mappings = strchr(db_tok_string, 'm') != NULL; 1171 t = db_read_token(); 1172 } else { 1173 show_mappings = false; 1174 } 1175 if (t == tNUMBER) { 1176 pci_domain = db_tok_number; 1177 t = db_read_token(); 1178 if (t == tNUMBER) { 1179 bus = db_tok_number; 1180 t = db_read_token(); 1181 if (t == tNUMBER) { 1182 device = db_tok_number; 1183 t = db_read_token(); 1184 if (t == tNUMBER) { 1185 function = db_tok_number; 1186 valid = true; 1187 } 1188 } 1189 } 1190 } 1191 db_radix = radix; 1192 db_skip_to_eol(); 1193 if (!valid) { 1194 db_printf("usage: show dmar_domain [/m] " 1195 "<domain> <bus> <device> <func>\n"); 1196 return; 1197 } 1198 for (i = 0; i < dmar_devcnt; i++) { 1199 unit = device_get_softc(dmar_devs[i]); 1200 LIST_FOREACH(domain, &unit->domains, link) { 1201 LIST_FOREACH(ctx, &domain->contexts, link) { 1202 if (pci_domain == unit->segment && 1203 bus == pci_get_bus(ctx->ctx_tag.owner) && 1204 device == 1205 pci_get_slot(ctx->ctx_tag.owner) && 1206 function == 1207 pci_get_function(ctx->ctx_tag.owner)) { 1208 dmar_print_domain(domain, 1209 show_mappings); 1210 goto out; 1211 } 1212 } 1213 } 1214 } 1215 out:; 1216 } 1217 1218 static void 1219 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1220 { 1221 struct dmar_unit *unit; 1222 struct dmar_domain *domain; 1223 int i, frir; 1224 1225 unit = device_get_softc(dmar_devs[idx]); 1226 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit, 1227 dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG)); 1228 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1229 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1230 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1231 dmar_read4(unit, DMAR_GSTS_REG), 1232 dmar_read4(unit, DMAR_FSTS_REG), 1233 dmar_read4(unit, DMAR_FECTL_REG)); 1234 if (unit->ir_enabled) { 1235 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1236 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1237 } 1238 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1239 dmar_read4(unit, DMAR_FEDATA_REG), 1240 dmar_read4(unit, DMAR_FEADDR_REG), 1241 dmar_read4(unit, DMAR_FEUADDR_REG)); 1242 db_printf("primary fault log:\n"); 1243 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1244 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1245 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1246 (uintmax_t)dmar_read8(unit, frir), 1247 (uintmax_t)dmar_read8(unit, frir + 8)); 1248 } 1249 if (DMAR_HAS_QI(unit)) { 1250 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1251 dmar_read4(unit, DMAR_IEDATA_REG), 1252 dmar_read4(unit, DMAR_IEADDR_REG), 1253 dmar_read4(unit, DMAR_IEUADDR_REG)); 1254 if (unit->qi_enabled) { 1255 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1256 "size 0x%jx\n" 1257 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1258 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1259 (uintmax_t)unit->inv_queue, 1260 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1261 (uintmax_t)unit->inv_queue_size, 1262 dmar_read4(unit, DMAR_IQH_REG), 1263 dmar_read4(unit, DMAR_IQT_REG), 1264 unit->inv_queue_avail, 1265 dmar_read4(unit, DMAR_ICS_REG), 1266 dmar_read4(unit, DMAR_IECTL_REG), 1267 unit->inv_waitd_seq_hw, 1268 &unit->inv_waitd_seq_hw, 1269 (uintmax_t)unit->inv_waitd_seq_hw_phys, 1270 unit->inv_waitd_seq, 1271 unit->inv_waitd_gen); 1272 } else { 1273 db_printf("qi is disabled\n"); 1274 } 1275 } 1276 if (show_domains) { 1277 db_printf("domains:\n"); 1278 LIST_FOREACH(domain, &unit->domains, link) { 1279 dmar_print_domain(domain, show_mappings); 1280 if (db_pager_quit) 1281 break; 1282 } 1283 } 1284 } 1285 1286 DB_SHOW_COMMAND(dmar, db_dmar_print) 1287 { 1288 bool show_domains, show_mappings; 1289 1290 show_domains = strchr(modif, 'd') != NULL; 1291 show_mappings = strchr(modif, 'm') != NULL; 1292 if (!have_addr) { 1293 db_printf("usage: show dmar [/d] [/m] index\n"); 1294 return; 1295 } 1296 dmar_print_one((int)addr, show_domains, show_mappings); 1297 } 1298 1299 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1300 { 1301 int i; 1302 bool show_domains, show_mappings; 1303 1304 show_domains = strchr(modif, 'd') != NULL; 1305 show_mappings = strchr(modif, 'm') != NULL; 1306 1307 for (i = 0; i < dmar_devcnt; i++) { 1308 dmar_print_one(i, show_domains, show_mappings); 1309 if (db_pager_quit) 1310 break; 1311 } 1312 } 1313 #endif 1314