1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "opt_acpi.h" 32 #if defined(__amd64__) 33 #define DEV_APIC 34 #else 35 #include "opt_apic.h" 36 #endif 37 #include "opt_ddb.h" 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/memdesc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/rman.h> 48 #include <sys/rwlock.h> 49 #include <sys/smp.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 #include <sys/vmem.h> 53 #include <vm/vm.h> 54 #include <vm/vm_extern.h> 55 #include <vm/vm_kern.h> 56 #include <vm/vm_object.h> 57 #include <vm/vm_page.h> 58 #include <vm/vm_pager.h> 59 #include <vm/vm_map.h> 60 #include <contrib/dev/acpica/include/acpi.h> 61 #include <contrib/dev/acpica/include/accommon.h> 62 #include <dev/acpica/acpivar.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <machine/bus.h> 66 #include <machine/pci_cfgreg.h> 67 #include <machine/md_var.h> 68 #include <machine/cputypes.h> 69 #include <x86/include/busdma_impl.h> 70 #include <dev/iommu/busdma_iommu.h> 71 #include <x86/iommu/intel_reg.h> 72 #include <x86/iommu/x86_iommu.h> 73 #include <x86/iommu/intel_dmar.h> 74 75 #ifdef DEV_APIC 76 #include "pcib_if.h" 77 #include <machine/intr_machdep.h> 78 #include <x86/apicreg.h> 79 #include <x86/apicvar.h> 80 #endif 81 82 #define DMAR_FAULT_IRQ_RID 0 83 #define DMAR_QI_IRQ_RID 1 84 #define DMAR_REG_RID 2 85 86 static device_t *dmar_devs; 87 static int dmar_devcnt; 88 89 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 90 91 static void 92 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 93 { 94 ACPI_TABLE_DMAR *dmartbl; 95 ACPI_DMAR_HEADER *dmarh; 96 char *ptr, *ptrend; 97 ACPI_STATUS status; 98 99 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 100 if (ACPI_FAILURE(status)) 101 return; 102 ptr = (char *)dmartbl + sizeof(*dmartbl); 103 ptrend = (char *)dmartbl + dmartbl->Header.Length; 104 for (;;) { 105 if (ptr >= ptrend) 106 break; 107 dmarh = (ACPI_DMAR_HEADER *)ptr; 108 if (dmarh->Length <= 0) { 109 printf("dmar_identify: corrupted DMAR table, l %d\n", 110 dmarh->Length); 111 break; 112 } 113 ptr += dmarh->Length; 114 if (!iter(dmarh, arg)) 115 break; 116 } 117 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 118 } 119 120 struct find_iter_args { 121 int i; 122 ACPI_DMAR_HARDWARE_UNIT *res; 123 }; 124 125 static int 126 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 127 { 128 struct find_iter_args *fia; 129 130 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 131 return (1); 132 133 fia = arg; 134 if (fia->i == 0) { 135 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 136 return (0); 137 } 138 fia->i--; 139 return (1); 140 } 141 142 static ACPI_DMAR_HARDWARE_UNIT * 143 dmar_find_by_index(int idx) 144 { 145 struct find_iter_args fia; 146 147 fia.i = idx; 148 fia.res = NULL; 149 dmar_iterate_tbl(dmar_find_iter, &fia); 150 return (fia.res); 151 } 152 153 static int 154 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 155 { 156 157 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 158 dmar_devcnt++; 159 return (1); 160 } 161 162 int dmar_rmrr_enable = 1; 163 164 static int dmar_enable = 0; 165 static void 166 dmar_identify(driver_t *driver, device_t parent) 167 { 168 ACPI_TABLE_DMAR *dmartbl; 169 ACPI_DMAR_HARDWARE_UNIT *dmarh; 170 ACPI_STATUS status; 171 int i, error; 172 173 if (acpi_disabled("dmar")) 174 return; 175 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 176 if (!dmar_enable) 177 return; 178 TUNABLE_INT_FETCH("hw.dmar.rmrr_enable", &dmar_rmrr_enable); 179 180 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 181 if (ACPI_FAILURE(status)) 182 return; 183 haw = dmartbl->Width + 1; 184 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 185 iommu_high = BUS_SPACE_MAXADDR; 186 else 187 iommu_high = 1ULL << (haw + 1); 188 if (bootverbose) { 189 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 190 (unsigned)dmartbl->Flags, 191 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 192 } 193 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 194 195 dmar_iterate_tbl(dmar_count_iter, NULL); 196 if (dmar_devcnt == 0) 197 return; 198 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 199 M_WAITOK | M_ZERO); 200 for (i = 0; i < dmar_devcnt; i++) { 201 dmarh = dmar_find_by_index(i); 202 if (dmarh == NULL) { 203 printf("dmar_identify: cannot find HWUNIT %d\n", i); 204 continue; 205 } 206 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 207 if (dmar_devs[i] == NULL) { 208 printf("dmar_identify: cannot create instance %d\n", i); 209 continue; 210 } 211 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 212 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 213 if (error != 0) { 214 printf( 215 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 216 i, (uintmax_t)dmarh->Address, error); 217 device_delete_child(parent, dmar_devs[i]); 218 dmar_devs[i] = NULL; 219 } 220 } 221 } 222 223 static int 224 dmar_probe(device_t dev) 225 { 226 227 if (acpi_get_handle(dev) != NULL) 228 return (ENXIO); 229 device_set_desc(dev, "DMA remap"); 230 return (BUS_PROBE_NOWILDCARD); 231 } 232 233 static void 234 dmar_release_resources(device_t dev, struct dmar_unit *unit) 235 { 236 int i; 237 238 iommu_fini_busdma(&unit->iommu); 239 dmar_fini_irt(unit); 240 dmar_fini_qi(unit); 241 dmar_fini_fault_log(unit); 242 for (i = 0; i < DMAR_INTR_TOTAL; i++) 243 iommu_release_intr(DMAR2IOMMU(unit), i); 244 if (unit->regs != NULL) { 245 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 246 unit->regs); 247 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 248 unit->regs); 249 unit->regs = NULL; 250 } 251 if (unit->domids != NULL) { 252 delete_unrhdr(unit->domids); 253 unit->domids = NULL; 254 } 255 if (unit->ctx_obj != NULL) { 256 vm_object_deallocate(unit->ctx_obj); 257 unit->ctx_obj = NULL; 258 } 259 sysctl_ctx_free(&unit->iommu.sysctl_ctx); 260 } 261 262 #ifdef DEV_APIC 263 static int 264 dmar_remap_intr(device_t dev, device_t child, u_int irq) 265 { 266 struct dmar_unit *unit; 267 struct iommu_msi_data *dmd; 268 uint64_t msi_addr; 269 uint32_t msi_data; 270 int i, error; 271 272 unit = device_get_softc(dev); 273 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 274 dmd = &unit->x86c.intrs[i]; 275 if (irq == dmd->irq) { 276 error = PCIB_MAP_MSI(device_get_parent( 277 device_get_parent(dev)), 278 dev, irq, &msi_addr, &msi_data); 279 if (error != 0) 280 return (error); 281 DMAR_LOCK(unit); 282 dmd->msi_data = msi_data; 283 dmd->msi_addr = msi_addr; 284 (dmd->disable_intr)(DMAR2IOMMU(unit)); 285 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); 286 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); 287 dmar_write4(unit, dmd->msi_uaddr_reg, 288 dmd->msi_addr >> 32); 289 (dmd->enable_intr)(DMAR2IOMMU(unit)); 290 DMAR_UNLOCK(unit); 291 return (0); 292 } 293 } 294 return (ENOENT); 295 } 296 #endif 297 298 static void 299 dmar_print_caps(device_t dev, struct dmar_unit *unit, 300 ACPI_DMAR_HARDWARE_UNIT *dmaru) 301 { 302 uint32_t caphi, ecaphi; 303 304 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 305 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 306 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 307 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 308 caphi = unit->hw_cap >> 32; 309 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 310 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 311 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 312 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 313 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 314 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 315 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 316 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 317 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 318 printf("\n"); 319 ecaphi = unit->hw_ecap >> 32; 320 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 321 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 322 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 323 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 324 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 325 DMAR_ECAP_IRO(unit->hw_ecap)); 326 } 327 328 static int 329 dmar_attach(device_t dev) 330 { 331 struct dmar_unit *unit; 332 ACPI_DMAR_HARDWARE_UNIT *dmaru; 333 struct iommu_msi_data *dmd; 334 uint64_t timeout; 335 int disable_pmr; 336 int i, error; 337 338 unit = device_get_softc(dev); 339 unit->iommu.unit = device_get_unit(dev); 340 unit->iommu.dev = dev; 341 sysctl_ctx_init(&unit->iommu.sysctl_ctx); 342 dmaru = dmar_find_by_index(unit->iommu.unit); 343 if (dmaru == NULL) 344 return (EINVAL); 345 unit->segment = dmaru->Segment; 346 unit->base = dmaru->Address; 347 unit->reg_rid = DMAR_REG_RID; 348 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 349 &unit->reg_rid, RF_ACTIVE); 350 if (unit->regs == NULL) { 351 device_printf(dev, "cannot allocate register window\n"); 352 dmar_devs[unit->iommu.unit] = NULL; 353 return (ENOMEM); 354 } 355 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 356 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 357 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 358 if (bootverbose) 359 dmar_print_caps(dev, unit, dmaru); 360 dmar_quirks_post_ident(unit); 361 362 timeout = dmar_get_timeout(); 363 TUNABLE_UINT64_FETCH("hw.iommu.dmar.timeout", &timeout); 364 dmar_update_timeout(timeout); 365 366 for (i = 0; i < DMAR_INTR_TOTAL; i++) 367 unit->x86c.intrs[i].irq = -1; 368 369 dmd = &unit->x86c.intrs[DMAR_INTR_FAULT]; 370 dmd->name = "fault"; 371 dmd->irq_rid = DMAR_FAULT_IRQ_RID; 372 dmd->handler = dmar_fault_intr; 373 dmd->msi_data_reg = DMAR_FEDATA_REG; 374 dmd->msi_addr_reg = DMAR_FEADDR_REG; 375 dmd->msi_uaddr_reg = DMAR_FEUADDR_REG; 376 dmd->enable_intr = dmar_enable_fault_intr; 377 dmd->disable_intr = dmar_disable_fault_intr; 378 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_FAULT); 379 if (error != 0) { 380 dmar_release_resources(dev, unit); 381 dmar_devs[unit->iommu.unit] = NULL; 382 return (error); 383 } 384 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); 385 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); 386 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); 387 388 if (DMAR_HAS_QI(unit)) { 389 dmd = &unit->x86c.intrs[DMAR_INTR_QI]; 390 dmd->name = "qi"; 391 dmd->irq_rid = DMAR_QI_IRQ_RID; 392 dmd->handler = dmar_qi_intr; 393 dmd->msi_data_reg = DMAR_IEDATA_REG; 394 dmd->msi_addr_reg = DMAR_IEADDR_REG; 395 dmd->msi_uaddr_reg = DMAR_IEUADDR_REG; 396 dmd->enable_intr = dmar_enable_qi_intr; 397 dmd->disable_intr = dmar_disable_qi_intr; 398 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_QI); 399 if (error != 0) { 400 dmar_release_resources(dev, unit); 401 dmar_devs[unit->iommu.unit] = NULL; 402 return (error); 403 } 404 405 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); 406 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); 407 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); 408 } 409 410 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); 411 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 412 &unit->iommu.lock); 413 LIST_INIT(&unit->domains); 414 415 /* 416 * 9.2 "Context Entry": 417 * When Caching Mode (CM) field is reported as Set, the 418 * domain-id value of zero is architecturally reserved. 419 * Software must not use domain-id value of zero 420 * when CM is Set. 421 */ 422 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 423 alloc_unr_specific(unit->domids, 0); 424 425 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 426 DMAR_CTX_CNT), 0, 0, NULL); 427 428 /* 429 * Allocate and load the root entry table pointer. Enable the 430 * address translation after the required invalidations are 431 * done. 432 */ 433 iommu_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); 434 DMAR_LOCK(unit); 435 error = dmar_load_root_entry_ptr(unit); 436 if (error != 0) { 437 DMAR_UNLOCK(unit); 438 dmar_release_resources(dev, unit); 439 dmar_devs[unit->iommu.unit] = NULL; 440 return (error); 441 } 442 error = dmar_inv_ctx_glob(unit); 443 if (error != 0) { 444 DMAR_UNLOCK(unit); 445 dmar_release_resources(dev, unit); 446 dmar_devs[unit->iommu.unit] = NULL; 447 return (error); 448 } 449 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 450 error = dmar_inv_iotlb_glob(unit); 451 if (error != 0) { 452 DMAR_UNLOCK(unit); 453 dmar_release_resources(dev, unit); 454 dmar_devs[unit->iommu.unit] = NULL; 455 return (error); 456 } 457 } 458 459 DMAR_UNLOCK(unit); 460 error = dmar_init_fault_log(unit); 461 if (error != 0) { 462 dmar_release_resources(dev, unit); 463 dmar_devs[unit->iommu.unit] = NULL; 464 return (error); 465 } 466 error = dmar_init_qi(unit); 467 if (error != 0) { 468 dmar_release_resources(dev, unit); 469 dmar_devs[unit->iommu.unit] = NULL; 470 return (error); 471 } 472 error = dmar_init_irt(unit); 473 if (error != 0) { 474 dmar_release_resources(dev, unit); 475 dmar_devs[unit->iommu.unit] = NULL; 476 return (error); 477 } 478 479 disable_pmr = 0; 480 TUNABLE_INT_FETCH("hw.dmar.pmr.disable", &disable_pmr); 481 if (disable_pmr) { 482 error = dmar_disable_protected_regions(unit); 483 if (error != 0) 484 device_printf(dev, 485 "Failed to disable protected regions\n"); 486 } 487 488 error = iommu_init_busdma(&unit->iommu); 489 if (error != 0) { 490 dmar_release_resources(dev, unit); 491 dmar_devs[unit->iommu.unit] = NULL; 492 return (error); 493 } 494 495 #ifdef NOTYET 496 DMAR_LOCK(unit); 497 error = dmar_enable_translation(unit); 498 if (error != 0) { 499 DMAR_UNLOCK(unit); 500 dmar_release_resources(dev, unit); 501 dmar_devs[unit->iommu.unit] = NULL; 502 return (error); 503 } 504 DMAR_UNLOCK(unit); 505 #endif 506 507 return (0); 508 } 509 510 static int 511 dmar_detach(device_t dev) 512 { 513 514 return (EBUSY); 515 } 516 517 static int 518 dmar_suspend(device_t dev) 519 { 520 521 return (0); 522 } 523 524 static int 525 dmar_resume(device_t dev) 526 { 527 528 /* XXXKIB */ 529 return (0); 530 } 531 532 static device_method_t dmar_methods[] = { 533 DEVMETHOD(device_identify, dmar_identify), 534 DEVMETHOD(device_probe, dmar_probe), 535 DEVMETHOD(device_attach, dmar_attach), 536 DEVMETHOD(device_detach, dmar_detach), 537 DEVMETHOD(device_suspend, dmar_suspend), 538 DEVMETHOD(device_resume, dmar_resume), 539 #ifdef DEV_APIC 540 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 541 #endif 542 DEVMETHOD_END 543 }; 544 545 static driver_t dmar_driver = { 546 "dmar", 547 dmar_methods, 548 sizeof(struct dmar_unit), 549 }; 550 551 DRIVER_MODULE(dmar, acpi, dmar_driver, 0, 0); 552 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 553 554 static void 555 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 556 { 557 int i; 558 559 printf("[%d, ", busno); 560 for (i = 0; i < depth; i++) { 561 if (i != 0) 562 printf(", "); 563 printf("(%d, %d)", path[i].Device, path[i].Function); 564 } 565 printf("]"); 566 } 567 568 int 569 dmar_dev_depth(device_t child) 570 { 571 devclass_t pci_class; 572 device_t bus, pcib; 573 int depth; 574 575 pci_class = devclass_find("pci"); 576 for (depth = 1; ; depth++) { 577 bus = device_get_parent(child); 578 pcib = device_get_parent(bus); 579 if (device_get_devclass(device_get_parent(pcib)) != 580 pci_class) 581 return (depth); 582 child = pcib; 583 } 584 } 585 586 void 587 dmar_dev_path(device_t child, int *busno, void *path1, int depth) 588 { 589 devclass_t pci_class; 590 device_t bus, pcib; 591 ACPI_DMAR_PCI_PATH *path; 592 593 pci_class = devclass_find("pci"); 594 path = path1; 595 for (depth--; depth != -1; depth--) { 596 path[depth].Device = pci_get_slot(child); 597 path[depth].Function = pci_get_function(child); 598 bus = device_get_parent(child); 599 pcib = device_get_parent(bus); 600 if (device_get_devclass(device_get_parent(pcib)) != 601 pci_class) { 602 /* reached a host bridge */ 603 *busno = pcib_get_bus(bus); 604 return; 605 } 606 child = pcib; 607 } 608 panic("wrong depth"); 609 } 610 611 static int 612 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 613 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 614 enum AcpiDmarScopeType scope_type) 615 { 616 int i, depth; 617 618 if (busno1 != busno2) 619 return (0); 620 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 621 return (0); 622 depth = depth1; 623 if (depth2 < depth) 624 depth = depth2; 625 for (i = 0; i < depth; i++) { 626 if (path1[i].Device != path2[i].Device || 627 path1[i].Function != path2[i].Function) 628 return (0); 629 } 630 return (1); 631 } 632 633 static int 634 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 635 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 636 { 637 ACPI_DMAR_PCI_PATH *path; 638 int path_len; 639 640 if (devscope->Length < sizeof(*devscope)) { 641 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 642 devscope->Length); 643 return (-1); 644 } 645 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 646 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 647 return (0); 648 path_len = devscope->Length - sizeof(*devscope); 649 if (path_len % 2 != 0) { 650 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 651 devscope->Length); 652 return (-1); 653 } 654 path_len /= 2; 655 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 656 if (path_len == 0) { 657 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 658 devscope->Length); 659 return (-1); 660 } 661 662 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 663 dev_path, dev_path_len, devscope->EntryType)); 664 } 665 666 static bool 667 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 668 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 669 { 670 ACPI_DMAR_HARDWARE_UNIT *dmarh; 671 ACPI_DMAR_DEVICE_SCOPE *devscope; 672 char *ptr, *ptrend; 673 int match; 674 675 dmarh = dmar_find_by_index(unit->iommu.unit); 676 if (dmarh == NULL) 677 return (false); 678 if (dmarh->Segment != dev_domain) 679 return (false); 680 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 681 if (banner != NULL) 682 *banner = "INCLUDE_ALL"; 683 return (true); 684 } 685 ptr = (char *)dmarh + sizeof(*dmarh); 686 ptrend = (char *)dmarh + dmarh->Header.Length; 687 while (ptr < ptrend) { 688 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 689 ptr += devscope->Length; 690 match = dmar_match_devscope(devscope, dev_busno, dev_path, 691 dev_path_len); 692 if (match == -1) 693 return (false); 694 if (match == 1) { 695 if (banner != NULL) 696 *banner = "specific match"; 697 return (true); 698 } 699 } 700 return (false); 701 } 702 703 static struct dmar_unit * 704 dmar_find_by_scope(int dev_domain, int dev_busno, 705 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 706 { 707 struct dmar_unit *unit; 708 int i; 709 710 for (i = 0; i < dmar_devcnt; i++) { 711 if (dmar_devs[i] == NULL) 712 continue; 713 unit = device_get_softc(dmar_devs[i]); 714 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 715 dev_path_len, NULL)) 716 return (unit); 717 } 718 return (NULL); 719 } 720 721 struct dmar_unit * 722 dmar_find(device_t dev, bool verbose) 723 { 724 struct dmar_unit *unit; 725 const char *banner; 726 int i, dev_domain, dev_busno, dev_path_len; 727 728 /* 729 * This function can only handle PCI(e) devices. 730 */ 731 if (device_get_devclass(device_get_parent(dev)) != 732 devclass_find("pci")) 733 return (NULL); 734 735 dev_domain = pci_get_domain(dev); 736 dev_path_len = dmar_dev_depth(dev); 737 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 738 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 739 banner = ""; 740 741 for (i = 0; i < dmar_devcnt; i++) { 742 if (dmar_devs[i] == NULL) 743 continue; 744 unit = device_get_softc(dmar_devs[i]); 745 if (dmar_match_by_path(unit, dev_domain, dev_busno, 746 dev_path, dev_path_len, &banner)) 747 break; 748 } 749 if (i == dmar_devcnt) 750 return (NULL); 751 752 if (verbose) { 753 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 754 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 755 pci_get_function(dev), unit->iommu.unit, banner); 756 printf(" scope path "); 757 dmar_print_path(dev_busno, dev_path_len, dev_path); 758 printf("\n"); 759 } 760 iommu_device_set_iommu_prop(dev, unit->iommu.dev); 761 return (unit); 762 } 763 764 static struct dmar_unit * 765 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 766 { 767 device_t dmar_dev; 768 struct dmar_unit *unit; 769 ACPI_DMAR_HARDWARE_UNIT *dmarh; 770 ACPI_DMAR_DEVICE_SCOPE *devscope; 771 ACPI_DMAR_PCI_PATH *path; 772 char *ptr, *ptrend; 773 #ifdef DEV_APIC 774 int error; 775 #endif 776 int i; 777 778 for (i = 0; i < dmar_devcnt; i++) { 779 dmar_dev = dmar_devs[i]; 780 if (dmar_dev == NULL) 781 continue; 782 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 783 dmarh = dmar_find_by_index(i); 784 if (dmarh == NULL) 785 continue; 786 ptr = (char *)dmarh + sizeof(*dmarh); 787 ptrend = (char *)dmarh + dmarh->Header.Length; 788 for (;;) { 789 if (ptr >= ptrend) 790 break; 791 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 792 ptr += devscope->Length; 793 if (devscope->EntryType != entry_type) 794 continue; 795 if (devscope->EnumerationId != id) 796 continue; 797 #ifdef DEV_APIC 798 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 799 error = ioapic_get_rid(id, rid); 800 /* 801 * If our IOAPIC has PCI bindings then 802 * use the PCI device rid. 803 */ 804 if (error == 0) 805 return (unit); 806 } 807 #endif 808 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 809 == 2) { 810 if (rid != NULL) { 811 path = (ACPI_DMAR_PCI_PATH *) 812 (devscope + 1); 813 *rid = PCI_RID(devscope->Bus, 814 path->Device, path->Function); 815 } 816 return (unit); 817 } 818 printf( 819 "dmar_find_nonpci: id %d type %d path length != 2\n", 820 id, entry_type); 821 break; 822 } 823 } 824 return (NULL); 825 } 826 827 struct dmar_unit * 828 dmar_find_hpet(device_t dev, uint16_t *rid) 829 { 830 struct dmar_unit *unit; 831 832 unit = dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 833 rid); 834 if (unit != NULL) 835 iommu_device_set_iommu_prop(dev, unit->iommu.dev); 836 return (unit); 837 } 838 839 struct dmar_unit * 840 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 841 { 842 struct dmar_unit *unit; 843 device_t apic_dev; 844 845 unit = dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid); 846 if (unit != NULL) { 847 apic_dev = ioapic_get_dev(apic_id); 848 if (apic_dev != NULL) 849 iommu_device_set_iommu_prop(apic_dev, unit->iommu.dev); 850 } 851 return (unit); 852 } 853 854 struct rmrr_iter_args { 855 struct dmar_domain *domain; 856 int dev_domain; 857 int dev_busno; 858 const ACPI_DMAR_PCI_PATH *dev_path; 859 int dev_path_len; 860 struct iommu_map_entries_tailq *rmrr_entries; 861 }; 862 863 static int 864 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 865 { 866 struct rmrr_iter_args *ria; 867 ACPI_DMAR_RESERVED_MEMORY *resmem; 868 ACPI_DMAR_DEVICE_SCOPE *devscope; 869 struct iommu_map_entry *entry; 870 char *ptr, *ptrend; 871 int match; 872 873 if (!dmar_rmrr_enable) 874 return (1); 875 876 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 877 return (1); 878 879 ria = arg; 880 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 881 if (resmem->Segment != ria->dev_domain) 882 return (1); 883 884 ptr = (char *)resmem + sizeof(*resmem); 885 ptrend = (char *)resmem + resmem->Header.Length; 886 for (;;) { 887 if (ptr >= ptrend) 888 break; 889 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 890 ptr += devscope->Length; 891 match = dmar_match_devscope(devscope, ria->dev_busno, 892 ria->dev_path, ria->dev_path_len); 893 if (match == 1) { 894 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), 895 IOMMU_PGF_WAITOK); 896 entry->start = resmem->BaseAddress; 897 /* The RMRR entry end address is inclusive. */ 898 entry->end = resmem->EndAddress; 899 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 900 dmamap_link); 901 } 902 } 903 904 return (1); 905 } 906 907 void 908 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 909 const void *dev_path, int dev_path_len, 910 struct iommu_map_entries_tailq *rmrr_entries) 911 { 912 struct rmrr_iter_args ria; 913 914 ria.domain = domain; 915 ria.dev_domain = dev_domain; 916 ria.dev_busno = dev_busno; 917 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 918 ria.dev_path_len = dev_path_len; 919 ria.rmrr_entries = rmrr_entries; 920 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 921 } 922 923 struct inst_rmrr_iter_args { 924 struct dmar_unit *dmar; 925 }; 926 927 static device_t 928 dmar_path_dev(int segment, int path_len, int busno, 929 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 930 { 931 device_t dev; 932 int i; 933 934 dev = NULL; 935 for (i = 0; i < path_len; i++) { 936 dev = pci_find_dbsf(segment, busno, path->Device, 937 path->Function); 938 if (i != path_len - 1) { 939 busno = pci_cfgregread(segment, busno, path->Device, 940 path->Function, PCIR_SECBUS_1, 1); 941 path++; 942 } 943 } 944 *rid = PCI_RID(busno, path->Device, path->Function); 945 return (dev); 946 } 947 948 static int 949 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 950 { 951 const ACPI_DMAR_RESERVED_MEMORY *resmem; 952 const ACPI_DMAR_DEVICE_SCOPE *devscope; 953 struct inst_rmrr_iter_args *iria; 954 const char *ptr, *ptrend; 955 device_t dev; 956 struct dmar_unit *unit; 957 int dev_path_len; 958 uint16_t rid; 959 960 iria = arg; 961 962 if (!dmar_rmrr_enable) 963 return (1); 964 965 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 966 return (1); 967 968 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 969 if (resmem->Segment != iria->dmar->segment) 970 return (1); 971 972 ptr = (const char *)resmem + sizeof(*resmem); 973 ptrend = (const char *)resmem + resmem->Header.Length; 974 for (;;) { 975 if (ptr >= ptrend) 976 break; 977 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 978 ptr += devscope->Length; 979 /* XXXKIB bridge */ 980 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 981 continue; 982 rid = 0; 983 dev_path_len = (devscope->Length - 984 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 985 dev = dmar_path_dev(resmem->Segment, dev_path_len, 986 devscope->Bus, 987 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 988 if (dev == NULL) { 989 if (bootverbose) { 990 printf("dmar%d no dev found for RMRR " 991 "[%#jx, %#jx] rid %#x scope path ", 992 iria->dmar->iommu.unit, 993 (uintmax_t)resmem->BaseAddress, 994 (uintmax_t)resmem->EndAddress, 995 rid); 996 dmar_print_path(devscope->Bus, dev_path_len, 997 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 998 printf("\n"); 999 } 1000 unit = dmar_find_by_scope(resmem->Segment, 1001 devscope->Bus, 1002 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1003 dev_path_len); 1004 if (iria->dmar != unit) 1005 continue; 1006 dmar_get_ctx_for_devpath(iria->dmar, rid, 1007 resmem->Segment, devscope->Bus, 1008 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1009 dev_path_len, false, true); 1010 } else { 1011 unit = dmar_find(dev, false); 1012 if (iria->dmar != unit) 1013 continue; 1014 iommu_instantiate_ctx(&(iria)->dmar->iommu, 1015 dev, true); 1016 } 1017 } 1018 1019 return (1); 1020 1021 } 1022 1023 /* 1024 * Pre-create all contexts for the DMAR which have RMRR entries. 1025 */ 1026 int 1027 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) 1028 { 1029 struct dmar_unit *dmar; 1030 struct inst_rmrr_iter_args iria; 1031 int error; 1032 1033 dmar = IOMMU2DMAR(unit); 1034 1035 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1036 return (0); 1037 1038 error = 0; 1039 iria.dmar = dmar; 1040 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1041 DMAR_LOCK(dmar); 1042 if (!LIST_EMPTY(&dmar->domains)) { 1043 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1044 ("dmar%d: RMRR not handled but translation is already enabled", 1045 dmar->iommu.unit)); 1046 error = dmar_disable_protected_regions(dmar); 1047 if (error != 0) 1048 printf("dmar%d: Failed to disable protected regions\n", 1049 dmar->iommu.unit); 1050 error = dmar_enable_translation(dmar); 1051 if (bootverbose) { 1052 if (error == 0) { 1053 printf("dmar%d: enabled translation\n", 1054 dmar->iommu.unit); 1055 } else { 1056 printf("dmar%d: enabling translation failed, " 1057 "error %d\n", dmar->iommu.unit, error); 1058 } 1059 } 1060 } 1061 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1062 return (error); 1063 } 1064 1065 #ifdef DDB 1066 #include <ddb/ddb.h> 1067 #include <ddb/db_lex.h> 1068 1069 static void 1070 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1071 { 1072 struct iommu_domain *iodom; 1073 1074 iodom = DOM2IODOM(domain); 1075 1076 db_printf( 1077 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1078 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1079 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1080 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt, 1081 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt); 1082 1083 iommu_db_domain_print_contexts(iodom); 1084 1085 if (show_mappings) 1086 iommu_db_domain_print_mappings(iodom); 1087 } 1088 1089 DB_SHOW_COMMAND_FLAGS(dmar_domain, db_dmar_print_domain, CS_OWN) 1090 { 1091 struct dmar_unit *unit; 1092 struct dmar_domain *domain; 1093 struct iommu_ctx *ctx; 1094 bool show_mappings, valid; 1095 int pci_domain, bus, device, function, i, t; 1096 db_expr_t radix; 1097 1098 valid = false; 1099 radix = db_radix; 1100 db_radix = 10; 1101 t = db_read_token(); 1102 if (t == tSLASH) { 1103 t = db_read_token(); 1104 if (t != tIDENT) { 1105 db_printf("Bad modifier\n"); 1106 db_radix = radix; 1107 db_skip_to_eol(); 1108 return; 1109 } 1110 show_mappings = strchr(db_tok_string, 'm') != NULL; 1111 t = db_read_token(); 1112 } else { 1113 show_mappings = false; 1114 } 1115 if (t == tNUMBER) { 1116 pci_domain = db_tok_number; 1117 t = db_read_token(); 1118 if (t == tNUMBER) { 1119 bus = db_tok_number; 1120 t = db_read_token(); 1121 if (t == tNUMBER) { 1122 device = db_tok_number; 1123 t = db_read_token(); 1124 if (t == tNUMBER) { 1125 function = db_tok_number; 1126 valid = true; 1127 } 1128 } 1129 } 1130 } 1131 db_radix = radix; 1132 db_skip_to_eol(); 1133 if (!valid) { 1134 db_printf("usage: show dmar_domain [/m] " 1135 "<domain> <bus> <device> <func>\n"); 1136 return; 1137 } 1138 for (i = 0; i < dmar_devcnt; i++) { 1139 unit = device_get_softc(dmar_devs[i]); 1140 LIST_FOREACH(domain, &unit->domains, link) { 1141 LIST_FOREACH(ctx, &domain->iodom.contexts, link) { 1142 if (pci_domain == unit->segment && 1143 bus == pci_get_bus(ctx->tag->owner) && 1144 device == pci_get_slot(ctx->tag->owner) && 1145 function == pci_get_function(ctx->tag-> 1146 owner)) { 1147 dmar_print_domain(domain, 1148 show_mappings); 1149 goto out; 1150 } 1151 } 1152 } 1153 } 1154 out:; 1155 } 1156 1157 static void 1158 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1159 { 1160 struct dmar_unit *unit; 1161 struct dmar_domain *domain; 1162 int i, frir; 1163 1164 unit = device_get_softc(dmar_devs[idx]); 1165 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, 1166 unit, dmar_read8(unit, DMAR_RTADDR_REG), 1167 dmar_read4(unit, DMAR_VER_REG)); 1168 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1169 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1170 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1171 dmar_read4(unit, DMAR_GSTS_REG), 1172 dmar_read4(unit, DMAR_FSTS_REG), 1173 dmar_read4(unit, DMAR_FECTL_REG)); 1174 if (unit->ir_enabled) { 1175 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1176 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1177 } 1178 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1179 dmar_read4(unit, DMAR_FEDATA_REG), 1180 dmar_read4(unit, DMAR_FEADDR_REG), 1181 dmar_read4(unit, DMAR_FEUADDR_REG)); 1182 db_printf("primary fault log:\n"); 1183 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1184 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1185 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1186 (uintmax_t)dmar_read8(unit, frir), 1187 (uintmax_t)dmar_read8(unit, frir + 8)); 1188 } 1189 if (DMAR_HAS_QI(unit)) { 1190 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1191 dmar_read4(unit, DMAR_IEDATA_REG), 1192 dmar_read4(unit, DMAR_IEADDR_REG), 1193 dmar_read4(unit, DMAR_IEUADDR_REG)); 1194 if (unit->qi_enabled) { 1195 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1196 "size 0x%jx\n" 1197 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1198 " hw compl 0x%jx@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1199 (uintmax_t)unit->x86c.inv_queue, 1200 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1201 (uintmax_t)unit->x86c.inv_queue_size, 1202 dmar_read4(unit, DMAR_IQH_REG), 1203 dmar_read4(unit, DMAR_IQT_REG), 1204 unit->x86c.inv_queue_avail, 1205 dmar_read4(unit, DMAR_ICS_REG), 1206 dmar_read4(unit, DMAR_IECTL_REG), 1207 (uintmax_t)unit->x86c.inv_waitd_seq_hw, 1208 &unit->x86c.inv_waitd_seq_hw, 1209 (uintmax_t)unit->x86c.inv_waitd_seq_hw_phys, 1210 unit->x86c.inv_waitd_seq, 1211 unit->x86c.inv_waitd_gen); 1212 } else { 1213 db_printf("qi is disabled\n"); 1214 } 1215 } 1216 if (show_domains) { 1217 db_printf("domains:\n"); 1218 LIST_FOREACH(domain, &unit->domains, link) { 1219 dmar_print_domain(domain, show_mappings); 1220 if (db_pager_quit) 1221 break; 1222 } 1223 } 1224 } 1225 1226 DB_SHOW_COMMAND(dmar, db_dmar_print) 1227 { 1228 bool show_domains, show_mappings; 1229 1230 show_domains = strchr(modif, 'd') != NULL; 1231 show_mappings = strchr(modif, 'm') != NULL; 1232 if (!have_addr) { 1233 db_printf("usage: show dmar [/d] [/m] index\n"); 1234 return; 1235 } 1236 dmar_print_one((int)addr, show_domains, show_mappings); 1237 } 1238 1239 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1240 { 1241 int i; 1242 bool show_domains, show_mappings; 1243 1244 show_domains = strchr(modif, 'd') != NULL; 1245 show_mappings = strchr(modif, 'm') != NULL; 1246 1247 for (i = 0; i < dmar_devcnt; i++) { 1248 dmar_print_one(i, show_domains, show_mappings); 1249 if (db_pager_quit) 1250 break; 1251 } 1252 } 1253 #endif 1254 1255 static struct iommu_unit * 1256 dmar_find_method(device_t dev, bool verbose) 1257 { 1258 struct dmar_unit *dmar; 1259 1260 dmar = dmar_find(dev, verbose); 1261 return (&dmar->iommu); 1262 } 1263 1264 static struct x86_unit_common * 1265 dmar_get_x86_common(struct iommu_unit *unit) 1266 { 1267 struct dmar_unit *dmar; 1268 1269 dmar = IOMMU2DMAR(unit); 1270 return (&dmar->x86c); 1271 } 1272 1273 static void 1274 dmar_unit_pre_instantiate_ctx(struct iommu_unit *unit) 1275 { 1276 dmar_quirks_pre_use(unit); 1277 dmar_instantiate_rmrr_ctxs(unit); 1278 } 1279 1280 static struct x86_iommu dmar_x86_iommu = { 1281 .get_x86_common = dmar_get_x86_common, 1282 .unit_pre_instantiate_ctx = dmar_unit_pre_instantiate_ctx, 1283 .domain_unload_entry = dmar_domain_unload_entry, 1284 .domain_unload = dmar_domain_unload, 1285 .get_ctx = dmar_get_ctx, 1286 .free_ctx_locked = dmar_free_ctx_locked_method, 1287 .free_ctx = dmar_free_ctx_method, 1288 .find = dmar_find_method, 1289 .alloc_msi_intr = dmar_alloc_msi_intr, 1290 .map_msi_intr = dmar_map_msi_intr, 1291 .unmap_msi_intr = dmar_unmap_msi_intr, 1292 .map_ioapic_intr = dmar_map_ioapic_intr, 1293 .unmap_ioapic_intr = dmar_unmap_ioapic_intr, 1294 }; 1295 1296 static void 1297 x86_iommu_set_intel(void *arg __unused) 1298 { 1299 if (cpu_vendor_id == CPU_VENDOR_INTEL) 1300 set_x86_iommu(&dmar_x86_iommu); 1301 } 1302 1303 SYSINIT(x86_iommu, SI_SUB_TUNABLES, SI_ORDER_ANY, x86_iommu_set_intel, NULL); 1304