1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "opt_acpi.h" 32 #if defined(__amd64__) 33 #define DEV_APIC 34 #else 35 #include "opt_apic.h" 36 #endif 37 #include "opt_ddb.h" 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/memdesc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/rman.h> 48 #include <sys/rwlock.h> 49 #include <sys/smp.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 #include <sys/vmem.h> 53 #include <vm/vm.h> 54 #include <vm/vm_extern.h> 55 #include <vm/vm_kern.h> 56 #include <vm/vm_object.h> 57 #include <vm/vm_page.h> 58 #include <vm/vm_pager.h> 59 #include <vm/vm_map.h> 60 #include <contrib/dev/acpica/include/acpi.h> 61 #include <contrib/dev/acpica/include/accommon.h> 62 #include <dev/acpica/acpivar.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <machine/bus.h> 66 #include <machine/pci_cfgreg.h> 67 #include <x86/include/busdma_impl.h> 68 #include <dev/iommu/busdma_iommu.h> 69 #include <x86/iommu/intel_reg.h> 70 #include <x86/iommu/x86_iommu.h> 71 #include <x86/iommu/intel_dmar.h> 72 73 #ifdef DEV_APIC 74 #include "pcib_if.h" 75 #include <machine/intr_machdep.h> 76 #include <x86/apicreg.h> 77 #include <x86/apicvar.h> 78 #endif 79 80 #define DMAR_FAULT_IRQ_RID 0 81 #define DMAR_QI_IRQ_RID 1 82 #define DMAR_REG_RID 2 83 84 static device_t *dmar_devs; 85 static int dmar_devcnt; 86 87 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 88 89 static void 90 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 91 { 92 ACPI_TABLE_DMAR *dmartbl; 93 ACPI_DMAR_HEADER *dmarh; 94 char *ptr, *ptrend; 95 ACPI_STATUS status; 96 97 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 98 if (ACPI_FAILURE(status)) 99 return; 100 ptr = (char *)dmartbl + sizeof(*dmartbl); 101 ptrend = (char *)dmartbl + dmartbl->Header.Length; 102 for (;;) { 103 if (ptr >= ptrend) 104 break; 105 dmarh = (ACPI_DMAR_HEADER *)ptr; 106 if (dmarh->Length <= 0) { 107 printf("dmar_identify: corrupted DMAR table, l %d\n", 108 dmarh->Length); 109 break; 110 } 111 ptr += dmarh->Length; 112 if (!iter(dmarh, arg)) 113 break; 114 } 115 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 116 } 117 118 struct find_iter_args { 119 int i; 120 ACPI_DMAR_HARDWARE_UNIT *res; 121 }; 122 123 static int 124 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 125 { 126 struct find_iter_args *fia; 127 128 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 129 return (1); 130 131 fia = arg; 132 if (fia->i == 0) { 133 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 134 return (0); 135 } 136 fia->i--; 137 return (1); 138 } 139 140 static ACPI_DMAR_HARDWARE_UNIT * 141 dmar_find_by_index(int idx) 142 { 143 struct find_iter_args fia; 144 145 fia.i = idx; 146 fia.res = NULL; 147 dmar_iterate_tbl(dmar_find_iter, &fia); 148 return (fia.res); 149 } 150 151 static int 152 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 153 { 154 155 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 156 dmar_devcnt++; 157 return (1); 158 } 159 160 int dmar_rmrr_enable = 1; 161 162 static int dmar_enable = 1; 163 164 static void 165 dmar_identify(driver_t *driver, device_t parent) 166 { 167 ACPI_TABLE_DMAR *dmartbl; 168 ACPI_DMAR_HARDWARE_UNIT *dmarh; 169 ACPI_STATUS status; 170 int i, error; 171 172 if (acpi_disabled("dmar")) 173 return; 174 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 175 if (!dmar_enable) 176 return; 177 TUNABLE_INT_FETCH("hw.dmar.rmrr_enable", &dmar_rmrr_enable); 178 179 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 180 if (ACPI_FAILURE(status)) 181 return; 182 haw = dmartbl->Width + 1; 183 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 184 iommu_high = BUS_SPACE_MAXADDR; 185 else 186 iommu_high = 1ULL << (haw + 1); 187 if (bootverbose) { 188 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 189 (unsigned)dmartbl->Flags, 190 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 191 } 192 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 193 194 dmar_iterate_tbl(dmar_count_iter, NULL); 195 if (dmar_devcnt == 0) 196 return; 197 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 198 M_WAITOK | M_ZERO); 199 for (i = 0; i < dmar_devcnt; i++) { 200 dmarh = dmar_find_by_index(i); 201 if (dmarh == NULL) { 202 printf("dmar_identify: cannot find HWUNIT %d\n", i); 203 continue; 204 } 205 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 206 if (dmar_devs[i] == NULL) { 207 printf("dmar_identify: cannot create instance %d\n", i); 208 continue; 209 } 210 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 211 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 212 if (error != 0) { 213 printf( 214 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 215 i, (uintmax_t)dmarh->Address, error); 216 device_delete_child(parent, dmar_devs[i]); 217 dmar_devs[i] = NULL; 218 } 219 } 220 } 221 222 static int 223 dmar_probe(device_t dev) 224 { 225 226 if (acpi_get_handle(dev) != NULL) 227 return (ENXIO); 228 device_set_desc(dev, "DMA remap"); 229 return (BUS_PROBE_NOWILDCARD); 230 } 231 232 static void 233 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx) 234 { 235 struct dmar_msi_data *dmd; 236 237 dmd = &unit->intrs[idx]; 238 if (dmd->irq == -1) 239 return; 240 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 241 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 242 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 243 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)), 244 dev, dmd->irq); 245 dmd->irq = -1; 246 } 247 248 static void 249 dmar_release_resources(device_t dev, struct dmar_unit *unit) 250 { 251 int i; 252 253 iommu_fini_busdma(&unit->iommu); 254 dmar_fini_irt(unit); 255 dmar_fini_qi(unit); 256 dmar_fini_fault_log(unit); 257 for (i = 0; i < DMAR_INTR_TOTAL; i++) 258 dmar_release_intr(dev, unit, i); 259 if (unit->regs != NULL) { 260 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 261 unit->regs); 262 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 263 unit->regs); 264 unit->regs = NULL; 265 } 266 if (unit->domids != NULL) { 267 delete_unrhdr(unit->domids); 268 unit->domids = NULL; 269 } 270 if (unit->ctx_obj != NULL) { 271 vm_object_deallocate(unit->ctx_obj); 272 unit->ctx_obj = NULL; 273 } 274 } 275 276 static int 277 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx) 278 { 279 device_t pcib; 280 struct dmar_msi_data *dmd; 281 uint64_t msi_addr; 282 uint32_t msi_data; 283 int error; 284 285 dmd = &unit->intrs[idx]; 286 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */ 287 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq); 288 if (error != 0) { 289 device_printf(dev, "cannot allocate %s interrupt, %d\n", 290 dmd->name, error); 291 goto err1; 292 } 293 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid, 294 dmd->irq, 1); 295 if (error != 0) { 296 device_printf(dev, "cannot set %s interrupt resource, %d\n", 297 dmd->name, error); 298 goto err2; 299 } 300 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 301 &dmd->irq_rid, RF_ACTIVE); 302 if (dmd->irq_res == NULL) { 303 device_printf(dev, 304 "cannot allocate resource for %s interrupt\n", dmd->name); 305 error = ENXIO; 306 goto err3; 307 } 308 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC, 309 dmd->handler, NULL, unit, &dmd->intr_handle); 310 if (error != 0) { 311 device_printf(dev, "cannot setup %s interrupt, %d\n", 312 dmd->name, error); 313 goto err4; 314 } 315 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name); 316 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data); 317 if (error != 0) { 318 device_printf(dev, "cannot map %s interrupt, %d\n", 319 dmd->name, error); 320 goto err5; 321 } 322 dmar_write4(unit, dmd->msi_data_reg, msi_data); 323 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 324 /* Only for xAPIC mode */ 325 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 326 return (0); 327 328 err5: 329 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 330 err4: 331 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 332 err3: 333 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 334 err2: 335 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq); 336 dmd->irq = -1; 337 err1: 338 return (error); 339 } 340 341 #ifdef DEV_APIC 342 static int 343 dmar_remap_intr(device_t dev, device_t child, u_int irq) 344 { 345 struct dmar_unit *unit; 346 struct dmar_msi_data *dmd; 347 uint64_t msi_addr; 348 uint32_t msi_data; 349 int i, error; 350 351 unit = device_get_softc(dev); 352 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 353 dmd = &unit->intrs[i]; 354 if (irq == dmd->irq) { 355 error = PCIB_MAP_MSI(device_get_parent( 356 device_get_parent(dev)), 357 dev, irq, &msi_addr, &msi_data); 358 if (error != 0) 359 return (error); 360 DMAR_LOCK(unit); 361 (dmd->disable_intr)(unit); 362 dmar_write4(unit, dmd->msi_data_reg, msi_data); 363 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 364 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 365 (dmd->enable_intr)(unit); 366 DMAR_UNLOCK(unit); 367 return (0); 368 } 369 } 370 return (ENOENT); 371 } 372 #endif 373 374 static void 375 dmar_print_caps(device_t dev, struct dmar_unit *unit, 376 ACPI_DMAR_HARDWARE_UNIT *dmaru) 377 { 378 uint32_t caphi, ecaphi; 379 380 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 381 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 382 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 383 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 384 caphi = unit->hw_cap >> 32; 385 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 386 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 387 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 388 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 389 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 390 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 391 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 392 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 393 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 394 printf("\n"); 395 ecaphi = unit->hw_ecap >> 32; 396 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 397 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 398 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 399 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 400 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 401 DMAR_ECAP_IRO(unit->hw_ecap)); 402 } 403 404 static int 405 dmar_attach(device_t dev) 406 { 407 struct dmar_unit *unit; 408 ACPI_DMAR_HARDWARE_UNIT *dmaru; 409 uint64_t timeout; 410 int disable_pmr; 411 int i, error; 412 413 unit = device_get_softc(dev); 414 unit->iommu.unit = device_get_unit(dev); 415 unit->iommu.dev = dev; 416 dmaru = dmar_find_by_index(unit->iommu.unit); 417 if (dmaru == NULL) 418 return (EINVAL); 419 unit->segment = dmaru->Segment; 420 unit->base = dmaru->Address; 421 unit->reg_rid = DMAR_REG_RID; 422 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 423 &unit->reg_rid, RF_ACTIVE); 424 if (unit->regs == NULL) { 425 device_printf(dev, "cannot allocate register window\n"); 426 return (ENOMEM); 427 } 428 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 429 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 430 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 431 if (bootverbose) 432 dmar_print_caps(dev, unit, dmaru); 433 dmar_quirks_post_ident(unit); 434 435 timeout = dmar_get_timeout(); 436 TUNABLE_UINT64_FETCH("hw.iommu.dmar.timeout", &timeout); 437 dmar_update_timeout(timeout); 438 439 for (i = 0; i < DMAR_INTR_TOTAL; i++) 440 unit->intrs[i].irq = -1; 441 442 unit->intrs[DMAR_INTR_FAULT].name = "fault"; 443 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; 444 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; 445 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; 446 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; 447 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; 448 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr; 449 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr; 450 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT); 451 if (error != 0) { 452 dmar_release_resources(dev, unit); 453 return (error); 454 } 455 if (DMAR_HAS_QI(unit)) { 456 unit->intrs[DMAR_INTR_QI].name = "qi"; 457 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID; 458 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr; 459 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG; 460 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG; 461 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG; 462 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr; 463 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr; 464 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI); 465 if (error != 0) { 466 dmar_release_resources(dev, unit); 467 return (error); 468 } 469 } 470 471 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); 472 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 473 &unit->iommu.lock); 474 LIST_INIT(&unit->domains); 475 476 /* 477 * 9.2 "Context Entry": 478 * When Caching Mode (CM) field is reported as Set, the 479 * domain-id value of zero is architecturally reserved. 480 * Software must not use domain-id value of zero 481 * when CM is Set. 482 */ 483 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 484 alloc_unr_specific(unit->domids, 0); 485 486 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 487 DMAR_CTX_CNT), 0, 0, NULL); 488 489 /* 490 * Allocate and load the root entry table pointer. Enable the 491 * address translation after the required invalidations are 492 * done. 493 */ 494 iommu_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); 495 DMAR_LOCK(unit); 496 error = dmar_load_root_entry_ptr(unit); 497 if (error != 0) { 498 DMAR_UNLOCK(unit); 499 dmar_release_resources(dev, unit); 500 return (error); 501 } 502 error = dmar_inv_ctx_glob(unit); 503 if (error != 0) { 504 DMAR_UNLOCK(unit); 505 dmar_release_resources(dev, unit); 506 return (error); 507 } 508 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 509 error = dmar_inv_iotlb_glob(unit); 510 if (error != 0) { 511 DMAR_UNLOCK(unit); 512 dmar_release_resources(dev, unit); 513 return (error); 514 } 515 } 516 517 DMAR_UNLOCK(unit); 518 error = dmar_init_fault_log(unit); 519 if (error != 0) { 520 dmar_release_resources(dev, unit); 521 return (error); 522 } 523 error = dmar_init_qi(unit); 524 if (error != 0) { 525 dmar_release_resources(dev, unit); 526 return (error); 527 } 528 error = dmar_init_irt(unit); 529 if (error != 0) { 530 dmar_release_resources(dev, unit); 531 return (error); 532 } 533 534 disable_pmr = 0; 535 TUNABLE_INT_FETCH("hw.dmar.pmr.disable", &disable_pmr); 536 if (disable_pmr) { 537 error = dmar_disable_protected_regions(unit); 538 if (error != 0) 539 device_printf(dev, 540 "Failed to disable protected regions\n"); 541 } 542 543 error = iommu_init_busdma(&unit->iommu); 544 if (error != 0) { 545 dmar_release_resources(dev, unit); 546 return (error); 547 } 548 549 #ifdef NOTYET 550 DMAR_LOCK(unit); 551 error = dmar_enable_translation(unit); 552 if (error != 0) { 553 DMAR_UNLOCK(unit); 554 dmar_release_resources(dev, unit); 555 return (error); 556 } 557 DMAR_UNLOCK(unit); 558 #endif 559 560 return (0); 561 } 562 563 static int 564 dmar_detach(device_t dev) 565 { 566 567 return (EBUSY); 568 } 569 570 static int 571 dmar_suspend(device_t dev) 572 { 573 574 return (0); 575 } 576 577 static int 578 dmar_resume(device_t dev) 579 { 580 581 /* XXXKIB */ 582 return (0); 583 } 584 585 static device_method_t dmar_methods[] = { 586 DEVMETHOD(device_identify, dmar_identify), 587 DEVMETHOD(device_probe, dmar_probe), 588 DEVMETHOD(device_attach, dmar_attach), 589 DEVMETHOD(device_detach, dmar_detach), 590 DEVMETHOD(device_suspend, dmar_suspend), 591 DEVMETHOD(device_resume, dmar_resume), 592 #ifdef DEV_APIC 593 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 594 #endif 595 DEVMETHOD_END 596 }; 597 598 static driver_t dmar_driver = { 599 "dmar", 600 dmar_methods, 601 sizeof(struct dmar_unit), 602 }; 603 604 DRIVER_MODULE(dmar, acpi, dmar_driver, 0, 0); 605 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 606 607 static void 608 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 609 { 610 int i; 611 612 printf("[%d, ", busno); 613 for (i = 0; i < depth; i++) { 614 if (i != 0) 615 printf(", "); 616 printf("(%d, %d)", path[i].Device, path[i].Function); 617 } 618 printf("]"); 619 } 620 621 int 622 dmar_dev_depth(device_t child) 623 { 624 devclass_t pci_class; 625 device_t bus, pcib; 626 int depth; 627 628 pci_class = devclass_find("pci"); 629 for (depth = 1; ; depth++) { 630 bus = device_get_parent(child); 631 pcib = device_get_parent(bus); 632 if (device_get_devclass(device_get_parent(pcib)) != 633 pci_class) 634 return (depth); 635 child = pcib; 636 } 637 } 638 639 void 640 dmar_dev_path(device_t child, int *busno, void *path1, int depth) 641 { 642 devclass_t pci_class; 643 device_t bus, pcib; 644 ACPI_DMAR_PCI_PATH *path; 645 646 pci_class = devclass_find("pci"); 647 path = path1; 648 for (depth--; depth != -1; depth--) { 649 path[depth].Device = pci_get_slot(child); 650 path[depth].Function = pci_get_function(child); 651 bus = device_get_parent(child); 652 pcib = device_get_parent(bus); 653 if (device_get_devclass(device_get_parent(pcib)) != 654 pci_class) { 655 /* reached a host bridge */ 656 *busno = pcib_get_bus(bus); 657 return; 658 } 659 child = pcib; 660 } 661 panic("wrong depth"); 662 } 663 664 static int 665 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 666 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 667 enum AcpiDmarScopeType scope_type) 668 { 669 int i, depth; 670 671 if (busno1 != busno2) 672 return (0); 673 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 674 return (0); 675 depth = depth1; 676 if (depth2 < depth) 677 depth = depth2; 678 for (i = 0; i < depth; i++) { 679 if (path1[i].Device != path2[i].Device || 680 path1[i].Function != path2[i].Function) 681 return (0); 682 } 683 return (1); 684 } 685 686 static int 687 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 688 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 689 { 690 ACPI_DMAR_PCI_PATH *path; 691 int path_len; 692 693 if (devscope->Length < sizeof(*devscope)) { 694 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 695 devscope->Length); 696 return (-1); 697 } 698 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 699 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 700 return (0); 701 path_len = devscope->Length - sizeof(*devscope); 702 if (path_len % 2 != 0) { 703 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 704 devscope->Length); 705 return (-1); 706 } 707 path_len /= 2; 708 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 709 if (path_len == 0) { 710 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 711 devscope->Length); 712 return (-1); 713 } 714 715 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 716 dev_path, dev_path_len, devscope->EntryType)); 717 } 718 719 static bool 720 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 721 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 722 { 723 ACPI_DMAR_HARDWARE_UNIT *dmarh; 724 ACPI_DMAR_DEVICE_SCOPE *devscope; 725 char *ptr, *ptrend; 726 int match; 727 728 dmarh = dmar_find_by_index(unit->iommu.unit); 729 if (dmarh == NULL) 730 return (false); 731 if (dmarh->Segment != dev_domain) 732 return (false); 733 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 734 if (banner != NULL) 735 *banner = "INCLUDE_ALL"; 736 return (true); 737 } 738 ptr = (char *)dmarh + sizeof(*dmarh); 739 ptrend = (char *)dmarh + dmarh->Header.Length; 740 while (ptr < ptrend) { 741 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 742 ptr += devscope->Length; 743 match = dmar_match_devscope(devscope, dev_busno, dev_path, 744 dev_path_len); 745 if (match == -1) 746 return (false); 747 if (match == 1) { 748 if (banner != NULL) 749 *banner = "specific match"; 750 return (true); 751 } 752 } 753 return (false); 754 } 755 756 static struct dmar_unit * 757 dmar_find_by_scope(int dev_domain, int dev_busno, 758 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 759 { 760 struct dmar_unit *unit; 761 int i; 762 763 for (i = 0; i < dmar_devcnt; i++) { 764 if (dmar_devs[i] == NULL) 765 continue; 766 unit = device_get_softc(dmar_devs[i]); 767 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 768 dev_path_len, NULL)) 769 return (unit); 770 } 771 return (NULL); 772 } 773 774 struct dmar_unit * 775 dmar_find(device_t dev, bool verbose) 776 { 777 struct dmar_unit *unit; 778 const char *banner; 779 int i, dev_domain, dev_busno, dev_path_len; 780 781 /* 782 * This function can only handle PCI(e) devices. 783 */ 784 if (device_get_devclass(device_get_parent(dev)) != 785 devclass_find("pci")) 786 return (NULL); 787 788 dev_domain = pci_get_domain(dev); 789 dev_path_len = dmar_dev_depth(dev); 790 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 791 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 792 banner = ""; 793 794 for (i = 0; i < dmar_devcnt; i++) { 795 if (dmar_devs[i] == NULL) 796 continue; 797 unit = device_get_softc(dmar_devs[i]); 798 if (dmar_match_by_path(unit, dev_domain, dev_busno, 799 dev_path, dev_path_len, &banner)) 800 break; 801 } 802 if (i == dmar_devcnt) 803 return (NULL); 804 805 if (verbose) { 806 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 807 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 808 pci_get_function(dev), unit->iommu.unit, banner); 809 printf(" scope path "); 810 dmar_print_path(dev_busno, dev_path_len, dev_path); 811 printf("\n"); 812 } 813 return (unit); 814 } 815 816 static struct dmar_unit * 817 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 818 { 819 device_t dmar_dev; 820 struct dmar_unit *unit; 821 ACPI_DMAR_HARDWARE_UNIT *dmarh; 822 ACPI_DMAR_DEVICE_SCOPE *devscope; 823 ACPI_DMAR_PCI_PATH *path; 824 char *ptr, *ptrend; 825 #ifdef DEV_APIC 826 int error; 827 #endif 828 int i; 829 830 for (i = 0; i < dmar_devcnt; i++) { 831 dmar_dev = dmar_devs[i]; 832 if (dmar_dev == NULL) 833 continue; 834 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 835 dmarh = dmar_find_by_index(i); 836 if (dmarh == NULL) 837 continue; 838 ptr = (char *)dmarh + sizeof(*dmarh); 839 ptrend = (char *)dmarh + dmarh->Header.Length; 840 for (;;) { 841 if (ptr >= ptrend) 842 break; 843 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 844 ptr += devscope->Length; 845 if (devscope->EntryType != entry_type) 846 continue; 847 if (devscope->EnumerationId != id) 848 continue; 849 #ifdef DEV_APIC 850 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 851 error = ioapic_get_rid(id, rid); 852 /* 853 * If our IOAPIC has PCI bindings then 854 * use the PCI device rid. 855 */ 856 if (error == 0) 857 return (unit); 858 } 859 #endif 860 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 861 == 2) { 862 if (rid != NULL) { 863 path = (ACPI_DMAR_PCI_PATH *) 864 (devscope + 1); 865 *rid = PCI_RID(devscope->Bus, 866 path->Device, path->Function); 867 } 868 return (unit); 869 } 870 printf( 871 "dmar_find_nonpci: id %d type %d path length != 2\n", 872 id, entry_type); 873 break; 874 } 875 } 876 return (NULL); 877 } 878 879 struct dmar_unit * 880 dmar_find_hpet(device_t dev, uint16_t *rid) 881 { 882 883 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 884 rid)); 885 } 886 887 struct dmar_unit * 888 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 889 { 890 891 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 892 } 893 894 struct rmrr_iter_args { 895 struct dmar_domain *domain; 896 int dev_domain; 897 int dev_busno; 898 const ACPI_DMAR_PCI_PATH *dev_path; 899 int dev_path_len; 900 struct iommu_map_entries_tailq *rmrr_entries; 901 }; 902 903 static int 904 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 905 { 906 struct rmrr_iter_args *ria; 907 ACPI_DMAR_RESERVED_MEMORY *resmem; 908 ACPI_DMAR_DEVICE_SCOPE *devscope; 909 struct iommu_map_entry *entry; 910 char *ptr, *ptrend; 911 int match; 912 913 if (!dmar_rmrr_enable) 914 return (1); 915 916 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 917 return (1); 918 919 ria = arg; 920 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 921 if (resmem->Segment != ria->dev_domain) 922 return (1); 923 924 ptr = (char *)resmem + sizeof(*resmem); 925 ptrend = (char *)resmem + resmem->Header.Length; 926 for (;;) { 927 if (ptr >= ptrend) 928 break; 929 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 930 ptr += devscope->Length; 931 match = dmar_match_devscope(devscope, ria->dev_busno, 932 ria->dev_path, ria->dev_path_len); 933 if (match == 1) { 934 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), 935 IOMMU_PGF_WAITOK); 936 entry->start = resmem->BaseAddress; 937 /* The RMRR entry end address is inclusive. */ 938 entry->end = resmem->EndAddress; 939 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 940 dmamap_link); 941 } 942 } 943 944 return (1); 945 } 946 947 void 948 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 949 const void *dev_path, int dev_path_len, 950 struct iommu_map_entries_tailq *rmrr_entries) 951 { 952 struct rmrr_iter_args ria; 953 954 ria.domain = domain; 955 ria.dev_domain = dev_domain; 956 ria.dev_busno = dev_busno; 957 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 958 ria.dev_path_len = dev_path_len; 959 ria.rmrr_entries = rmrr_entries; 960 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 961 } 962 963 struct inst_rmrr_iter_args { 964 struct dmar_unit *dmar; 965 }; 966 967 static device_t 968 dmar_path_dev(int segment, int path_len, int busno, 969 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 970 { 971 device_t dev; 972 int i; 973 974 dev = NULL; 975 for (i = 0; i < path_len; i++) { 976 dev = pci_find_dbsf(segment, busno, path->Device, 977 path->Function); 978 if (i != path_len - 1) { 979 busno = pci_cfgregread(segment, busno, path->Device, 980 path->Function, PCIR_SECBUS_1, 1); 981 path++; 982 } 983 } 984 *rid = PCI_RID(busno, path->Device, path->Function); 985 return (dev); 986 } 987 988 static int 989 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 990 { 991 const ACPI_DMAR_RESERVED_MEMORY *resmem; 992 const ACPI_DMAR_DEVICE_SCOPE *devscope; 993 struct inst_rmrr_iter_args *iria; 994 const char *ptr, *ptrend; 995 device_t dev; 996 struct dmar_unit *unit; 997 int dev_path_len; 998 uint16_t rid; 999 1000 iria = arg; 1001 1002 if (!dmar_rmrr_enable) 1003 return (1); 1004 1005 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 1006 return (1); 1007 1008 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 1009 if (resmem->Segment != iria->dmar->segment) 1010 return (1); 1011 1012 ptr = (const char *)resmem + sizeof(*resmem); 1013 ptrend = (const char *)resmem + resmem->Header.Length; 1014 for (;;) { 1015 if (ptr >= ptrend) 1016 break; 1017 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 1018 ptr += devscope->Length; 1019 /* XXXKIB bridge */ 1020 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 1021 continue; 1022 rid = 0; 1023 dev_path_len = (devscope->Length - 1024 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 1025 dev = dmar_path_dev(resmem->Segment, dev_path_len, 1026 devscope->Bus, 1027 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 1028 if (dev == NULL) { 1029 if (bootverbose) { 1030 printf("dmar%d no dev found for RMRR " 1031 "[%#jx, %#jx] rid %#x scope path ", 1032 iria->dmar->iommu.unit, 1033 (uintmax_t)resmem->BaseAddress, 1034 (uintmax_t)resmem->EndAddress, 1035 rid); 1036 dmar_print_path(devscope->Bus, dev_path_len, 1037 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1038 printf("\n"); 1039 } 1040 unit = dmar_find_by_scope(resmem->Segment, 1041 devscope->Bus, 1042 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1043 dev_path_len); 1044 if (iria->dmar != unit) 1045 continue; 1046 dmar_get_ctx_for_devpath(iria->dmar, rid, 1047 resmem->Segment, devscope->Bus, 1048 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1049 dev_path_len, false, true); 1050 } else { 1051 unit = dmar_find(dev, false); 1052 if (iria->dmar != unit) 1053 continue; 1054 iommu_instantiate_ctx(&(iria)->dmar->iommu, 1055 dev, true); 1056 } 1057 } 1058 1059 return (1); 1060 1061 } 1062 1063 /* 1064 * Pre-create all contexts for the DMAR which have RMRR entries. 1065 */ 1066 int 1067 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) 1068 { 1069 struct dmar_unit *dmar; 1070 struct inst_rmrr_iter_args iria; 1071 int error; 1072 1073 dmar = IOMMU2DMAR(unit); 1074 1075 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1076 return (0); 1077 1078 error = 0; 1079 iria.dmar = dmar; 1080 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1081 DMAR_LOCK(dmar); 1082 if (!LIST_EMPTY(&dmar->domains)) { 1083 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1084 ("dmar%d: RMRR not handled but translation is already enabled", 1085 dmar->iommu.unit)); 1086 error = dmar_disable_protected_regions(dmar); 1087 if (error != 0) 1088 printf("dmar%d: Failed to disable protected regions\n", 1089 dmar->iommu.unit); 1090 error = dmar_enable_translation(dmar); 1091 if (bootverbose) { 1092 if (error == 0) { 1093 printf("dmar%d: enabled translation\n", 1094 dmar->iommu.unit); 1095 } else { 1096 printf("dmar%d: enabling translation failed, " 1097 "error %d\n", dmar->iommu.unit, error); 1098 } 1099 } 1100 } 1101 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1102 return (error); 1103 } 1104 1105 #ifdef DDB 1106 #include <ddb/ddb.h> 1107 #include <ddb/db_lex.h> 1108 1109 static void 1110 dmar_print_domain_entry(const struct iommu_map_entry *entry) 1111 { 1112 struct iommu_map_entry *l, *r; 1113 1114 db_printf( 1115 " start %jx end %jx first %jx last %jx free_down %jx flags %x ", 1116 entry->start, entry->end, entry->first, entry->last, 1117 entry->free_down, entry->flags); 1118 db_printf("left "); 1119 l = RB_LEFT(entry, rb_entry); 1120 if (l == NULL) 1121 db_printf("NULL "); 1122 else 1123 db_printf("%jx ", l->start); 1124 db_printf("right "); 1125 r = RB_RIGHT(entry, rb_entry); 1126 if (r == NULL) 1127 db_printf("NULL"); 1128 else 1129 db_printf("%jx", r->start); 1130 db_printf("\n"); 1131 } 1132 1133 static void 1134 dmar_print_ctx(struct dmar_ctx *ctx) 1135 { 1136 1137 db_printf( 1138 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n", 1139 ctx, pci_get_bus(ctx->context.tag->owner), 1140 pci_get_slot(ctx->context.tag->owner), 1141 pci_get_function(ctx->context.tag->owner), ctx->refs, 1142 ctx->context.flags, ctx->context.loads, ctx->context.unloads); 1143 } 1144 1145 static void 1146 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1147 { 1148 struct iommu_domain *iodom; 1149 struct iommu_map_entry *entry; 1150 struct dmar_ctx *ctx; 1151 1152 iodom = DOM2IODOM(domain); 1153 1154 db_printf( 1155 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1156 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1157 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1158 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt, 1159 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt); 1160 if (!LIST_EMPTY(&domain->contexts)) { 1161 db_printf(" Contexts:\n"); 1162 LIST_FOREACH(ctx, &domain->contexts, link) 1163 dmar_print_ctx(ctx); 1164 } 1165 if (!show_mappings) 1166 return; 1167 db_printf(" mapped:\n"); 1168 RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) { 1169 dmar_print_domain_entry(entry); 1170 if (db_pager_quit) 1171 break; 1172 } 1173 if (db_pager_quit) 1174 return; 1175 db_printf(" unloading:\n"); 1176 TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) { 1177 dmar_print_domain_entry(entry); 1178 if (db_pager_quit) 1179 break; 1180 } 1181 } 1182 1183 DB_SHOW_COMMAND_FLAGS(dmar_domain, db_dmar_print_domain, CS_OWN) 1184 { 1185 struct dmar_unit *unit; 1186 struct dmar_domain *domain; 1187 struct dmar_ctx *ctx; 1188 bool show_mappings, valid; 1189 int pci_domain, bus, device, function, i, t; 1190 db_expr_t radix; 1191 1192 valid = false; 1193 radix = db_radix; 1194 db_radix = 10; 1195 t = db_read_token(); 1196 if (t == tSLASH) { 1197 t = db_read_token(); 1198 if (t != tIDENT) { 1199 db_printf("Bad modifier\n"); 1200 db_radix = radix; 1201 db_skip_to_eol(); 1202 return; 1203 } 1204 show_mappings = strchr(db_tok_string, 'm') != NULL; 1205 t = db_read_token(); 1206 } else { 1207 show_mappings = false; 1208 } 1209 if (t == tNUMBER) { 1210 pci_domain = db_tok_number; 1211 t = db_read_token(); 1212 if (t == tNUMBER) { 1213 bus = db_tok_number; 1214 t = db_read_token(); 1215 if (t == tNUMBER) { 1216 device = db_tok_number; 1217 t = db_read_token(); 1218 if (t == tNUMBER) { 1219 function = db_tok_number; 1220 valid = true; 1221 } 1222 } 1223 } 1224 } 1225 db_radix = radix; 1226 db_skip_to_eol(); 1227 if (!valid) { 1228 db_printf("usage: show dmar_domain [/m] " 1229 "<domain> <bus> <device> <func>\n"); 1230 return; 1231 } 1232 for (i = 0; i < dmar_devcnt; i++) { 1233 unit = device_get_softc(dmar_devs[i]); 1234 LIST_FOREACH(domain, &unit->domains, link) { 1235 LIST_FOREACH(ctx, &domain->contexts, link) { 1236 if (pci_domain == unit->segment && 1237 bus == pci_get_bus(ctx->context.tag->owner) && 1238 device == 1239 pci_get_slot(ctx->context.tag->owner) && 1240 function == 1241 pci_get_function(ctx->context.tag->owner)) { 1242 dmar_print_domain(domain, 1243 show_mappings); 1244 goto out; 1245 } 1246 } 1247 } 1248 } 1249 out:; 1250 } 1251 1252 static void 1253 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1254 { 1255 struct dmar_unit *unit; 1256 struct dmar_domain *domain; 1257 int i, frir; 1258 1259 unit = device_get_softc(dmar_devs[idx]); 1260 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, 1261 unit, dmar_read8(unit, DMAR_RTADDR_REG), 1262 dmar_read4(unit, DMAR_VER_REG)); 1263 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1264 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1265 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1266 dmar_read4(unit, DMAR_GSTS_REG), 1267 dmar_read4(unit, DMAR_FSTS_REG), 1268 dmar_read4(unit, DMAR_FECTL_REG)); 1269 if (unit->ir_enabled) { 1270 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1271 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1272 } 1273 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1274 dmar_read4(unit, DMAR_FEDATA_REG), 1275 dmar_read4(unit, DMAR_FEADDR_REG), 1276 dmar_read4(unit, DMAR_FEUADDR_REG)); 1277 db_printf("primary fault log:\n"); 1278 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1279 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1280 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1281 (uintmax_t)dmar_read8(unit, frir), 1282 (uintmax_t)dmar_read8(unit, frir + 8)); 1283 } 1284 if (DMAR_HAS_QI(unit)) { 1285 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1286 dmar_read4(unit, DMAR_IEDATA_REG), 1287 dmar_read4(unit, DMAR_IEADDR_REG), 1288 dmar_read4(unit, DMAR_IEUADDR_REG)); 1289 if (unit->qi_enabled) { 1290 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1291 "size 0x%jx\n" 1292 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1293 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1294 (uintmax_t)unit->inv_queue, 1295 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1296 (uintmax_t)unit->inv_queue_size, 1297 dmar_read4(unit, DMAR_IQH_REG), 1298 dmar_read4(unit, DMAR_IQT_REG), 1299 unit->inv_queue_avail, 1300 dmar_read4(unit, DMAR_ICS_REG), 1301 dmar_read4(unit, DMAR_IECTL_REG), 1302 unit->inv_waitd_seq_hw, 1303 &unit->inv_waitd_seq_hw, 1304 (uintmax_t)unit->inv_waitd_seq_hw_phys, 1305 unit->inv_waitd_seq, 1306 unit->inv_waitd_gen); 1307 } else { 1308 db_printf("qi is disabled\n"); 1309 } 1310 } 1311 if (show_domains) { 1312 db_printf("domains:\n"); 1313 LIST_FOREACH(domain, &unit->domains, link) { 1314 dmar_print_domain(domain, show_mappings); 1315 if (db_pager_quit) 1316 break; 1317 } 1318 } 1319 } 1320 1321 DB_SHOW_COMMAND(dmar, db_dmar_print) 1322 { 1323 bool show_domains, show_mappings; 1324 1325 show_domains = strchr(modif, 'd') != NULL; 1326 show_mappings = strchr(modif, 'm') != NULL; 1327 if (!have_addr) { 1328 db_printf("usage: show dmar [/d] [/m] index\n"); 1329 return; 1330 } 1331 dmar_print_one((int)addr, show_domains, show_mappings); 1332 } 1333 1334 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1335 { 1336 int i; 1337 bool show_domains, show_mappings; 1338 1339 show_domains = strchr(modif, 'd') != NULL; 1340 show_mappings = strchr(modif, 'm') != NULL; 1341 1342 for (i = 0; i < dmar_devcnt; i++) { 1343 dmar_print_one(i, show_domains, show_mappings); 1344 if (db_pager_quit) 1345 break; 1346 } 1347 } 1348 #endif 1349 1350 struct iommu_unit * 1351 iommu_find(device_t dev, bool verbose) 1352 { 1353 struct dmar_unit *dmar; 1354 1355 dmar = dmar_find(dev, verbose); 1356 1357 return (&dmar->iommu); 1358 } 1359