1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "opt_acpi.h" 32 #if defined(__amd64__) 33 #define DEV_APIC 34 #else 35 #include "opt_apic.h" 36 #endif 37 #include "opt_ddb.h" 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/memdesc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/rman.h> 48 #include <sys/rwlock.h> 49 #include <sys/smp.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 #include <sys/vmem.h> 53 #include <vm/vm.h> 54 #include <vm/vm_extern.h> 55 #include <vm/vm_kern.h> 56 #include <vm/vm_object.h> 57 #include <vm/vm_page.h> 58 #include <vm/vm_pager.h> 59 #include <vm/vm_map.h> 60 #include <contrib/dev/acpica/include/acpi.h> 61 #include <contrib/dev/acpica/include/accommon.h> 62 #include <dev/acpica/acpivar.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <machine/bus.h> 66 #include <machine/pci_cfgreg.h> 67 #include <machine/md_var.h> 68 #include <machine/cputypes.h> 69 #include <x86/include/busdma_impl.h> 70 #include <dev/iommu/busdma_iommu.h> 71 #include <x86/iommu/intel_reg.h> 72 #include <x86/iommu/x86_iommu.h> 73 #include <x86/iommu/intel_dmar.h> 74 75 #ifdef DEV_APIC 76 #include "pcib_if.h" 77 #include <machine/intr_machdep.h> 78 #include <x86/apicreg.h> 79 #include <x86/apicvar.h> 80 #endif 81 82 #define DMAR_FAULT_IRQ_RID 0 83 #define DMAR_QI_IRQ_RID 1 84 #define DMAR_REG_RID 2 85 86 static device_t *dmar_devs; 87 static int dmar_devcnt; 88 89 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 90 91 static void 92 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 93 { 94 ACPI_TABLE_DMAR *dmartbl; 95 ACPI_DMAR_HEADER *dmarh; 96 char *ptr, *ptrend; 97 ACPI_STATUS status; 98 99 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 100 if (ACPI_FAILURE(status)) 101 return; 102 ptr = (char *)dmartbl + sizeof(*dmartbl); 103 ptrend = (char *)dmartbl + dmartbl->Header.Length; 104 for (;;) { 105 if (ptr >= ptrend) 106 break; 107 dmarh = (ACPI_DMAR_HEADER *)ptr; 108 if (dmarh->Length <= 0) { 109 printf("dmar_identify: corrupted DMAR table, l %d\n", 110 dmarh->Length); 111 break; 112 } 113 ptr += dmarh->Length; 114 if (!iter(dmarh, arg)) 115 break; 116 } 117 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 118 } 119 120 struct find_iter_args { 121 int i; 122 ACPI_DMAR_HARDWARE_UNIT *res; 123 }; 124 125 static int 126 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 127 { 128 struct find_iter_args *fia; 129 130 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 131 return (1); 132 133 fia = arg; 134 if (fia->i == 0) { 135 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 136 return (0); 137 } 138 fia->i--; 139 return (1); 140 } 141 142 static ACPI_DMAR_HARDWARE_UNIT * 143 dmar_find_by_index(int idx) 144 { 145 struct find_iter_args fia; 146 147 fia.i = idx; 148 fia.res = NULL; 149 dmar_iterate_tbl(dmar_find_iter, &fia); 150 return (fia.res); 151 } 152 153 static int 154 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 155 { 156 157 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 158 dmar_devcnt++; 159 return (1); 160 } 161 162 int dmar_rmrr_enable = 1; 163 164 static int dmar_enable = 0; 165 static void 166 dmar_identify(driver_t *driver, device_t parent) 167 { 168 ACPI_TABLE_DMAR *dmartbl; 169 ACPI_DMAR_HARDWARE_UNIT *dmarh; 170 ACPI_STATUS status; 171 int i, error; 172 173 if (acpi_disabled("dmar")) 174 return; 175 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 176 if (!dmar_enable) 177 return; 178 TUNABLE_INT_FETCH("hw.dmar.rmrr_enable", &dmar_rmrr_enable); 179 180 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 181 if (ACPI_FAILURE(status)) 182 return; 183 haw = dmartbl->Width + 1; 184 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 185 iommu_high = BUS_SPACE_MAXADDR; 186 else 187 iommu_high = 1ULL << (haw + 1); 188 if (bootverbose) { 189 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 190 (unsigned)dmartbl->Flags, 191 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 192 } 193 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 194 195 dmar_iterate_tbl(dmar_count_iter, NULL); 196 if (dmar_devcnt == 0) 197 return; 198 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 199 M_WAITOK | M_ZERO); 200 for (i = 0; i < dmar_devcnt; i++) { 201 dmarh = dmar_find_by_index(i); 202 if (dmarh == NULL) { 203 printf("dmar_identify: cannot find HWUNIT %d\n", i); 204 continue; 205 } 206 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 207 if (dmar_devs[i] == NULL) { 208 printf("dmar_identify: cannot create instance %d\n", i); 209 continue; 210 } 211 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 212 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 213 if (error != 0) { 214 printf( 215 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 216 i, (uintmax_t)dmarh->Address, error); 217 device_delete_child(parent, dmar_devs[i]); 218 dmar_devs[i] = NULL; 219 } 220 } 221 } 222 223 static int 224 dmar_probe(device_t dev) 225 { 226 227 if (acpi_get_handle(dev) != NULL) 228 return (ENXIO); 229 device_set_desc(dev, "DMA remap"); 230 return (BUS_PROBE_NOWILDCARD); 231 } 232 233 static void 234 dmar_release_resources(device_t dev, struct dmar_unit *unit) 235 { 236 int i; 237 238 iommu_fini_busdma(&unit->iommu); 239 dmar_fini_irt(unit); 240 dmar_fini_qi(unit); 241 dmar_fini_fault_log(unit); 242 for (i = 0; i < DMAR_INTR_TOTAL; i++) 243 iommu_release_intr(DMAR2IOMMU(unit), i); 244 if (unit->regs != NULL) { 245 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 246 unit->regs); 247 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 248 unit->regs); 249 unit->regs = NULL; 250 } 251 if (unit->domids != NULL) { 252 delete_unrhdr(unit->domids); 253 unit->domids = NULL; 254 } 255 if (unit->ctx_obj != NULL) { 256 vm_object_deallocate(unit->ctx_obj); 257 unit->ctx_obj = NULL; 258 } 259 } 260 261 #ifdef DEV_APIC 262 static int 263 dmar_remap_intr(device_t dev, device_t child, u_int irq) 264 { 265 struct dmar_unit *unit; 266 struct iommu_msi_data *dmd; 267 uint64_t msi_addr; 268 uint32_t msi_data; 269 int i, error; 270 271 unit = device_get_softc(dev); 272 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 273 dmd = &unit->x86c.intrs[i]; 274 if (irq == dmd->irq) { 275 error = PCIB_MAP_MSI(device_get_parent( 276 device_get_parent(dev)), 277 dev, irq, &msi_addr, &msi_data); 278 if (error != 0) 279 return (error); 280 DMAR_LOCK(unit); 281 dmd->msi_data = msi_data; 282 dmd->msi_addr = msi_addr; 283 (dmd->disable_intr)(DMAR2IOMMU(unit)); 284 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); 285 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); 286 dmar_write4(unit, dmd->msi_uaddr_reg, 287 dmd->msi_addr >> 32); 288 (dmd->enable_intr)(DMAR2IOMMU(unit)); 289 DMAR_UNLOCK(unit); 290 return (0); 291 } 292 } 293 return (ENOENT); 294 } 295 #endif 296 297 static void 298 dmar_print_caps(device_t dev, struct dmar_unit *unit, 299 ACPI_DMAR_HARDWARE_UNIT *dmaru) 300 { 301 uint32_t caphi, ecaphi; 302 303 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 304 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 305 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 306 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 307 caphi = unit->hw_cap >> 32; 308 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 309 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 310 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 311 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 312 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 313 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 314 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 315 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 316 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 317 printf("\n"); 318 ecaphi = unit->hw_ecap >> 32; 319 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 320 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 321 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 322 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 323 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 324 DMAR_ECAP_IRO(unit->hw_ecap)); 325 } 326 327 static int 328 dmar_attach(device_t dev) 329 { 330 struct dmar_unit *unit; 331 ACPI_DMAR_HARDWARE_UNIT *dmaru; 332 struct iommu_msi_data *dmd; 333 uint64_t timeout; 334 int disable_pmr; 335 int i, error; 336 337 unit = device_get_softc(dev); 338 unit->iommu.unit = device_get_unit(dev); 339 unit->iommu.dev = dev; 340 dmaru = dmar_find_by_index(unit->iommu.unit); 341 if (dmaru == NULL) 342 return (EINVAL); 343 unit->segment = dmaru->Segment; 344 unit->base = dmaru->Address; 345 unit->reg_rid = DMAR_REG_RID; 346 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 347 &unit->reg_rid, RF_ACTIVE); 348 if (unit->regs == NULL) { 349 device_printf(dev, "cannot allocate register window\n"); 350 dmar_devs[unit->iommu.unit] = NULL; 351 return (ENOMEM); 352 } 353 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 354 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 355 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 356 if (bootverbose) 357 dmar_print_caps(dev, unit, dmaru); 358 dmar_quirks_post_ident(unit); 359 360 timeout = dmar_get_timeout(); 361 TUNABLE_UINT64_FETCH("hw.iommu.dmar.timeout", &timeout); 362 dmar_update_timeout(timeout); 363 364 for (i = 0; i < DMAR_INTR_TOTAL; i++) 365 unit->x86c.intrs[i].irq = -1; 366 367 dmd = &unit->x86c.intrs[DMAR_INTR_FAULT]; 368 dmd->name = "fault"; 369 dmd->irq_rid = DMAR_FAULT_IRQ_RID; 370 dmd->handler = dmar_fault_intr; 371 dmd->msi_data_reg = DMAR_FEDATA_REG; 372 dmd->msi_addr_reg = DMAR_FEADDR_REG; 373 dmd->msi_uaddr_reg = DMAR_FEUADDR_REG; 374 dmd->enable_intr = dmar_enable_fault_intr; 375 dmd->disable_intr = dmar_disable_fault_intr; 376 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_FAULT); 377 if (error != 0) { 378 dmar_release_resources(dev, unit); 379 dmar_devs[unit->iommu.unit] = NULL; 380 return (error); 381 } 382 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); 383 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); 384 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); 385 386 if (DMAR_HAS_QI(unit)) { 387 dmd = &unit->x86c.intrs[DMAR_INTR_QI]; 388 dmd->name = "qi"; 389 dmd->irq_rid = DMAR_QI_IRQ_RID; 390 dmd->handler = dmar_qi_intr; 391 dmd->msi_data_reg = DMAR_IEDATA_REG; 392 dmd->msi_addr_reg = DMAR_IEADDR_REG; 393 dmd->msi_uaddr_reg = DMAR_IEUADDR_REG; 394 dmd->enable_intr = dmar_enable_qi_intr; 395 dmd->disable_intr = dmar_disable_qi_intr; 396 error = iommu_alloc_irq(DMAR2IOMMU(unit), DMAR_INTR_QI); 397 if (error != 0) { 398 dmar_release_resources(dev, unit); 399 dmar_devs[unit->iommu.unit] = NULL; 400 return (error); 401 } 402 403 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); 404 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); 405 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); 406 } 407 408 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); 409 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 410 &unit->iommu.lock); 411 LIST_INIT(&unit->domains); 412 413 /* 414 * 9.2 "Context Entry": 415 * When Caching Mode (CM) field is reported as Set, the 416 * domain-id value of zero is architecturally reserved. 417 * Software must not use domain-id value of zero 418 * when CM is Set. 419 */ 420 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 421 alloc_unr_specific(unit->domids, 0); 422 423 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 424 DMAR_CTX_CNT), 0, 0, NULL); 425 426 /* 427 * Allocate and load the root entry table pointer. Enable the 428 * address translation after the required invalidations are 429 * done. 430 */ 431 iommu_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); 432 DMAR_LOCK(unit); 433 error = dmar_load_root_entry_ptr(unit); 434 if (error != 0) { 435 DMAR_UNLOCK(unit); 436 dmar_release_resources(dev, unit); 437 dmar_devs[unit->iommu.unit] = NULL; 438 return (error); 439 } 440 error = dmar_inv_ctx_glob(unit); 441 if (error != 0) { 442 DMAR_UNLOCK(unit); 443 dmar_release_resources(dev, unit); 444 dmar_devs[unit->iommu.unit] = NULL; 445 return (error); 446 } 447 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 448 error = dmar_inv_iotlb_glob(unit); 449 if (error != 0) { 450 DMAR_UNLOCK(unit); 451 dmar_release_resources(dev, unit); 452 dmar_devs[unit->iommu.unit] = NULL; 453 return (error); 454 } 455 } 456 457 DMAR_UNLOCK(unit); 458 error = dmar_init_fault_log(unit); 459 if (error != 0) { 460 dmar_release_resources(dev, unit); 461 dmar_devs[unit->iommu.unit] = NULL; 462 return (error); 463 } 464 error = dmar_init_qi(unit); 465 if (error != 0) { 466 dmar_release_resources(dev, unit); 467 dmar_devs[unit->iommu.unit] = NULL; 468 return (error); 469 } 470 error = dmar_init_irt(unit); 471 if (error != 0) { 472 dmar_release_resources(dev, unit); 473 dmar_devs[unit->iommu.unit] = NULL; 474 return (error); 475 } 476 477 disable_pmr = 0; 478 TUNABLE_INT_FETCH("hw.dmar.pmr.disable", &disable_pmr); 479 if (disable_pmr) { 480 error = dmar_disable_protected_regions(unit); 481 if (error != 0) 482 device_printf(dev, 483 "Failed to disable protected regions\n"); 484 } 485 486 error = iommu_init_busdma(&unit->iommu); 487 if (error != 0) { 488 dmar_release_resources(dev, unit); 489 dmar_devs[unit->iommu.unit] = NULL; 490 return (error); 491 } 492 493 #ifdef NOTYET 494 DMAR_LOCK(unit); 495 error = dmar_enable_translation(unit); 496 if (error != 0) { 497 DMAR_UNLOCK(unit); 498 dmar_release_resources(dev, unit); 499 dmar_devs[unit->iommu.unit] = NULL; 500 return (error); 501 } 502 DMAR_UNLOCK(unit); 503 #endif 504 505 return (0); 506 } 507 508 static int 509 dmar_detach(device_t dev) 510 { 511 512 return (EBUSY); 513 } 514 515 static int 516 dmar_suspend(device_t dev) 517 { 518 519 return (0); 520 } 521 522 static int 523 dmar_resume(device_t dev) 524 { 525 526 /* XXXKIB */ 527 return (0); 528 } 529 530 static device_method_t dmar_methods[] = { 531 DEVMETHOD(device_identify, dmar_identify), 532 DEVMETHOD(device_probe, dmar_probe), 533 DEVMETHOD(device_attach, dmar_attach), 534 DEVMETHOD(device_detach, dmar_detach), 535 DEVMETHOD(device_suspend, dmar_suspend), 536 DEVMETHOD(device_resume, dmar_resume), 537 #ifdef DEV_APIC 538 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 539 #endif 540 DEVMETHOD_END 541 }; 542 543 static driver_t dmar_driver = { 544 "dmar", 545 dmar_methods, 546 sizeof(struct dmar_unit), 547 }; 548 549 DRIVER_MODULE(dmar, acpi, dmar_driver, 0, 0); 550 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 551 552 static void 553 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 554 { 555 int i; 556 557 printf("[%d, ", busno); 558 for (i = 0; i < depth; i++) { 559 if (i != 0) 560 printf(", "); 561 printf("(%d, %d)", path[i].Device, path[i].Function); 562 } 563 printf("]"); 564 } 565 566 int 567 dmar_dev_depth(device_t child) 568 { 569 devclass_t pci_class; 570 device_t bus, pcib; 571 int depth; 572 573 pci_class = devclass_find("pci"); 574 for (depth = 1; ; depth++) { 575 bus = device_get_parent(child); 576 pcib = device_get_parent(bus); 577 if (device_get_devclass(device_get_parent(pcib)) != 578 pci_class) 579 return (depth); 580 child = pcib; 581 } 582 } 583 584 void 585 dmar_dev_path(device_t child, int *busno, void *path1, int depth) 586 { 587 devclass_t pci_class; 588 device_t bus, pcib; 589 ACPI_DMAR_PCI_PATH *path; 590 591 pci_class = devclass_find("pci"); 592 path = path1; 593 for (depth--; depth != -1; depth--) { 594 path[depth].Device = pci_get_slot(child); 595 path[depth].Function = pci_get_function(child); 596 bus = device_get_parent(child); 597 pcib = device_get_parent(bus); 598 if (device_get_devclass(device_get_parent(pcib)) != 599 pci_class) { 600 /* reached a host bridge */ 601 *busno = pcib_get_bus(bus); 602 return; 603 } 604 child = pcib; 605 } 606 panic("wrong depth"); 607 } 608 609 static int 610 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 611 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 612 enum AcpiDmarScopeType scope_type) 613 { 614 int i, depth; 615 616 if (busno1 != busno2) 617 return (0); 618 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 619 return (0); 620 depth = depth1; 621 if (depth2 < depth) 622 depth = depth2; 623 for (i = 0; i < depth; i++) { 624 if (path1[i].Device != path2[i].Device || 625 path1[i].Function != path2[i].Function) 626 return (0); 627 } 628 return (1); 629 } 630 631 static int 632 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 633 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 634 { 635 ACPI_DMAR_PCI_PATH *path; 636 int path_len; 637 638 if (devscope->Length < sizeof(*devscope)) { 639 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 640 devscope->Length); 641 return (-1); 642 } 643 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 644 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 645 return (0); 646 path_len = devscope->Length - sizeof(*devscope); 647 if (path_len % 2 != 0) { 648 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 649 devscope->Length); 650 return (-1); 651 } 652 path_len /= 2; 653 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 654 if (path_len == 0) { 655 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 656 devscope->Length); 657 return (-1); 658 } 659 660 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 661 dev_path, dev_path_len, devscope->EntryType)); 662 } 663 664 static bool 665 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 666 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 667 { 668 ACPI_DMAR_HARDWARE_UNIT *dmarh; 669 ACPI_DMAR_DEVICE_SCOPE *devscope; 670 char *ptr, *ptrend; 671 int match; 672 673 dmarh = dmar_find_by_index(unit->iommu.unit); 674 if (dmarh == NULL) 675 return (false); 676 if (dmarh->Segment != dev_domain) 677 return (false); 678 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 679 if (banner != NULL) 680 *banner = "INCLUDE_ALL"; 681 return (true); 682 } 683 ptr = (char *)dmarh + sizeof(*dmarh); 684 ptrend = (char *)dmarh + dmarh->Header.Length; 685 while (ptr < ptrend) { 686 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 687 ptr += devscope->Length; 688 match = dmar_match_devscope(devscope, dev_busno, dev_path, 689 dev_path_len); 690 if (match == -1) 691 return (false); 692 if (match == 1) { 693 if (banner != NULL) 694 *banner = "specific match"; 695 return (true); 696 } 697 } 698 return (false); 699 } 700 701 static struct dmar_unit * 702 dmar_find_by_scope(int dev_domain, int dev_busno, 703 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 704 { 705 struct dmar_unit *unit; 706 int i; 707 708 for (i = 0; i < dmar_devcnt; i++) { 709 if (dmar_devs[i] == NULL) 710 continue; 711 unit = device_get_softc(dmar_devs[i]); 712 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 713 dev_path_len, NULL)) 714 return (unit); 715 } 716 return (NULL); 717 } 718 719 struct dmar_unit * 720 dmar_find(device_t dev, bool verbose) 721 { 722 struct dmar_unit *unit; 723 const char *banner; 724 int i, dev_domain, dev_busno, dev_path_len; 725 726 /* 727 * This function can only handle PCI(e) devices. 728 */ 729 if (device_get_devclass(device_get_parent(dev)) != 730 devclass_find("pci")) 731 return (NULL); 732 733 dev_domain = pci_get_domain(dev); 734 dev_path_len = dmar_dev_depth(dev); 735 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 736 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 737 banner = ""; 738 739 for (i = 0; i < dmar_devcnt; i++) { 740 if (dmar_devs[i] == NULL) 741 continue; 742 unit = device_get_softc(dmar_devs[i]); 743 if (dmar_match_by_path(unit, dev_domain, dev_busno, 744 dev_path, dev_path_len, &banner)) 745 break; 746 } 747 if (i == dmar_devcnt) 748 return (NULL); 749 750 if (verbose) { 751 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 752 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 753 pci_get_function(dev), unit->iommu.unit, banner); 754 printf(" scope path "); 755 dmar_print_path(dev_busno, dev_path_len, dev_path); 756 printf("\n"); 757 } 758 return (unit); 759 } 760 761 static struct dmar_unit * 762 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 763 { 764 device_t dmar_dev; 765 struct dmar_unit *unit; 766 ACPI_DMAR_HARDWARE_UNIT *dmarh; 767 ACPI_DMAR_DEVICE_SCOPE *devscope; 768 ACPI_DMAR_PCI_PATH *path; 769 char *ptr, *ptrend; 770 #ifdef DEV_APIC 771 int error; 772 #endif 773 int i; 774 775 for (i = 0; i < dmar_devcnt; i++) { 776 dmar_dev = dmar_devs[i]; 777 if (dmar_dev == NULL) 778 continue; 779 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 780 dmarh = dmar_find_by_index(i); 781 if (dmarh == NULL) 782 continue; 783 ptr = (char *)dmarh + sizeof(*dmarh); 784 ptrend = (char *)dmarh + dmarh->Header.Length; 785 for (;;) { 786 if (ptr >= ptrend) 787 break; 788 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 789 ptr += devscope->Length; 790 if (devscope->EntryType != entry_type) 791 continue; 792 if (devscope->EnumerationId != id) 793 continue; 794 #ifdef DEV_APIC 795 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 796 error = ioapic_get_rid(id, rid); 797 /* 798 * If our IOAPIC has PCI bindings then 799 * use the PCI device rid. 800 */ 801 if (error == 0) 802 return (unit); 803 } 804 #endif 805 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 806 == 2) { 807 if (rid != NULL) { 808 path = (ACPI_DMAR_PCI_PATH *) 809 (devscope + 1); 810 *rid = PCI_RID(devscope->Bus, 811 path->Device, path->Function); 812 } 813 return (unit); 814 } 815 printf( 816 "dmar_find_nonpci: id %d type %d path length != 2\n", 817 id, entry_type); 818 break; 819 } 820 } 821 return (NULL); 822 } 823 824 struct dmar_unit * 825 dmar_find_hpet(device_t dev, uint16_t *rid) 826 { 827 828 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 829 rid)); 830 } 831 832 struct dmar_unit * 833 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 834 { 835 836 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 837 } 838 839 struct rmrr_iter_args { 840 struct dmar_domain *domain; 841 int dev_domain; 842 int dev_busno; 843 const ACPI_DMAR_PCI_PATH *dev_path; 844 int dev_path_len; 845 struct iommu_map_entries_tailq *rmrr_entries; 846 }; 847 848 static int 849 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 850 { 851 struct rmrr_iter_args *ria; 852 ACPI_DMAR_RESERVED_MEMORY *resmem; 853 ACPI_DMAR_DEVICE_SCOPE *devscope; 854 struct iommu_map_entry *entry; 855 char *ptr, *ptrend; 856 int match; 857 858 if (!dmar_rmrr_enable) 859 return (1); 860 861 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 862 return (1); 863 864 ria = arg; 865 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 866 if (resmem->Segment != ria->dev_domain) 867 return (1); 868 869 ptr = (char *)resmem + sizeof(*resmem); 870 ptrend = (char *)resmem + resmem->Header.Length; 871 for (;;) { 872 if (ptr >= ptrend) 873 break; 874 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 875 ptr += devscope->Length; 876 match = dmar_match_devscope(devscope, ria->dev_busno, 877 ria->dev_path, ria->dev_path_len); 878 if (match == 1) { 879 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), 880 IOMMU_PGF_WAITOK); 881 entry->start = resmem->BaseAddress; 882 /* The RMRR entry end address is inclusive. */ 883 entry->end = resmem->EndAddress; 884 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 885 dmamap_link); 886 } 887 } 888 889 return (1); 890 } 891 892 void 893 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 894 const void *dev_path, int dev_path_len, 895 struct iommu_map_entries_tailq *rmrr_entries) 896 { 897 struct rmrr_iter_args ria; 898 899 ria.domain = domain; 900 ria.dev_domain = dev_domain; 901 ria.dev_busno = dev_busno; 902 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 903 ria.dev_path_len = dev_path_len; 904 ria.rmrr_entries = rmrr_entries; 905 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 906 } 907 908 struct inst_rmrr_iter_args { 909 struct dmar_unit *dmar; 910 }; 911 912 static device_t 913 dmar_path_dev(int segment, int path_len, int busno, 914 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 915 { 916 device_t dev; 917 int i; 918 919 dev = NULL; 920 for (i = 0; i < path_len; i++) { 921 dev = pci_find_dbsf(segment, busno, path->Device, 922 path->Function); 923 if (i != path_len - 1) { 924 busno = pci_cfgregread(segment, busno, path->Device, 925 path->Function, PCIR_SECBUS_1, 1); 926 path++; 927 } 928 } 929 *rid = PCI_RID(busno, path->Device, path->Function); 930 return (dev); 931 } 932 933 static int 934 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 935 { 936 const ACPI_DMAR_RESERVED_MEMORY *resmem; 937 const ACPI_DMAR_DEVICE_SCOPE *devscope; 938 struct inst_rmrr_iter_args *iria; 939 const char *ptr, *ptrend; 940 device_t dev; 941 struct dmar_unit *unit; 942 int dev_path_len; 943 uint16_t rid; 944 945 iria = arg; 946 947 if (!dmar_rmrr_enable) 948 return (1); 949 950 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 951 return (1); 952 953 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 954 if (resmem->Segment != iria->dmar->segment) 955 return (1); 956 957 ptr = (const char *)resmem + sizeof(*resmem); 958 ptrend = (const char *)resmem + resmem->Header.Length; 959 for (;;) { 960 if (ptr >= ptrend) 961 break; 962 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 963 ptr += devscope->Length; 964 /* XXXKIB bridge */ 965 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 966 continue; 967 rid = 0; 968 dev_path_len = (devscope->Length - 969 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 970 dev = dmar_path_dev(resmem->Segment, dev_path_len, 971 devscope->Bus, 972 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 973 if (dev == NULL) { 974 if (bootverbose) { 975 printf("dmar%d no dev found for RMRR " 976 "[%#jx, %#jx] rid %#x scope path ", 977 iria->dmar->iommu.unit, 978 (uintmax_t)resmem->BaseAddress, 979 (uintmax_t)resmem->EndAddress, 980 rid); 981 dmar_print_path(devscope->Bus, dev_path_len, 982 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 983 printf("\n"); 984 } 985 unit = dmar_find_by_scope(resmem->Segment, 986 devscope->Bus, 987 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 988 dev_path_len); 989 if (iria->dmar != unit) 990 continue; 991 dmar_get_ctx_for_devpath(iria->dmar, rid, 992 resmem->Segment, devscope->Bus, 993 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 994 dev_path_len, false, true); 995 } else { 996 unit = dmar_find(dev, false); 997 if (iria->dmar != unit) 998 continue; 999 iommu_instantiate_ctx(&(iria)->dmar->iommu, 1000 dev, true); 1001 } 1002 } 1003 1004 return (1); 1005 1006 } 1007 1008 /* 1009 * Pre-create all contexts for the DMAR which have RMRR entries. 1010 */ 1011 int 1012 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) 1013 { 1014 struct dmar_unit *dmar; 1015 struct inst_rmrr_iter_args iria; 1016 int error; 1017 1018 dmar = IOMMU2DMAR(unit); 1019 1020 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1021 return (0); 1022 1023 error = 0; 1024 iria.dmar = dmar; 1025 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1026 DMAR_LOCK(dmar); 1027 if (!LIST_EMPTY(&dmar->domains)) { 1028 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1029 ("dmar%d: RMRR not handled but translation is already enabled", 1030 dmar->iommu.unit)); 1031 error = dmar_disable_protected_regions(dmar); 1032 if (error != 0) 1033 printf("dmar%d: Failed to disable protected regions\n", 1034 dmar->iommu.unit); 1035 error = dmar_enable_translation(dmar); 1036 if (bootverbose) { 1037 if (error == 0) { 1038 printf("dmar%d: enabled translation\n", 1039 dmar->iommu.unit); 1040 } else { 1041 printf("dmar%d: enabling translation failed, " 1042 "error %d\n", dmar->iommu.unit, error); 1043 } 1044 } 1045 } 1046 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1047 return (error); 1048 } 1049 1050 #ifdef DDB 1051 #include <ddb/ddb.h> 1052 #include <ddb/db_lex.h> 1053 1054 static void 1055 dmar_print_domain_entry(const struct iommu_map_entry *entry) 1056 { 1057 struct iommu_map_entry *l, *r; 1058 1059 db_printf( 1060 " start %jx end %jx first %jx last %jx free_down %jx flags %x ", 1061 entry->start, entry->end, entry->first, entry->last, 1062 entry->free_down, entry->flags); 1063 db_printf("left "); 1064 l = RB_LEFT(entry, rb_entry); 1065 if (l == NULL) 1066 db_printf("NULL "); 1067 else 1068 db_printf("%jx ", l->start); 1069 db_printf("right "); 1070 r = RB_RIGHT(entry, rb_entry); 1071 if (r == NULL) 1072 db_printf("NULL"); 1073 else 1074 db_printf("%jx", r->start); 1075 db_printf("\n"); 1076 } 1077 1078 static void 1079 dmar_print_ctx(struct dmar_ctx *ctx) 1080 { 1081 1082 db_printf( 1083 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n", 1084 ctx, pci_get_bus(ctx->context.tag->owner), 1085 pci_get_slot(ctx->context.tag->owner), 1086 pci_get_function(ctx->context.tag->owner), ctx->refs, 1087 ctx->context.flags, ctx->context.loads, ctx->context.unloads); 1088 } 1089 1090 static void 1091 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1092 { 1093 struct iommu_domain *iodom; 1094 struct iommu_map_entry *entry; 1095 struct dmar_ctx *ctx; 1096 1097 iodom = DOM2IODOM(domain); 1098 1099 db_printf( 1100 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1101 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1102 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1103 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt, 1104 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt); 1105 if (!LIST_EMPTY(&domain->contexts)) { 1106 db_printf(" Contexts:\n"); 1107 LIST_FOREACH(ctx, &domain->contexts, link) 1108 dmar_print_ctx(ctx); 1109 } 1110 if (!show_mappings) 1111 return; 1112 db_printf(" mapped:\n"); 1113 RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) { 1114 dmar_print_domain_entry(entry); 1115 if (db_pager_quit) 1116 break; 1117 } 1118 if (db_pager_quit) 1119 return; 1120 db_printf(" unloading:\n"); 1121 TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) { 1122 dmar_print_domain_entry(entry); 1123 if (db_pager_quit) 1124 break; 1125 } 1126 } 1127 1128 DB_SHOW_COMMAND_FLAGS(dmar_domain, db_dmar_print_domain, CS_OWN) 1129 { 1130 struct dmar_unit *unit; 1131 struct dmar_domain *domain; 1132 struct dmar_ctx *ctx; 1133 bool show_mappings, valid; 1134 int pci_domain, bus, device, function, i, t; 1135 db_expr_t radix; 1136 1137 valid = false; 1138 radix = db_radix; 1139 db_radix = 10; 1140 t = db_read_token(); 1141 if (t == tSLASH) { 1142 t = db_read_token(); 1143 if (t != tIDENT) { 1144 db_printf("Bad modifier\n"); 1145 db_radix = radix; 1146 db_skip_to_eol(); 1147 return; 1148 } 1149 show_mappings = strchr(db_tok_string, 'm') != NULL; 1150 t = db_read_token(); 1151 } else { 1152 show_mappings = false; 1153 } 1154 if (t == tNUMBER) { 1155 pci_domain = db_tok_number; 1156 t = db_read_token(); 1157 if (t == tNUMBER) { 1158 bus = db_tok_number; 1159 t = db_read_token(); 1160 if (t == tNUMBER) { 1161 device = db_tok_number; 1162 t = db_read_token(); 1163 if (t == tNUMBER) { 1164 function = db_tok_number; 1165 valid = true; 1166 } 1167 } 1168 } 1169 } 1170 db_radix = radix; 1171 db_skip_to_eol(); 1172 if (!valid) { 1173 db_printf("usage: show dmar_domain [/m] " 1174 "<domain> <bus> <device> <func>\n"); 1175 return; 1176 } 1177 for (i = 0; i < dmar_devcnt; i++) { 1178 unit = device_get_softc(dmar_devs[i]); 1179 LIST_FOREACH(domain, &unit->domains, link) { 1180 LIST_FOREACH(ctx, &domain->contexts, link) { 1181 if (pci_domain == unit->segment && 1182 bus == pci_get_bus(ctx->context.tag->owner) && 1183 device == 1184 pci_get_slot(ctx->context.tag->owner) && 1185 function == 1186 pci_get_function(ctx->context.tag->owner)) { 1187 dmar_print_domain(domain, 1188 show_mappings); 1189 goto out; 1190 } 1191 } 1192 } 1193 } 1194 out:; 1195 } 1196 1197 static void 1198 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1199 { 1200 struct dmar_unit *unit; 1201 struct dmar_domain *domain; 1202 int i, frir; 1203 1204 unit = device_get_softc(dmar_devs[idx]); 1205 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, 1206 unit, dmar_read8(unit, DMAR_RTADDR_REG), 1207 dmar_read4(unit, DMAR_VER_REG)); 1208 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1209 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1210 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1211 dmar_read4(unit, DMAR_GSTS_REG), 1212 dmar_read4(unit, DMAR_FSTS_REG), 1213 dmar_read4(unit, DMAR_FECTL_REG)); 1214 if (unit->ir_enabled) { 1215 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1216 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1217 } 1218 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1219 dmar_read4(unit, DMAR_FEDATA_REG), 1220 dmar_read4(unit, DMAR_FEADDR_REG), 1221 dmar_read4(unit, DMAR_FEUADDR_REG)); 1222 db_printf("primary fault log:\n"); 1223 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1224 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1225 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1226 (uintmax_t)dmar_read8(unit, frir), 1227 (uintmax_t)dmar_read8(unit, frir + 8)); 1228 } 1229 if (DMAR_HAS_QI(unit)) { 1230 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1231 dmar_read4(unit, DMAR_IEDATA_REG), 1232 dmar_read4(unit, DMAR_IEADDR_REG), 1233 dmar_read4(unit, DMAR_IEUADDR_REG)); 1234 if (unit->qi_enabled) { 1235 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1236 "size 0x%jx\n" 1237 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1238 " hw compl 0x%jx@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1239 (uintmax_t)unit->x86c.inv_queue, 1240 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1241 (uintmax_t)unit->x86c.inv_queue_size, 1242 dmar_read4(unit, DMAR_IQH_REG), 1243 dmar_read4(unit, DMAR_IQT_REG), 1244 unit->x86c.inv_queue_avail, 1245 dmar_read4(unit, DMAR_ICS_REG), 1246 dmar_read4(unit, DMAR_IECTL_REG), 1247 (uintmax_t)unit->x86c.inv_waitd_seq_hw, 1248 &unit->x86c.inv_waitd_seq_hw, 1249 (uintmax_t)unit->x86c.inv_waitd_seq_hw_phys, 1250 unit->x86c.inv_waitd_seq, 1251 unit->x86c.inv_waitd_gen); 1252 } else { 1253 db_printf("qi is disabled\n"); 1254 } 1255 } 1256 if (show_domains) { 1257 db_printf("domains:\n"); 1258 LIST_FOREACH(domain, &unit->domains, link) { 1259 dmar_print_domain(domain, show_mappings); 1260 if (db_pager_quit) 1261 break; 1262 } 1263 } 1264 } 1265 1266 DB_SHOW_COMMAND(dmar, db_dmar_print) 1267 { 1268 bool show_domains, show_mappings; 1269 1270 show_domains = strchr(modif, 'd') != NULL; 1271 show_mappings = strchr(modif, 'm') != NULL; 1272 if (!have_addr) { 1273 db_printf("usage: show dmar [/d] [/m] index\n"); 1274 return; 1275 } 1276 dmar_print_one((int)addr, show_domains, show_mappings); 1277 } 1278 1279 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1280 { 1281 int i; 1282 bool show_domains, show_mappings; 1283 1284 show_domains = strchr(modif, 'd') != NULL; 1285 show_mappings = strchr(modif, 'm') != NULL; 1286 1287 for (i = 0; i < dmar_devcnt; i++) { 1288 dmar_print_one(i, show_domains, show_mappings); 1289 if (db_pager_quit) 1290 break; 1291 } 1292 } 1293 #endif 1294 1295 static struct iommu_unit * 1296 dmar_find_method(device_t dev, bool verbose) 1297 { 1298 struct dmar_unit *dmar; 1299 1300 dmar = dmar_find(dev, verbose); 1301 return (&dmar->iommu); 1302 } 1303 1304 static struct x86_unit_common * 1305 dmar_get_x86_common(struct iommu_unit *unit) 1306 { 1307 struct dmar_unit *dmar; 1308 1309 dmar = IOMMU2DMAR(unit); 1310 return (&dmar->x86c); 1311 } 1312 1313 static void 1314 dmar_unit_pre_instantiate_ctx(struct iommu_unit *unit) 1315 { 1316 dmar_quirks_pre_use(unit); 1317 dmar_instantiate_rmrr_ctxs(unit); 1318 } 1319 1320 static struct x86_iommu dmar_x86_iommu = { 1321 .get_x86_common = dmar_get_x86_common, 1322 .unit_pre_instantiate_ctx = dmar_unit_pre_instantiate_ctx, 1323 .domain_unload_entry = dmar_domain_unload_entry, 1324 .domain_unload = dmar_domain_unload, 1325 .get_ctx = dmar_get_ctx, 1326 .free_ctx_locked = dmar_free_ctx_locked_method, 1327 .free_ctx = dmar_free_ctx_method, 1328 .find = dmar_find_method, 1329 .alloc_msi_intr = dmar_alloc_msi_intr, 1330 .map_msi_intr = dmar_map_msi_intr, 1331 .unmap_msi_intr = dmar_unmap_msi_intr, 1332 .map_ioapic_intr = dmar_map_ioapic_intr, 1333 .unmap_ioapic_intr = dmar_unmap_ioapic_intr, 1334 }; 1335 1336 static void 1337 x86_iommu_set_intel(void *arg __unused) 1338 { 1339 if (cpu_vendor_id == CPU_VENDOR_INTEL) 1340 set_x86_iommu(&dmar_x86_iommu); 1341 } 1342 1343 SYSINIT(x86_iommu, SI_SUB_TUNABLES, SI_ORDER_ANY, x86_iommu_set_intel, NULL); 1344