1 /*- 2 * Copyright (c) 2013-2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_acpi.h" 34 #if defined(__amd64__) 35 #define DEV_APIC 36 #else 37 #include "opt_apic.h" 38 #endif 39 #include "opt_ddb.h" 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/kernel.h> 44 #include <sys/lock.h> 45 #include <sys/malloc.h> 46 #include <sys/memdesc.h> 47 #include <sys/module.h> 48 #include <sys/rman.h> 49 #include <sys/rwlock.h> 50 #include <sys/smp.h> 51 #include <sys/taskqueue.h> 52 #include <sys/tree.h> 53 #include <sys/vmem.h> 54 #include <machine/bus.h> 55 #include <contrib/dev/acpica/include/acpi.h> 56 #include <contrib/dev/acpica/include/accommon.h> 57 #include <dev/acpica/acpivar.h> 58 #include <vm/vm.h> 59 #include <vm/vm_extern.h> 60 #include <vm/vm_kern.h> 61 #include <vm/vm_object.h> 62 #include <vm/vm_page.h> 63 #include <vm/vm_pager.h> 64 #include <vm/vm_map.h> 65 #include <x86/include/busdma_impl.h> 66 #include <x86/iommu/intel_reg.h> 67 #include <x86/iommu/busdma_dmar.h> 68 #include <x86/iommu/intel_dmar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #ifdef DEV_APIC 73 #include "pcib_if.h" 74 #endif 75 76 #define DMAR_FAULT_IRQ_RID 0 77 #define DMAR_QI_IRQ_RID 1 78 #define DMAR_REG_RID 2 79 80 static devclass_t dmar_devclass; 81 static device_t *dmar_devs; 82 static int dmar_devcnt; 83 84 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 85 86 static void 87 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 88 { 89 ACPI_TABLE_DMAR *dmartbl; 90 ACPI_DMAR_HEADER *dmarh; 91 char *ptr, *ptrend; 92 ACPI_STATUS status; 93 94 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 95 if (ACPI_FAILURE(status)) 96 return; 97 ptr = (char *)dmartbl + sizeof(*dmartbl); 98 ptrend = (char *)dmartbl + dmartbl->Header.Length; 99 for (;;) { 100 if (ptr >= ptrend) 101 break; 102 dmarh = (ACPI_DMAR_HEADER *)ptr; 103 if (dmarh->Length <= 0) { 104 printf("dmar_identify: corrupted DMAR table, l %d\n", 105 dmarh->Length); 106 break; 107 } 108 ptr += dmarh->Length; 109 if (!iter(dmarh, arg)) 110 break; 111 } 112 } 113 114 struct find_iter_args { 115 int i; 116 ACPI_DMAR_HARDWARE_UNIT *res; 117 }; 118 119 static int 120 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 121 { 122 struct find_iter_args *fia; 123 124 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 125 return (1); 126 127 fia = arg; 128 if (fia->i == 0) { 129 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 130 return (0); 131 } 132 fia->i--; 133 return (1); 134 } 135 136 static ACPI_DMAR_HARDWARE_UNIT * 137 dmar_find_by_index(int idx) 138 { 139 struct find_iter_args fia; 140 141 fia.i = idx; 142 fia.res = NULL; 143 dmar_iterate_tbl(dmar_find_iter, &fia); 144 return (fia.res); 145 } 146 147 static int 148 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 149 { 150 151 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 152 dmar_devcnt++; 153 return (1); 154 } 155 156 static int dmar_enable = 0; 157 static void 158 dmar_identify(driver_t *driver, device_t parent) 159 { 160 ACPI_TABLE_DMAR *dmartbl; 161 ACPI_DMAR_HARDWARE_UNIT *dmarh; 162 ACPI_STATUS status; 163 int i, error; 164 165 if (acpi_disabled("dmar")) 166 return; 167 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 168 if (!dmar_enable) 169 return; 170 #ifdef INVARIANTS 171 TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free); 172 #endif 173 TUNABLE_INT_FETCH("hw.dmar.match_verbose", &dmar_match_verbose); 174 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 175 if (ACPI_FAILURE(status)) 176 return; 177 haw = dmartbl->Width + 1; 178 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 179 dmar_high = BUS_SPACE_MAXADDR; 180 else 181 dmar_high = 1ULL << (haw + 1); 182 if (bootverbose) { 183 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 184 (unsigned)dmartbl->Flags, 185 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 186 } 187 188 dmar_iterate_tbl(dmar_count_iter, NULL); 189 if (dmar_devcnt == 0) 190 return; 191 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 192 M_WAITOK | M_ZERO); 193 for (i = 0; i < dmar_devcnt; i++) { 194 dmarh = dmar_find_by_index(i); 195 if (dmarh == NULL) { 196 printf("dmar_identify: cannot find HWUNIT %d\n", i); 197 continue; 198 } 199 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 200 if (dmar_devs[i] == NULL) { 201 printf("dmar_identify: cannot create instance %d\n", i); 202 continue; 203 } 204 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 205 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 206 if (error != 0) { 207 printf( 208 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 209 i, (uintmax_t)dmarh->Address, error); 210 device_delete_child(parent, dmar_devs[i]); 211 dmar_devs[i] = NULL; 212 } 213 } 214 } 215 216 static int 217 dmar_probe(device_t dev) 218 { 219 220 if (acpi_get_handle(dev) != NULL) 221 return (ENXIO); 222 device_set_desc(dev, "DMA remap"); 223 return (BUS_PROBE_NOWILDCARD); 224 } 225 226 static void 227 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx) 228 { 229 struct dmar_msi_data *dmd; 230 231 dmd = &unit->intrs[idx]; 232 if (dmd->irq == -1) 233 return; 234 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 235 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 236 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 237 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)), 238 dev, dmd->irq); 239 dmd->irq = -1; 240 } 241 242 static void 243 dmar_release_resources(device_t dev, struct dmar_unit *unit) 244 { 245 int i; 246 247 dmar_fini_busdma(unit); 248 dmar_fini_irt(unit); 249 dmar_fini_qi(unit); 250 dmar_fini_fault_log(unit); 251 for (i = 0; i < DMAR_INTR_TOTAL; i++) 252 dmar_release_intr(dev, unit, i); 253 if (unit->regs != NULL) { 254 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 255 unit->regs); 256 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 257 unit->regs); 258 unit->regs = NULL; 259 } 260 if (unit->domids != NULL) { 261 delete_unrhdr(unit->domids); 262 unit->domids = NULL; 263 } 264 if (unit->ctx_obj != NULL) { 265 vm_object_deallocate(unit->ctx_obj); 266 unit->ctx_obj = NULL; 267 } 268 } 269 270 static int 271 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx) 272 { 273 device_t pcib; 274 struct dmar_msi_data *dmd; 275 uint64_t msi_addr; 276 uint32_t msi_data; 277 int error; 278 279 dmd = &unit->intrs[idx]; 280 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */ 281 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq); 282 if (error != 0) { 283 device_printf(dev, "cannot allocate %s interrupt, %d\n", 284 dmd->name, error); 285 goto err1; 286 } 287 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid, 288 dmd->irq, 1); 289 if (error != 0) { 290 device_printf(dev, "cannot set %s interrupt resource, %d\n", 291 dmd->name, error); 292 goto err2; 293 } 294 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 295 &dmd->irq_rid, RF_ACTIVE); 296 if (dmd->irq_res == NULL) { 297 device_printf(dev, 298 "cannot allocate resource for %s interrupt\n", dmd->name); 299 error = ENXIO; 300 goto err3; 301 } 302 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC, 303 dmd->handler, NULL, unit, &dmd->intr_handle); 304 if (error != 0) { 305 device_printf(dev, "cannot setup %s interrupt, %d\n", 306 dmd->name, error); 307 goto err4; 308 } 309 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, dmd->name); 310 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data); 311 if (error != 0) { 312 device_printf(dev, "cannot map %s interrupt, %d\n", 313 dmd->name, error); 314 goto err5; 315 } 316 dmar_write4(unit, dmd->msi_data_reg, msi_data); 317 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 318 /* Only for xAPIC mode */ 319 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 320 return (0); 321 322 err5: 323 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 324 err4: 325 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 326 err3: 327 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 328 err2: 329 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq); 330 dmd->irq = -1; 331 err1: 332 return (error); 333 } 334 335 #ifdef DEV_APIC 336 static int 337 dmar_remap_intr(device_t dev, device_t child, u_int irq) 338 { 339 struct dmar_unit *unit; 340 struct dmar_msi_data *dmd; 341 uint64_t msi_addr; 342 uint32_t msi_data; 343 int i, error; 344 345 unit = device_get_softc(dev); 346 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 347 dmd = &unit->intrs[i]; 348 if (irq == dmd->irq) { 349 error = PCIB_MAP_MSI(device_get_parent( 350 device_get_parent(dev)), 351 dev, irq, &msi_addr, &msi_data); 352 if (error != 0) 353 return (error); 354 DMAR_LOCK(unit); 355 (dmd->disable_intr)(unit); 356 dmar_write4(unit, dmd->msi_data_reg, msi_data); 357 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 358 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 359 (dmd->enable_intr)(unit); 360 DMAR_UNLOCK(unit); 361 return (0); 362 } 363 } 364 return (ENOENT); 365 } 366 #endif 367 368 static void 369 dmar_print_caps(device_t dev, struct dmar_unit *unit, 370 ACPI_DMAR_HARDWARE_UNIT *dmaru) 371 { 372 uint32_t caphi, ecaphi; 373 374 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 375 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 376 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 377 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 378 caphi = unit->hw_cap >> 32; 379 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 380 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 381 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 382 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 383 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 384 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 385 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 386 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 387 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 388 printf("\n"); 389 ecaphi = unit->hw_ecap >> 32; 390 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 391 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 392 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 393 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 394 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 395 DMAR_ECAP_IRO(unit->hw_ecap)); 396 } 397 398 static int 399 dmar_attach(device_t dev) 400 { 401 struct dmar_unit *unit; 402 ACPI_DMAR_HARDWARE_UNIT *dmaru; 403 int i, error; 404 405 unit = device_get_softc(dev); 406 unit->dev = dev; 407 unit->unit = device_get_unit(dev); 408 dmaru = dmar_find_by_index(unit->unit); 409 if (dmaru == NULL) 410 return (EINVAL); 411 unit->segment = dmaru->Segment; 412 unit->base = dmaru->Address; 413 unit->reg_rid = DMAR_REG_RID; 414 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 415 &unit->reg_rid, RF_ACTIVE); 416 if (unit->regs == NULL) { 417 device_printf(dev, "cannot allocate register window\n"); 418 return (ENOMEM); 419 } 420 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 421 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 422 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 423 if (bootverbose) 424 dmar_print_caps(dev, unit, dmaru); 425 dmar_quirks_post_ident(unit); 426 427 for (i = 0; i < DMAR_INTR_TOTAL; i++) 428 unit->intrs[i].irq = -1; 429 430 unit->intrs[DMAR_INTR_FAULT].name = "fault"; 431 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; 432 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; 433 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; 434 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; 435 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; 436 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr; 437 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr; 438 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT); 439 if (error != 0) { 440 dmar_release_resources(dev, unit); 441 return (error); 442 } 443 if (DMAR_HAS_QI(unit)) { 444 unit->intrs[DMAR_INTR_QI].name = "qi"; 445 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID; 446 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr; 447 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG; 448 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG; 449 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG; 450 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr; 451 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr; 452 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI); 453 if (error != 0) { 454 dmar_release_resources(dev, unit); 455 return (error); 456 } 457 } 458 459 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF); 460 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 461 &unit->lock); 462 463 /* 464 * 9.2 "Context Entry": 465 * When Caching Mode (CM) field is reported as Set, the 466 * domain-id value of zero is architecturally reserved. 467 * Software must not use domain-id value of zero 468 * when CM is Set. 469 */ 470 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 471 alloc_unr_specific(unit->domids, 0); 472 473 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 474 DMAR_CTX_CNT), 0, 0, NULL); 475 476 /* 477 * Allocate and load the root entry table pointer. Enable the 478 * address translation after the required invalidations are 479 * done. 480 */ 481 dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO); 482 DMAR_LOCK(unit); 483 error = dmar_load_root_entry_ptr(unit); 484 if (error != 0) { 485 DMAR_UNLOCK(unit); 486 dmar_release_resources(dev, unit); 487 return (error); 488 } 489 error = dmar_inv_ctx_glob(unit); 490 if (error != 0) { 491 DMAR_UNLOCK(unit); 492 dmar_release_resources(dev, unit); 493 return (error); 494 } 495 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 496 error = dmar_inv_iotlb_glob(unit); 497 if (error != 0) { 498 DMAR_UNLOCK(unit); 499 dmar_release_resources(dev, unit); 500 return (error); 501 } 502 } 503 504 DMAR_UNLOCK(unit); 505 error = dmar_init_fault_log(unit); 506 if (error != 0) { 507 dmar_release_resources(dev, unit); 508 return (error); 509 } 510 error = dmar_init_qi(unit); 511 if (error != 0) { 512 dmar_release_resources(dev, unit); 513 return (error); 514 } 515 error = dmar_init_irt(unit); 516 if (error != 0) { 517 dmar_release_resources(dev, unit); 518 return (error); 519 } 520 error = dmar_init_busdma(unit); 521 if (error != 0) { 522 dmar_release_resources(dev, unit); 523 return (error); 524 } 525 526 #ifdef NOTYET 527 DMAR_LOCK(unit); 528 error = dmar_enable_translation(unit); 529 if (error != 0) { 530 DMAR_UNLOCK(unit); 531 dmar_release_resources(dev, unit); 532 return (error); 533 } 534 DMAR_UNLOCK(unit); 535 #endif 536 537 return (0); 538 } 539 540 static int 541 dmar_detach(device_t dev) 542 { 543 544 return (EBUSY); 545 } 546 547 static int 548 dmar_suspend(device_t dev) 549 { 550 551 return (0); 552 } 553 554 static int 555 dmar_resume(device_t dev) 556 { 557 558 /* XXXKIB */ 559 return (0); 560 } 561 562 static device_method_t dmar_methods[] = { 563 DEVMETHOD(device_identify, dmar_identify), 564 DEVMETHOD(device_probe, dmar_probe), 565 DEVMETHOD(device_attach, dmar_attach), 566 DEVMETHOD(device_detach, dmar_detach), 567 DEVMETHOD(device_suspend, dmar_suspend), 568 DEVMETHOD(device_resume, dmar_resume), 569 #ifdef DEV_APIC 570 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 571 #endif 572 DEVMETHOD_END 573 }; 574 575 static driver_t dmar_driver = { 576 "dmar", 577 dmar_methods, 578 sizeof(struct dmar_unit), 579 }; 580 581 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0); 582 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 583 584 static void 585 dmar_print_path(device_t dev, const char *banner, int busno, int depth, 586 const ACPI_DMAR_PCI_PATH *path) 587 { 588 int i; 589 590 device_printf(dev, "%s [%d, ", banner, busno); 591 for (i = 0; i < depth; i++) { 592 if (i != 0) 593 printf(", "); 594 printf("(%d, %d)", path[i].Device, path[i].Function); 595 } 596 printf("]\n"); 597 } 598 599 static int 600 dmar_dev_depth(device_t child) 601 { 602 devclass_t pci_class; 603 device_t bus, pcib; 604 int depth; 605 606 pci_class = devclass_find("pci"); 607 for (depth = 1; ; depth++) { 608 bus = device_get_parent(child); 609 pcib = device_get_parent(bus); 610 if (device_get_devclass(device_get_parent(pcib)) != 611 pci_class) 612 return (depth); 613 child = pcib; 614 } 615 } 616 617 static void 618 dmar_dev_path(device_t child, int *busno, ACPI_DMAR_PCI_PATH *path, int depth) 619 { 620 devclass_t pci_class; 621 device_t bus, pcib; 622 623 pci_class = devclass_find("pci"); 624 for (depth--; depth != -1; depth--) { 625 path[depth].Device = pci_get_slot(child); 626 path[depth].Function = pci_get_function(child); 627 bus = device_get_parent(child); 628 pcib = device_get_parent(bus); 629 if (device_get_devclass(device_get_parent(pcib)) != 630 pci_class) { 631 /* reached a host bridge */ 632 *busno = pcib_get_bus(bus); 633 return; 634 } 635 child = pcib; 636 } 637 panic("wrong depth"); 638 } 639 640 static int 641 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 642 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 643 enum AcpiDmarScopeType scope_type) 644 { 645 int i, depth; 646 647 if (busno1 != busno2) 648 return (0); 649 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 650 return (0); 651 depth = depth1; 652 if (depth2 < depth) 653 depth = depth2; 654 for (i = 0; i < depth; i++) { 655 if (path1[i].Device != path2[i].Device || 656 path1[i].Function != path2[i].Function) 657 return (0); 658 } 659 return (1); 660 } 661 662 static int 663 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, device_t dev, 664 int dev_busno, const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 665 { 666 ACPI_DMAR_PCI_PATH *path; 667 int path_len; 668 669 if (devscope->Length < sizeof(*devscope)) { 670 printf("dmar_find: corrupted DMAR table, dl %d\n", 671 devscope->Length); 672 return (-1); 673 } 674 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 675 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 676 return (0); 677 path_len = devscope->Length - sizeof(*devscope); 678 if (path_len % 2 != 0) { 679 printf("dmar_find_bsf: corrupted DMAR table, dl %d\n", 680 devscope->Length); 681 return (-1); 682 } 683 path_len /= 2; 684 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 685 if (path_len == 0) { 686 printf("dmar_find: corrupted DMAR table, dl %d\n", 687 devscope->Length); 688 return (-1); 689 } 690 if (dmar_match_verbose) 691 dmar_print_path(dev, "DMAR", devscope->Bus, path_len, path); 692 693 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 694 dev_path, dev_path_len, devscope->EntryType)); 695 } 696 697 struct dmar_unit * 698 dmar_find(device_t dev) 699 { 700 device_t dmar_dev; 701 ACPI_DMAR_HARDWARE_UNIT *dmarh; 702 ACPI_DMAR_DEVICE_SCOPE *devscope; 703 char *ptr, *ptrend; 704 int i, match, dev_domain, dev_busno, dev_path_len; 705 706 dmar_dev = NULL; 707 dev_domain = pci_get_domain(dev); 708 dev_path_len = dmar_dev_depth(dev); 709 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 710 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 711 if (dmar_match_verbose) 712 dmar_print_path(dev, "PCI", dev_busno, dev_path_len, dev_path); 713 714 for (i = 0; i < dmar_devcnt; i++) { 715 if (dmar_devs[i] == NULL) 716 continue; 717 dmarh = dmar_find_by_index(i); 718 if (dmarh == NULL) 719 continue; 720 if (dmarh->Segment != dev_domain) 721 continue; 722 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 723 dmar_dev = dmar_devs[i]; 724 if (dmar_match_verbose) { 725 device_printf(dev, 726 "pci%d:%d:%d:%d matched dmar%d INCLUDE_ALL\n", 727 dev_domain, pci_get_bus(dev), 728 pci_get_slot(dev), 729 pci_get_function(dev), 730 ((struct dmar_unit *)device_get_softc( 731 dmar_dev))->unit); 732 } 733 goto found; 734 } 735 ptr = (char *)dmarh + sizeof(*dmarh); 736 ptrend = (char *)dmarh + dmarh->Header.Length; 737 for (;;) { 738 if (ptr >= ptrend) 739 break; 740 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 741 ptr += devscope->Length; 742 if (dmar_match_verbose) { 743 device_printf(dev, 744 "pci%d:%d:%d:%d matching dmar%d\n", 745 dev_domain, pci_get_bus(dev), 746 pci_get_slot(dev), 747 pci_get_function(dev), 748 ((struct dmar_unit *)device_get_softc( 749 dmar_devs[i]))->unit); 750 } 751 match = dmar_match_devscope(devscope, dev, dev_busno, 752 dev_path, dev_path_len); 753 if (dmar_match_verbose) { 754 if (match == -1) 755 printf("table error\n"); 756 else if (match == 0) 757 printf("not matched\n"); 758 else 759 printf("matched\n"); 760 } 761 if (match == -1) 762 return (NULL); 763 else if (match == 1) { 764 dmar_dev = dmar_devs[i]; 765 goto found; 766 } 767 } 768 } 769 return (NULL); 770 found: 771 return (device_get_softc(dmar_dev)); 772 } 773 774 static struct dmar_unit * 775 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 776 { 777 device_t dmar_dev; 778 struct dmar_unit *unit; 779 ACPI_DMAR_HARDWARE_UNIT *dmarh; 780 ACPI_DMAR_DEVICE_SCOPE *devscope; 781 ACPI_DMAR_PCI_PATH *path; 782 char *ptr, *ptrend; 783 int i; 784 785 for (i = 0; i < dmar_devcnt; i++) { 786 dmar_dev = dmar_devs[i]; 787 if (dmar_dev == NULL) 788 continue; 789 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 790 dmarh = dmar_find_by_index(i); 791 if (dmarh == NULL) 792 continue; 793 ptr = (char *)dmarh + sizeof(*dmarh); 794 ptrend = (char *)dmarh + dmarh->Header.Length; 795 for (;;) { 796 if (ptr >= ptrend) 797 break; 798 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 799 ptr += devscope->Length; 800 if (devscope->EntryType != entry_type) 801 continue; 802 if (devscope->EnumerationId != id) 803 continue; 804 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 805 == 2) { 806 if (rid != NULL) { 807 path = (ACPI_DMAR_PCI_PATH *) 808 (devscope + 1); 809 *rid = PCI_RID(devscope->Bus, 810 path->Device, path->Function); 811 } 812 return (unit); 813 } else { 814 /* XXXKIB */ 815 printf( 816 "dmar_find_nonpci: id %d type %d path length != 2\n", 817 id, entry_type); 818 } 819 } 820 } 821 return (NULL); 822 } 823 824 825 struct dmar_unit * 826 dmar_find_hpet(device_t dev, uint16_t *rid) 827 { 828 ACPI_HANDLE handle; 829 uint32_t hpet_id; 830 831 handle = acpi_get_handle(dev); 832 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &hpet_id))) 833 return (NULL); 834 return (dmar_find_nonpci(hpet_id, ACPI_DMAR_SCOPE_TYPE_HPET, rid)); 835 } 836 837 struct dmar_unit * 838 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 839 { 840 841 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 842 } 843 844 struct rmrr_iter_args { 845 struct dmar_ctx *ctx; 846 device_t dev; 847 int dev_domain; 848 int dev_busno; 849 ACPI_DMAR_PCI_PATH *dev_path; 850 int dev_path_len; 851 struct dmar_map_entries_tailq *rmrr_entries; 852 }; 853 854 static int 855 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 856 { 857 struct rmrr_iter_args *ria; 858 ACPI_DMAR_RESERVED_MEMORY *resmem; 859 ACPI_DMAR_DEVICE_SCOPE *devscope; 860 struct dmar_map_entry *entry; 861 char *ptr, *ptrend; 862 int match; 863 864 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 865 return (1); 866 867 ria = arg; 868 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 869 if (dmar_match_verbose) { 870 printf("RMRR [%jx,%jx] segment %d\n", 871 (uintmax_t)resmem->BaseAddress, 872 (uintmax_t)resmem->EndAddress, 873 resmem->Segment); 874 } 875 if (resmem->Segment != ria->dev_domain) 876 return (1); 877 878 ptr = (char *)resmem + sizeof(*resmem); 879 ptrend = (char *)resmem + resmem->Header.Length; 880 for (;;) { 881 if (ptr >= ptrend) 882 break; 883 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 884 ptr += devscope->Length; 885 match = dmar_match_devscope(devscope, ria->dev, ria->dev_busno, 886 ria->dev_path, ria->dev_path_len); 887 if (match == 1) { 888 if (dmar_match_verbose) 889 printf("matched\n"); 890 entry = dmar_gas_alloc_entry(ria->ctx, DMAR_PGF_WAITOK); 891 entry->start = resmem->BaseAddress; 892 /* The RMRR entry end address is inclusive. */ 893 entry->end = resmem->EndAddress; 894 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 895 unroll_link); 896 } else if (dmar_match_verbose) { 897 printf("not matched, err %d\n", match); 898 } 899 } 900 901 return (1); 902 } 903 904 void 905 dmar_ctx_parse_rmrr(struct dmar_ctx *ctx, device_t dev, 906 struct dmar_map_entries_tailq *rmrr_entries) 907 { 908 struct rmrr_iter_args ria; 909 910 ria.dev_domain = pci_get_domain(dev); 911 ria.dev_path_len = dmar_dev_depth(dev); 912 ACPI_DMAR_PCI_PATH dev_path[ria.dev_path_len]; 913 dmar_dev_path(dev, &ria.dev_busno, dev_path, ria.dev_path_len); 914 915 if (dmar_match_verbose) { 916 device_printf(dev, "parsing RMRR entries for "); 917 dmar_print_path(dev, "PCI", ria.dev_busno, ria.dev_path_len, 918 dev_path); 919 } 920 921 ria.ctx = ctx; 922 ria.dev = dev; 923 ria.dev_path = dev_path; 924 ria.rmrr_entries = rmrr_entries; 925 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 926 } 927 928 struct inst_rmrr_iter_args { 929 struct dmar_unit *dmar; 930 }; 931 932 static device_t 933 dmar_path_dev(int segment, int path_len, int busno, 934 const ACPI_DMAR_PCI_PATH *path) 935 { 936 devclass_t pci_class; 937 device_t bus, pcib, dev; 938 int i; 939 940 pci_class = devclass_find("pci"); 941 dev = NULL; 942 for (i = 0; i < path_len; i++, path++) { 943 dev = pci_find_dbsf(segment, busno, path->Device, 944 path->Function); 945 if (dev == NULL) 946 break; 947 if (i != path_len - 1) { 948 bus = device_get_parent(dev); 949 pcib = device_get_parent(bus); 950 if (device_get_devclass(device_get_parent(pcib)) != 951 pci_class) 952 return (NULL); 953 } 954 busno = pcib_get_bus(dev); 955 } 956 return (dev); 957 } 958 959 static int 960 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 961 { 962 const ACPI_DMAR_RESERVED_MEMORY *resmem; 963 const ACPI_DMAR_DEVICE_SCOPE *devscope; 964 struct inst_rmrr_iter_args *iria; 965 const char *ptr, *ptrend; 966 struct dmar_unit *dev_dmar; 967 device_t dev; 968 969 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 970 return (1); 971 972 iria = arg; 973 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 974 if (resmem->Segment != iria->dmar->segment) 975 return (1); 976 if (dmar_match_verbose) { 977 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit, 978 (uintmax_t)resmem->BaseAddress, 979 (uintmax_t)resmem->EndAddress); 980 } 981 982 ptr = (const char *)resmem + sizeof(*resmem); 983 ptrend = (const char *)resmem + resmem->Header.Length; 984 for (;;) { 985 if (ptr >= ptrend) 986 break; 987 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 988 ptr += devscope->Length; 989 /* XXXKIB bridge */ 990 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 991 continue; 992 if (dmar_match_verbose) { 993 dmar_print_path(iria->dmar->dev, "RMRR scope", 994 devscope->Bus, (devscope->Length - 995 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, 996 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 997 } 998 dev = dmar_path_dev(resmem->Segment, (devscope->Length - 999 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, devscope->Bus, 1000 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1001 if (dev == NULL) { 1002 if (dmar_match_verbose) 1003 printf("null dev\n"); 1004 continue; 1005 } 1006 dev_dmar = dmar_find(dev); 1007 if (dev_dmar != iria->dmar) { 1008 if (dmar_match_verbose) { 1009 printf("dmar%d matched, skipping\n", 1010 dev_dmar->unit); 1011 } 1012 continue; 1013 } 1014 if (dmar_match_verbose) 1015 printf("matched, instantiating RMRR context\n"); 1016 dmar_instantiate_ctx(iria->dmar, dev, true); 1017 } 1018 1019 return (1); 1020 1021 } 1022 1023 /* 1024 * Pre-create all contexts for the DMAR which have RMRR entries. 1025 */ 1026 int 1027 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar) 1028 { 1029 struct inst_rmrr_iter_args iria; 1030 int error; 1031 1032 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1033 return (0); 1034 1035 error = 0; 1036 iria.dmar = dmar; 1037 if (dmar_match_verbose) 1038 printf("dmar%d: instantiating RMRR contexts\n", dmar->unit); 1039 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1040 DMAR_LOCK(dmar); 1041 if (!LIST_EMPTY(&dmar->contexts)) { 1042 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1043 ("dmar%d: RMRR not handled but translation is already enabled", 1044 dmar->unit)); 1045 error = dmar_enable_translation(dmar); 1046 } 1047 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1048 return (error); 1049 } 1050 1051 #ifdef DDB 1052 #include <ddb/ddb.h> 1053 #include <ddb/db_lex.h> 1054 1055 static void 1056 dmar_print_ctx_entry(const struct dmar_map_entry *entry) 1057 { 1058 struct dmar_map_entry *l, *r; 1059 1060 db_printf( 1061 " start %jx end %jx free_after %jx free_down %jx flags %x ", 1062 entry->start, entry->end, entry->free_after, entry->free_down, 1063 entry->flags); 1064 db_printf("left "); 1065 l = RB_LEFT(entry, rb_entry); 1066 if (l == NULL) 1067 db_printf("NULL "); 1068 else 1069 db_printf("%jx ", l->start); 1070 db_printf("right "); 1071 r = RB_RIGHT(entry, rb_entry); 1072 if (r == NULL) 1073 db_printf("NULL"); 1074 else 1075 db_printf("%jx", r->start); 1076 db_printf("\n"); 1077 } 1078 1079 static void 1080 dmar_print_ctx(struct dmar_ctx *ctx, bool show_mappings) 1081 { 1082 struct dmar_map_entry *entry; 1083 1084 db_printf( 1085 " @%p pci%d:%d:%d dom %d mgaw %d agaw %d pglvl %d end %jx\n" 1086 " refs %d flags %x pgobj %p map_ents %u loads %lu unloads %lu\n", 1087 ctx, pci_get_bus(ctx->ctx_tag.owner), 1088 pci_get_slot(ctx->ctx_tag.owner), 1089 pci_get_function(ctx->ctx_tag.owner), ctx->domain, ctx->mgaw, 1090 ctx->agaw, ctx->pglvl, (uintmax_t)ctx->end, ctx->refs, 1091 ctx->flags, ctx->pgtbl_obj, ctx->entries_cnt, ctx->loads, 1092 ctx->unloads); 1093 if (!show_mappings) 1094 return; 1095 db_printf(" mapped:\n"); 1096 RB_FOREACH(entry, dmar_gas_entries_tree, &ctx->rb_root) { 1097 dmar_print_ctx_entry(entry); 1098 if (db_pager_quit) 1099 break; 1100 } 1101 if (db_pager_quit) 1102 return; 1103 db_printf(" unloading:\n"); 1104 TAILQ_FOREACH(entry, &ctx->unload_entries, dmamap_link) { 1105 dmar_print_ctx_entry(entry); 1106 if (db_pager_quit) 1107 break; 1108 } 1109 } 1110 1111 DB_FUNC(dmar_ctx, db_dmar_print_ctx, db_show_table, CS_OWN, NULL) 1112 { 1113 struct dmar_unit *unit; 1114 struct dmar_ctx *ctx; 1115 bool show_mappings, valid; 1116 int domain, bus, device, function, i, t; 1117 db_expr_t radix; 1118 1119 valid = false; 1120 radix = db_radix; 1121 db_radix = 10; 1122 t = db_read_token(); 1123 if (t == tSLASH) { 1124 t = db_read_token(); 1125 if (t != tIDENT) { 1126 db_printf("Bad modifier\n"); 1127 db_radix = radix; 1128 db_skip_to_eol(); 1129 return; 1130 } 1131 show_mappings = strchr(db_tok_string, 'm') != NULL; 1132 t = db_read_token(); 1133 } else { 1134 show_mappings = false; 1135 } 1136 if (t == tNUMBER) { 1137 domain = db_tok_number; 1138 t = db_read_token(); 1139 if (t == tNUMBER) { 1140 bus = db_tok_number; 1141 t = db_read_token(); 1142 if (t == tNUMBER) { 1143 device = db_tok_number; 1144 t = db_read_token(); 1145 if (t == tNUMBER) { 1146 function = db_tok_number; 1147 valid = true; 1148 } 1149 } 1150 } 1151 } 1152 db_radix = radix; 1153 db_skip_to_eol(); 1154 if (!valid) { 1155 db_printf("usage: show dmar_ctx [/m] " 1156 "<domain> <bus> <device> <func>\n"); 1157 return; 1158 } 1159 for (i = 0; i < dmar_devcnt; i++) { 1160 unit = device_get_softc(dmar_devs[i]); 1161 LIST_FOREACH(ctx, &unit->contexts, link) { 1162 if (domain == unit->segment && 1163 bus == pci_get_bus(ctx->ctx_tag.owner) && 1164 device == pci_get_slot(ctx->ctx_tag.owner) && 1165 function == pci_get_function(ctx->ctx_tag.owner)) { 1166 dmar_print_ctx(ctx, show_mappings); 1167 goto out; 1168 } 1169 } 1170 } 1171 out:; 1172 } 1173 1174 static void 1175 dmar_print_one(int idx, bool show_ctxs, bool show_mappings) 1176 { 1177 struct dmar_unit *unit; 1178 struct dmar_ctx *ctx; 1179 int i, frir; 1180 1181 unit = device_get_softc(dmar_devs[idx]); 1182 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit, 1183 dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG)); 1184 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1185 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1186 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1187 dmar_read4(unit, DMAR_GSTS_REG), 1188 dmar_read4(unit, DMAR_FSTS_REG), 1189 dmar_read4(unit, DMAR_FECTL_REG)); 1190 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1191 dmar_read4(unit, DMAR_FEDATA_REG), 1192 dmar_read4(unit, DMAR_FEADDR_REG), 1193 dmar_read4(unit, DMAR_FEUADDR_REG)); 1194 db_printf("primary fault log:\n"); 1195 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1196 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1197 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1198 (uintmax_t)dmar_read8(unit, frir), 1199 (uintmax_t)dmar_read8(unit, frir + 8)); 1200 } 1201 if (DMAR_HAS_QI(unit)) { 1202 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1203 dmar_read4(unit, DMAR_IEDATA_REG), 1204 dmar_read4(unit, DMAR_IEADDR_REG), 1205 dmar_read4(unit, DMAR_IEUADDR_REG)); 1206 if (unit->qi_enabled) { 1207 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1208 "size 0x%jx\n" 1209 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1210 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1211 (uintmax_t)unit->inv_queue, 1212 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1213 (uintmax_t)unit->inv_queue_size, 1214 dmar_read4(unit, DMAR_IQH_REG), 1215 dmar_read4(unit, DMAR_IQT_REG), 1216 unit->inv_queue_avail, 1217 dmar_read4(unit, DMAR_ICS_REG), 1218 dmar_read4(unit, DMAR_IECTL_REG), 1219 unit->inv_waitd_seq_hw, 1220 &unit->inv_waitd_seq_hw, 1221 (uintmax_t)unit->inv_waitd_seq_hw_phys, 1222 unit->inv_waitd_seq, 1223 unit->inv_waitd_gen); 1224 } else { 1225 db_printf("qi is disabled\n"); 1226 } 1227 } 1228 if (show_ctxs) { 1229 db_printf("contexts:\n"); 1230 LIST_FOREACH(ctx, &unit->contexts, link) { 1231 dmar_print_ctx(ctx, show_mappings); 1232 if (db_pager_quit) 1233 break; 1234 } 1235 } 1236 } 1237 1238 DB_SHOW_COMMAND(dmar, db_dmar_print) 1239 { 1240 bool show_ctxs, show_mappings; 1241 1242 show_ctxs = strchr(modif, 'c') != NULL; 1243 show_mappings = strchr(modif, 'm') != NULL; 1244 if (!have_addr) { 1245 db_printf("usage: show dmar [/c] [/m] index\n"); 1246 return; 1247 } 1248 dmar_print_one((int)addr, show_ctxs, show_mappings); 1249 } 1250 1251 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1252 { 1253 int i; 1254 bool show_ctxs, show_mappings; 1255 1256 show_ctxs = strchr(modif, 'c') != NULL; 1257 show_mappings = strchr(modif, 'm') != NULL; 1258 1259 for (i = 0; i < dmar_devcnt; i++) { 1260 dmar_print_one(i, show_ctxs, show_mappings); 1261 if (db_pager_quit) 1262 break; 1263 } 1264 } 1265 #endif 1266