xref: /freebsd/sys/x86/iommu/intel_drv.c (revision 2f513db72b034fd5ef7f080b11be5c711c15186a)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2013-2015 The FreeBSD Foundation
5  * All rights reserved.
6  *
7  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
8  * under sponsorship from the FreeBSD Foundation.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34 
35 #include "opt_acpi.h"
36 #if defined(__amd64__)
37 #define	DEV_APIC
38 #else
39 #include "opt_apic.h"
40 #endif
41 #include "opt_ddb.h"
42 
43 #include <sys/param.h>
44 #include <sys/bus.h>
45 #include <sys/kernel.h>
46 #include <sys/lock.h>
47 #include <sys/malloc.h>
48 #include <sys/memdesc.h>
49 #include <sys/module.h>
50 #include <sys/mutex.h>
51 #include <sys/rman.h>
52 #include <sys/rwlock.h>
53 #include <sys/smp.h>
54 #include <sys/taskqueue.h>
55 #include <sys/tree.h>
56 #include <sys/vmem.h>
57 #include <machine/bus.h>
58 #include <machine/pci_cfgreg.h>
59 #include <contrib/dev/acpica/include/acpi.h>
60 #include <contrib/dev/acpica/include/accommon.h>
61 #include <dev/acpica/acpivar.h>
62 #include <vm/vm.h>
63 #include <vm/vm_extern.h>
64 #include <vm/vm_kern.h>
65 #include <vm/vm_object.h>
66 #include <vm/vm_page.h>
67 #include <vm/vm_pager.h>
68 #include <vm/vm_map.h>
69 #include <x86/include/busdma_impl.h>
70 #include <x86/iommu/intel_reg.h>
71 #include <x86/iommu/busdma_dmar.h>
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
74 #include <x86/iommu/intel_dmar.h>
75 
76 #ifdef DEV_APIC
77 #include "pcib_if.h"
78 #include <machine/intr_machdep.h>
79 #include <x86/apicreg.h>
80 #include <x86/apicvar.h>
81 #endif
82 
83 #define	DMAR_FAULT_IRQ_RID	0
84 #define	DMAR_QI_IRQ_RID		1
85 #define	DMAR_REG_RID		2
86 
87 static devclass_t dmar_devclass;
88 static device_t *dmar_devs;
89 static int dmar_devcnt;
90 
91 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
92 
93 static void
94 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
95 {
96 	ACPI_TABLE_DMAR *dmartbl;
97 	ACPI_DMAR_HEADER *dmarh;
98 	char *ptr, *ptrend;
99 	ACPI_STATUS status;
100 
101 	status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
102 	if (ACPI_FAILURE(status))
103 		return;
104 	ptr = (char *)dmartbl + sizeof(*dmartbl);
105 	ptrend = (char *)dmartbl + dmartbl->Header.Length;
106 	for (;;) {
107 		if (ptr >= ptrend)
108 			break;
109 		dmarh = (ACPI_DMAR_HEADER *)ptr;
110 		if (dmarh->Length <= 0) {
111 			printf("dmar_identify: corrupted DMAR table, l %d\n",
112 			    dmarh->Length);
113 			break;
114 		}
115 		ptr += dmarh->Length;
116 		if (!iter(dmarh, arg))
117 			break;
118 	}
119 	AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
120 }
121 
122 struct find_iter_args {
123 	int i;
124 	ACPI_DMAR_HARDWARE_UNIT *res;
125 };
126 
127 static int
128 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
129 {
130 	struct find_iter_args *fia;
131 
132 	if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
133 		return (1);
134 
135 	fia = arg;
136 	if (fia->i == 0) {
137 		fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
138 		return (0);
139 	}
140 	fia->i--;
141 	return (1);
142 }
143 
144 static ACPI_DMAR_HARDWARE_UNIT *
145 dmar_find_by_index(int idx)
146 {
147 	struct find_iter_args fia;
148 
149 	fia.i = idx;
150 	fia.res = NULL;
151 	dmar_iterate_tbl(dmar_find_iter, &fia);
152 	return (fia.res);
153 }
154 
155 static int
156 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
157 {
158 
159 	if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
160 		dmar_devcnt++;
161 	return (1);
162 }
163 
164 static int dmar_enable = 0;
165 static void
166 dmar_identify(driver_t *driver, device_t parent)
167 {
168 	ACPI_TABLE_DMAR *dmartbl;
169 	ACPI_DMAR_HARDWARE_UNIT *dmarh;
170 	ACPI_STATUS status;
171 	int i, error;
172 
173 	if (acpi_disabled("dmar"))
174 		return;
175 	TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
176 	if (!dmar_enable)
177 		return;
178 #ifdef INVARIANTS
179 	TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free);
180 #endif
181 	status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
182 	if (ACPI_FAILURE(status))
183 		return;
184 	haw = dmartbl->Width + 1;
185 	if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
186 		dmar_high = BUS_SPACE_MAXADDR;
187 	else
188 		dmar_high = 1ULL << (haw + 1);
189 	if (bootverbose) {
190 		printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
191 		    (unsigned)dmartbl->Flags,
192 		    "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
193 	}
194 	AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
195 
196 	dmar_iterate_tbl(dmar_count_iter, NULL);
197 	if (dmar_devcnt == 0)
198 		return;
199 	dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
200 	    M_WAITOK | M_ZERO);
201 	for (i = 0; i < dmar_devcnt; i++) {
202 		dmarh = dmar_find_by_index(i);
203 		if (dmarh == NULL) {
204 			printf("dmar_identify: cannot find HWUNIT %d\n", i);
205 			continue;
206 		}
207 		dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
208 		if (dmar_devs[i] == NULL) {
209 			printf("dmar_identify: cannot create instance %d\n", i);
210 			continue;
211 		}
212 		error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
213 		    DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
214 		if (error != 0) {
215 			printf(
216 	"dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
217 			    i, (uintmax_t)dmarh->Address, error);
218 			device_delete_child(parent, dmar_devs[i]);
219 			dmar_devs[i] = NULL;
220 		}
221 	}
222 }
223 
224 static int
225 dmar_probe(device_t dev)
226 {
227 
228 	if (acpi_get_handle(dev) != NULL)
229 		return (ENXIO);
230 	device_set_desc(dev, "DMA remap");
231 	return (BUS_PROBE_NOWILDCARD);
232 }
233 
234 static void
235 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
236 {
237 	struct dmar_msi_data *dmd;
238 
239 	dmd = &unit->intrs[idx];
240 	if (dmd->irq == -1)
241 		return;
242 	bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
243 	bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
244 	bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
245 	PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
246 	    dev, dmd->irq);
247 	dmd->irq = -1;
248 }
249 
250 static void
251 dmar_release_resources(device_t dev, struct dmar_unit *unit)
252 {
253 	int i;
254 
255 	dmar_fini_busdma(unit);
256 	dmar_fini_irt(unit);
257 	dmar_fini_qi(unit);
258 	dmar_fini_fault_log(unit);
259 	for (i = 0; i < DMAR_INTR_TOTAL; i++)
260 		dmar_release_intr(dev, unit, i);
261 	if (unit->regs != NULL) {
262 		bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
263 		    unit->regs);
264 		bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
265 		    unit->regs);
266 		unit->regs = NULL;
267 	}
268 	if (unit->domids != NULL) {
269 		delete_unrhdr(unit->domids);
270 		unit->domids = NULL;
271 	}
272 	if (unit->ctx_obj != NULL) {
273 		vm_object_deallocate(unit->ctx_obj);
274 		unit->ctx_obj = NULL;
275 	}
276 }
277 
278 static int
279 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
280 {
281 	device_t pcib;
282 	struct dmar_msi_data *dmd;
283 	uint64_t msi_addr;
284 	uint32_t msi_data;
285 	int error;
286 
287 	dmd = &unit->intrs[idx];
288 	pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
289 	error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
290 	if (error != 0) {
291 		device_printf(dev, "cannot allocate %s interrupt, %d\n",
292 		    dmd->name, error);
293 		goto err1;
294 	}
295 	error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
296 	    dmd->irq, 1);
297 	if (error != 0) {
298 		device_printf(dev, "cannot set %s interrupt resource, %d\n",
299 		    dmd->name, error);
300 		goto err2;
301 	}
302 	dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
303 	    &dmd->irq_rid, RF_ACTIVE);
304 	if (dmd->irq_res == NULL) {
305 		device_printf(dev,
306 		    "cannot allocate resource for %s interrupt\n", dmd->name);
307 		error = ENXIO;
308 		goto err3;
309 	}
310 	error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
311 	    dmd->handler, NULL, unit, &dmd->intr_handle);
312 	if (error != 0) {
313 		device_printf(dev, "cannot setup %s interrupt, %d\n",
314 		    dmd->name, error);
315 		goto err4;
316 	}
317 	bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
318 	error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
319 	if (error != 0) {
320 		device_printf(dev, "cannot map %s interrupt, %d\n",
321 		    dmd->name, error);
322 		goto err5;
323 	}
324 	dmar_write4(unit, dmd->msi_data_reg, msi_data);
325 	dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
326 	/* Only for xAPIC mode */
327 	dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
328 	return (0);
329 
330 err5:
331 	bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
332 err4:
333 	bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
334 err3:
335 	bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
336 err2:
337 	PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
338 	dmd->irq = -1;
339 err1:
340 	return (error);
341 }
342 
343 #ifdef DEV_APIC
344 static int
345 dmar_remap_intr(device_t dev, device_t child, u_int irq)
346 {
347 	struct dmar_unit *unit;
348 	struct dmar_msi_data *dmd;
349 	uint64_t msi_addr;
350 	uint32_t msi_data;
351 	int i, error;
352 
353 	unit = device_get_softc(dev);
354 	for (i = 0; i < DMAR_INTR_TOTAL; i++) {
355 		dmd = &unit->intrs[i];
356 		if (irq == dmd->irq) {
357 			error = PCIB_MAP_MSI(device_get_parent(
358 			    device_get_parent(dev)),
359 			    dev, irq, &msi_addr, &msi_data);
360 			if (error != 0)
361 				return (error);
362 			DMAR_LOCK(unit);
363 			(dmd->disable_intr)(unit);
364 			dmar_write4(unit, dmd->msi_data_reg, msi_data);
365 			dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
366 			dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
367 			(dmd->enable_intr)(unit);
368 			DMAR_UNLOCK(unit);
369 			return (0);
370 		}
371 	}
372 	return (ENOENT);
373 }
374 #endif
375 
376 static void
377 dmar_print_caps(device_t dev, struct dmar_unit *unit,
378     ACPI_DMAR_HARDWARE_UNIT *dmaru)
379 {
380 	uint32_t caphi, ecaphi;
381 
382 	device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
383 	    (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
384 	    DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
385 	    dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
386 	caphi = unit->hw_cap >> 32;
387 	device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
388 	    "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
389 	printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
390 	printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
391 	    DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
392 	    DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
393 	    DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
394 	if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
395 		printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
396 	printf("\n");
397 	ecaphi = unit->hw_ecap >> 32;
398 	device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
399 	    "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
400 	    "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
401 	printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
402 	printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
403 	    DMAR_ECAP_IRO(unit->hw_ecap));
404 }
405 
406 static int
407 dmar_attach(device_t dev)
408 {
409 	struct dmar_unit *unit;
410 	ACPI_DMAR_HARDWARE_UNIT *dmaru;
411 	uint64_t timeout;
412 	int i, error;
413 
414 	unit = device_get_softc(dev);
415 	unit->dev = dev;
416 	unit->unit = device_get_unit(dev);
417 	dmaru = dmar_find_by_index(unit->unit);
418 	if (dmaru == NULL)
419 		return (EINVAL);
420 	unit->segment = dmaru->Segment;
421 	unit->base = dmaru->Address;
422 	unit->reg_rid = DMAR_REG_RID;
423 	unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
424 	    &unit->reg_rid, RF_ACTIVE);
425 	if (unit->regs == NULL) {
426 		device_printf(dev, "cannot allocate register window\n");
427 		return (ENOMEM);
428 	}
429 	unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
430 	unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
431 	unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
432 	if (bootverbose)
433 		dmar_print_caps(dev, unit, dmaru);
434 	dmar_quirks_post_ident(unit);
435 
436 	timeout = dmar_get_timeout();
437 	TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout);
438 	dmar_update_timeout(timeout);
439 
440 	for (i = 0; i < DMAR_INTR_TOTAL; i++)
441 		unit->intrs[i].irq = -1;
442 
443 	unit->intrs[DMAR_INTR_FAULT].name = "fault";
444 	unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
445 	unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
446 	unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
447 	unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
448 	unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
449 	unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
450 	unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
451 	error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
452 	if (error != 0) {
453 		dmar_release_resources(dev, unit);
454 		return (error);
455 	}
456 	if (DMAR_HAS_QI(unit)) {
457 		unit->intrs[DMAR_INTR_QI].name = "qi";
458 		unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
459 		unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
460 		unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
461 		unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
462 		unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
463 		unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
464 		unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
465 		error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
466 		if (error != 0) {
467 			dmar_release_resources(dev, unit);
468 			return (error);
469 		}
470 	}
471 
472 	mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
473 	unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
474 	    &unit->lock);
475 	LIST_INIT(&unit->domains);
476 
477 	/*
478 	 * 9.2 "Context Entry":
479 	 * When Caching Mode (CM) field is reported as Set, the
480 	 * domain-id value of zero is architecturally reserved.
481 	 * Software must not use domain-id value of zero
482 	 * when CM is Set.
483 	 */
484 	if ((unit->hw_cap & DMAR_CAP_CM) != 0)
485 		alloc_unr_specific(unit->domids, 0);
486 
487 	unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
488 	    DMAR_CTX_CNT), 0, 0, NULL);
489 
490 	/*
491 	 * Allocate and load the root entry table pointer.  Enable the
492 	 * address translation after the required invalidations are
493 	 * done.
494 	 */
495 	dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO);
496 	DMAR_LOCK(unit);
497 	error = dmar_load_root_entry_ptr(unit);
498 	if (error != 0) {
499 		DMAR_UNLOCK(unit);
500 		dmar_release_resources(dev, unit);
501 		return (error);
502 	}
503 	error = dmar_inv_ctx_glob(unit);
504 	if (error != 0) {
505 		DMAR_UNLOCK(unit);
506 		dmar_release_resources(dev, unit);
507 		return (error);
508 	}
509 	if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
510 		error = dmar_inv_iotlb_glob(unit);
511 		if (error != 0) {
512 			DMAR_UNLOCK(unit);
513 			dmar_release_resources(dev, unit);
514 			return (error);
515 		}
516 	}
517 
518 	DMAR_UNLOCK(unit);
519 	error = dmar_init_fault_log(unit);
520 	if (error != 0) {
521 		dmar_release_resources(dev, unit);
522 		return (error);
523 	}
524 	error = dmar_init_qi(unit);
525 	if (error != 0) {
526 		dmar_release_resources(dev, unit);
527 		return (error);
528 	}
529 	error = dmar_init_irt(unit);
530 	if (error != 0) {
531 		dmar_release_resources(dev, unit);
532 		return (error);
533 	}
534 	error = dmar_init_busdma(unit);
535 	if (error != 0) {
536 		dmar_release_resources(dev, unit);
537 		return (error);
538 	}
539 
540 #ifdef NOTYET
541 	DMAR_LOCK(unit);
542 	error = dmar_enable_translation(unit);
543 	if (error != 0) {
544 		DMAR_UNLOCK(unit);
545 		dmar_release_resources(dev, unit);
546 		return (error);
547 	}
548 	DMAR_UNLOCK(unit);
549 #endif
550 
551 	return (0);
552 }
553 
554 static int
555 dmar_detach(device_t dev)
556 {
557 
558 	return (EBUSY);
559 }
560 
561 static int
562 dmar_suspend(device_t dev)
563 {
564 
565 	return (0);
566 }
567 
568 static int
569 dmar_resume(device_t dev)
570 {
571 
572 	/* XXXKIB */
573 	return (0);
574 }
575 
576 static device_method_t dmar_methods[] = {
577 	DEVMETHOD(device_identify, dmar_identify),
578 	DEVMETHOD(device_probe, dmar_probe),
579 	DEVMETHOD(device_attach, dmar_attach),
580 	DEVMETHOD(device_detach, dmar_detach),
581 	DEVMETHOD(device_suspend, dmar_suspend),
582 	DEVMETHOD(device_resume, dmar_resume),
583 #ifdef DEV_APIC
584 	DEVMETHOD(bus_remap_intr, dmar_remap_intr),
585 #endif
586 	DEVMETHOD_END
587 };
588 
589 static driver_t	dmar_driver = {
590 	"dmar",
591 	dmar_methods,
592 	sizeof(struct dmar_unit),
593 };
594 
595 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
596 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
597 
598 void
599 dmar_set_buswide_ctx(struct dmar_unit *unit, u_int busno)
600 {
601 
602 	MPASS(busno <= PCI_BUSMAX);
603 	DMAR_LOCK(unit);
604 	unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
605 	    1 << (busno % (NBBY * sizeof(uint32_t)));
606 	DMAR_UNLOCK(unit);
607 }
608 
609 bool
610 dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno)
611 {
612 
613 	MPASS(busno <= PCI_BUSMAX);
614 	return ((unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] &
615 	    (1U << (busno % (NBBY * sizeof(uint32_t))))) != 0);
616 }
617 
618 static void
619 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
620 {
621 	int i;
622 
623 	printf("[%d, ", busno);
624 	for (i = 0; i < depth; i++) {
625 		if (i != 0)
626 			printf(", ");
627 		printf("(%d, %d)", path[i].Device, path[i].Function);
628 	}
629 	printf("]");
630 }
631 
632 int
633 dmar_dev_depth(device_t child)
634 {
635 	devclass_t pci_class;
636 	device_t bus, pcib;
637 	int depth;
638 
639 	pci_class = devclass_find("pci");
640 	for (depth = 1; ; depth++) {
641 		bus = device_get_parent(child);
642 		pcib = device_get_parent(bus);
643 		if (device_get_devclass(device_get_parent(pcib)) !=
644 		    pci_class)
645 			return (depth);
646 		child = pcib;
647 	}
648 }
649 
650 void
651 dmar_dev_path(device_t child, int *busno, void *path1, int depth)
652 {
653 	devclass_t pci_class;
654 	device_t bus, pcib;
655 	ACPI_DMAR_PCI_PATH *path;
656 
657 	pci_class = devclass_find("pci");
658 	path = path1;
659 	for (depth--; depth != -1; depth--) {
660 		path[depth].Device = pci_get_slot(child);
661 		path[depth].Function = pci_get_function(child);
662 		bus = device_get_parent(child);
663 		pcib = device_get_parent(bus);
664 		if (device_get_devclass(device_get_parent(pcib)) !=
665 		    pci_class) {
666 			/* reached a host bridge */
667 			*busno = pcib_get_bus(bus);
668 			return;
669 		}
670 		child = pcib;
671 	}
672 	panic("wrong depth");
673 }
674 
675 static int
676 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
677     int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
678     enum AcpiDmarScopeType scope_type)
679 {
680 	int i, depth;
681 
682 	if (busno1 != busno2)
683 		return (0);
684 	if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
685 		return (0);
686 	depth = depth1;
687 	if (depth2 < depth)
688 		depth = depth2;
689 	for (i = 0; i < depth; i++) {
690 		if (path1[i].Device != path2[i].Device ||
691 		    path1[i].Function != path2[i].Function)
692 			return (0);
693 	}
694 	return (1);
695 }
696 
697 static int
698 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno,
699     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
700 {
701 	ACPI_DMAR_PCI_PATH *path;
702 	int path_len;
703 
704 	if (devscope->Length < sizeof(*devscope)) {
705 		printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
706 		    devscope->Length);
707 		return (-1);
708 	}
709 	if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
710 	    devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
711 		return (0);
712 	path_len = devscope->Length - sizeof(*devscope);
713 	if (path_len % 2 != 0) {
714 		printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
715 		    devscope->Length);
716 		return (-1);
717 	}
718 	path_len /= 2;
719 	path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
720 	if (path_len == 0) {
721 		printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
722 		    devscope->Length);
723 		return (-1);
724 	}
725 
726 	return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
727 	    dev_path, dev_path_len, devscope->EntryType));
728 }
729 
730 static bool
731 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno,
732     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner)
733 {
734 	ACPI_DMAR_HARDWARE_UNIT *dmarh;
735 	ACPI_DMAR_DEVICE_SCOPE *devscope;
736 	char *ptr, *ptrend;
737 	int match;
738 
739 	dmarh = dmar_find_by_index(unit->unit);
740 	if (dmarh == NULL)
741 		return (false);
742 	if (dmarh->Segment != dev_domain)
743 		return (false);
744 	if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
745 		if (banner != NULL)
746 			*banner = "INCLUDE_ALL";
747 		return (true);
748 	}
749 	ptr = (char *)dmarh + sizeof(*dmarh);
750 	ptrend = (char *)dmarh + dmarh->Header.Length;
751 	while (ptr < ptrend) {
752 		devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
753 		ptr += devscope->Length;
754 		match = dmar_match_devscope(devscope, dev_busno, dev_path,
755 		    dev_path_len);
756 		if (match == -1)
757 			return (false);
758 		if (match == 1) {
759 			if (banner != NULL)
760 				*banner = "specific match";
761 			return (true);
762 		}
763 	}
764 	return (false);
765 }
766 
767 static struct dmar_unit *
768 dmar_find_by_scope(int dev_domain, int dev_busno,
769     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
770 {
771 	struct dmar_unit *unit;
772 	int i;
773 
774 	for (i = 0; i < dmar_devcnt; i++) {
775 		if (dmar_devs[i] == NULL)
776 			continue;
777 		unit = device_get_softc(dmar_devs[i]);
778 		if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path,
779 		    dev_path_len, NULL))
780 			return (unit);
781 	}
782 	return (NULL);
783 }
784 
785 struct dmar_unit *
786 dmar_find(device_t dev, bool verbose)
787 {
788 	device_t dmar_dev;
789 	struct dmar_unit *unit;
790 	const char *banner;
791 	int i, dev_domain, dev_busno, dev_path_len;
792 
793 	/*
794 	 * This function can only handle PCI(e) devices.
795 	 */
796 	if (device_get_devclass(device_get_parent(dev)) !=
797 	    devclass_find("pci"))
798 		return (NULL);
799 
800 	dmar_dev = NULL;
801 	dev_domain = pci_get_domain(dev);
802 	dev_path_len = dmar_dev_depth(dev);
803 	ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
804 	dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
805 	banner = "";
806 
807 	for (i = 0; i < dmar_devcnt; i++) {
808 		if (dmar_devs[i] == NULL)
809 			continue;
810 		unit = device_get_softc(dmar_devs[i]);
811 		if (dmar_match_by_path(unit, dev_domain, dev_busno,
812 		    dev_path, dev_path_len, &banner))
813 			break;
814 	}
815 	if (i == dmar_devcnt)
816 		return (NULL);
817 
818 	if (verbose) {
819 		device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s",
820 		    dev_domain, pci_get_bus(dev), pci_get_slot(dev),
821 		    pci_get_function(dev), unit->unit, banner);
822 		printf(" scope path ");
823 		dmar_print_path(dev_busno, dev_path_len, dev_path);
824 		printf("\n");
825 	}
826 	return (unit);
827 }
828 
829 static struct dmar_unit *
830 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
831 {
832 	device_t dmar_dev;
833 	struct dmar_unit *unit;
834 	ACPI_DMAR_HARDWARE_UNIT *dmarh;
835 	ACPI_DMAR_DEVICE_SCOPE *devscope;
836 	ACPI_DMAR_PCI_PATH *path;
837 	char *ptr, *ptrend;
838 #ifdef DEV_APIC
839 	int error;
840 #endif
841 	int i;
842 
843 	for (i = 0; i < dmar_devcnt; i++) {
844 		dmar_dev = dmar_devs[i];
845 		if (dmar_dev == NULL)
846 			continue;
847 		unit = (struct dmar_unit *)device_get_softc(dmar_dev);
848 		dmarh = dmar_find_by_index(i);
849 		if (dmarh == NULL)
850 			continue;
851 		ptr = (char *)dmarh + sizeof(*dmarh);
852 		ptrend = (char *)dmarh + dmarh->Header.Length;
853 		for (;;) {
854 			if (ptr >= ptrend)
855 				break;
856 			devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
857 			ptr += devscope->Length;
858 			if (devscope->EntryType != entry_type)
859 				continue;
860 			if (devscope->EnumerationId != id)
861 				continue;
862 #ifdef DEV_APIC
863 			if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
864 				error = ioapic_get_rid(id, rid);
865 				/*
866 				 * If our IOAPIC has PCI bindings then
867 				 * use the PCI device rid.
868 				 */
869 				if (error == 0)
870 					return (unit);
871 			}
872 #endif
873 			if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
874 			    == 2) {
875 				if (rid != NULL) {
876 					path = (ACPI_DMAR_PCI_PATH *)
877 					    (devscope + 1);
878 					*rid = PCI_RID(devscope->Bus,
879 					    path->Device, path->Function);
880 				}
881 				return (unit);
882 			}
883 			printf(
884 		           "dmar_find_nonpci: id %d type %d path length != 2\n",
885 			    id, entry_type);
886 			break;
887 		}
888 	}
889 	return (NULL);
890 }
891 
892 
893 struct dmar_unit *
894 dmar_find_hpet(device_t dev, uint16_t *rid)
895 {
896 
897 	return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
898 	    rid));
899 }
900 
901 struct dmar_unit *
902 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
903 {
904 
905 	return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
906 }
907 
908 struct rmrr_iter_args {
909 	struct dmar_domain *domain;
910 	int dev_domain;
911 	int dev_busno;
912 	const ACPI_DMAR_PCI_PATH *dev_path;
913 	int dev_path_len;
914 	struct dmar_map_entries_tailq *rmrr_entries;
915 };
916 
917 static int
918 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
919 {
920 	struct rmrr_iter_args *ria;
921 	ACPI_DMAR_RESERVED_MEMORY *resmem;
922 	ACPI_DMAR_DEVICE_SCOPE *devscope;
923 	struct dmar_map_entry *entry;
924 	char *ptr, *ptrend;
925 	int match;
926 
927 	if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
928 		return (1);
929 
930 	ria = arg;
931 	resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
932 	if (resmem->Segment != ria->dev_domain)
933 		return (1);
934 
935 	ptr = (char *)resmem + sizeof(*resmem);
936 	ptrend = (char *)resmem + resmem->Header.Length;
937 	for (;;) {
938 		if (ptr >= ptrend)
939 			break;
940 		devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
941 		ptr += devscope->Length;
942 		match = dmar_match_devscope(devscope, ria->dev_busno,
943 		    ria->dev_path, ria->dev_path_len);
944 		if (match == 1) {
945 			entry = dmar_gas_alloc_entry(ria->domain,
946 			    DMAR_PGF_WAITOK);
947 			entry->start = resmem->BaseAddress;
948 			/* The RMRR entry end address is inclusive. */
949 			entry->end = resmem->EndAddress;
950 			TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
951 			    unroll_link);
952 		}
953 	}
954 
955 	return (1);
956 }
957 
958 void
959 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno,
960     const void *dev_path, int dev_path_len,
961     struct dmar_map_entries_tailq *rmrr_entries)
962 {
963 	struct rmrr_iter_args ria;
964 
965 	ria.domain = domain;
966 	ria.dev_domain = dev_domain;
967 	ria.dev_busno = dev_busno;
968 	ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path;
969 	ria.dev_path_len = dev_path_len;
970 	ria.rmrr_entries = rmrr_entries;
971 	dmar_iterate_tbl(dmar_rmrr_iter, &ria);
972 }
973 
974 struct inst_rmrr_iter_args {
975 	struct dmar_unit *dmar;
976 };
977 
978 static device_t
979 dmar_path_dev(int segment, int path_len, int busno,
980     const ACPI_DMAR_PCI_PATH *path, uint16_t *rid)
981 {
982 	device_t dev;
983 	int i;
984 
985 	dev = NULL;
986 	for (i = 0; i < path_len; i++) {
987 		dev = pci_find_dbsf(segment, busno, path->Device,
988 		    path->Function);
989 		if (i != path_len - 1) {
990 			busno = pci_cfgregread(busno, path->Device,
991 			    path->Function, PCIR_SECBUS_1, 1);
992 			path++;
993 		}
994 	}
995 	*rid = PCI_RID(busno, path->Device, path->Function);
996 	return (dev);
997 }
998 
999 static int
1000 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
1001 {
1002 	const ACPI_DMAR_RESERVED_MEMORY *resmem;
1003 	const ACPI_DMAR_DEVICE_SCOPE *devscope;
1004 	struct inst_rmrr_iter_args *iria;
1005 	const char *ptr, *ptrend;
1006 	device_t dev;
1007 	struct dmar_unit *unit;
1008 	int dev_path_len;
1009 	uint16_t rid;
1010 
1011 	iria = arg;
1012 
1013 	if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
1014 		return (1);
1015 
1016 	resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
1017 	if (resmem->Segment != iria->dmar->segment)
1018 		return (1);
1019 
1020 	ptr = (const char *)resmem + sizeof(*resmem);
1021 	ptrend = (const char *)resmem + resmem->Header.Length;
1022 	for (;;) {
1023 		if (ptr >= ptrend)
1024 			break;
1025 		devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
1026 		ptr += devscope->Length;
1027 		/* XXXKIB bridge */
1028 		if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
1029 			continue;
1030 		rid = 0;
1031 		dev_path_len = (devscope->Length -
1032 		    sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2;
1033 		dev = dmar_path_dev(resmem->Segment, dev_path_len,
1034 		    devscope->Bus,
1035 		    (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid);
1036 		if (dev == NULL) {
1037 			if (bootverbose) {
1038 				printf("dmar%d no dev found for RMRR "
1039 				    "[%#jx, %#jx] rid %#x scope path ",
1040 				     iria->dmar->unit,
1041 				     (uintmax_t)resmem->BaseAddress,
1042 				     (uintmax_t)resmem->EndAddress,
1043 				     rid);
1044 				dmar_print_path(devscope->Bus, dev_path_len,
1045 				    (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
1046 				printf("\n");
1047 			}
1048 			unit = dmar_find_by_scope(resmem->Segment,
1049 			    devscope->Bus,
1050 			    (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1051 			    dev_path_len);
1052 			if (iria->dmar != unit)
1053 				continue;
1054 			dmar_get_ctx_for_devpath(iria->dmar, rid,
1055 			    resmem->Segment, devscope->Bus,
1056 			    (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1057 			    dev_path_len, false, true);
1058 		} else {
1059 			unit = dmar_find(dev, false);
1060 			if (iria->dmar != unit)
1061 				continue;
1062 			dmar_instantiate_ctx(iria->dmar, dev, true);
1063 		}
1064 	}
1065 
1066 	return (1);
1067 
1068 }
1069 
1070 /*
1071  * Pre-create all contexts for the DMAR which have RMRR entries.
1072  */
1073 int
1074 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar)
1075 {
1076 	struct inst_rmrr_iter_args iria;
1077 	int error;
1078 
1079 	if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
1080 		return (0);
1081 
1082 	error = 0;
1083 	iria.dmar = dmar;
1084 	dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
1085 	DMAR_LOCK(dmar);
1086 	if (!LIST_EMPTY(&dmar->domains)) {
1087 		KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1088 	    ("dmar%d: RMRR not handled but translation is already enabled",
1089 		    dmar->unit));
1090 		error = dmar_enable_translation(dmar);
1091 		if (bootverbose) {
1092 			if (error == 0) {
1093 				printf("dmar%d: enabled translation\n",
1094 				    dmar->unit);
1095 			} else {
1096 				printf("dmar%d: enabling translation failed, "
1097 				    "error %d\n", dmar->unit, error);
1098 			}
1099 		}
1100 	}
1101 	dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
1102 	return (error);
1103 }
1104 
1105 #ifdef DDB
1106 #include <ddb/ddb.h>
1107 #include <ddb/db_lex.h>
1108 
1109 static void
1110 dmar_print_domain_entry(const struct dmar_map_entry *entry)
1111 {
1112 	struct dmar_map_entry *l, *r;
1113 
1114 	db_printf(
1115 	    "    start %jx end %jx first %jx last %jx free_down %jx flags %x ",
1116 	    entry->start, entry->end, entry->first, entry->last,
1117 	    entry->free_down, entry->flags);
1118 	db_printf("left ");
1119 	l = RB_LEFT(entry, rb_entry);
1120 	if (l == NULL)
1121 		db_printf("NULL ");
1122 	else
1123 		db_printf("%jx ", l->start);
1124 	db_printf("right ");
1125 	r = RB_RIGHT(entry, rb_entry);
1126 	if (r == NULL)
1127 		db_printf("NULL");
1128 	else
1129 		db_printf("%jx", r->start);
1130 	db_printf("\n");
1131 }
1132 
1133 static void
1134 dmar_print_ctx(struct dmar_ctx *ctx)
1135 {
1136 
1137 	db_printf(
1138 	    "    @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
1139 	    ctx, pci_get_bus(ctx->ctx_tag.owner),
1140 	    pci_get_slot(ctx->ctx_tag.owner),
1141 	    pci_get_function(ctx->ctx_tag.owner), ctx->refs, ctx->flags,
1142 	    ctx->loads, ctx->unloads);
1143 }
1144 
1145 static void
1146 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
1147 {
1148 	struct dmar_map_entry *entry;
1149 	struct dmar_ctx *ctx;
1150 
1151 	db_printf(
1152 	    "  @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
1153 	    "   ctx_cnt %d flags %x pgobj %p map_ents %u\n",
1154 	    domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1155 	    (uintmax_t)domain->end, domain->refs, domain->ctx_cnt,
1156 	    domain->flags, domain->pgtbl_obj, domain->entries_cnt);
1157 	if (!LIST_EMPTY(&domain->contexts)) {
1158 		db_printf("  Contexts:\n");
1159 		LIST_FOREACH(ctx, &domain->contexts, link)
1160 			dmar_print_ctx(ctx);
1161 	}
1162 	if (!show_mappings)
1163 		return;
1164 	db_printf("    mapped:\n");
1165 	RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) {
1166 		dmar_print_domain_entry(entry);
1167 		if (db_pager_quit)
1168 			break;
1169 	}
1170 	if (db_pager_quit)
1171 		return;
1172 	db_printf("    unloading:\n");
1173 	TAILQ_FOREACH(entry, &domain->unload_entries, dmamap_link) {
1174 		dmar_print_domain_entry(entry);
1175 		if (db_pager_quit)
1176 			break;
1177 	}
1178 }
1179 
1180 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
1181 {
1182 	struct dmar_unit *unit;
1183 	struct dmar_domain *domain;
1184 	struct dmar_ctx *ctx;
1185 	bool show_mappings, valid;
1186 	int pci_domain, bus, device, function, i, t;
1187 	db_expr_t radix;
1188 
1189 	valid = false;
1190 	radix = db_radix;
1191 	db_radix = 10;
1192 	t = db_read_token();
1193 	if (t == tSLASH) {
1194 		t = db_read_token();
1195 		if (t != tIDENT) {
1196 			db_printf("Bad modifier\n");
1197 			db_radix = radix;
1198 			db_skip_to_eol();
1199 			return;
1200 		}
1201 		show_mappings = strchr(db_tok_string, 'm') != NULL;
1202 		t = db_read_token();
1203 	} else {
1204 		show_mappings = false;
1205 	}
1206 	if (t == tNUMBER) {
1207 		pci_domain = db_tok_number;
1208 		t = db_read_token();
1209 		if (t == tNUMBER) {
1210 			bus = db_tok_number;
1211 			t = db_read_token();
1212 			if (t == tNUMBER) {
1213 				device = db_tok_number;
1214 				t = db_read_token();
1215 				if (t == tNUMBER) {
1216 					function = db_tok_number;
1217 					valid = true;
1218 				}
1219 			}
1220 		}
1221 	}
1222 			db_radix = radix;
1223 	db_skip_to_eol();
1224 	if (!valid) {
1225 		db_printf("usage: show dmar_domain [/m] "
1226 		    "<domain> <bus> <device> <func>\n");
1227 		return;
1228 	}
1229 	for (i = 0; i < dmar_devcnt; i++) {
1230 		unit = device_get_softc(dmar_devs[i]);
1231 		LIST_FOREACH(domain, &unit->domains, link) {
1232 			LIST_FOREACH(ctx, &domain->contexts, link) {
1233 				if (pci_domain == unit->segment &&
1234 				    bus == pci_get_bus(ctx->ctx_tag.owner) &&
1235 				    device ==
1236 				    pci_get_slot(ctx->ctx_tag.owner) &&
1237 				    function ==
1238 				    pci_get_function(ctx->ctx_tag.owner)) {
1239 					dmar_print_domain(domain,
1240 					    show_mappings);
1241 					goto out;
1242 				}
1243 			}
1244 		}
1245 	}
1246 out:;
1247 }
1248 
1249 static void
1250 dmar_print_one(int idx, bool show_domains, bool show_mappings)
1251 {
1252 	struct dmar_unit *unit;
1253 	struct dmar_domain *domain;
1254 	int i, frir;
1255 
1256 	unit = device_get_softc(dmar_devs[idx]);
1257 	db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit,
1258 	    dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG));
1259 	db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1260 	    (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1261 	    (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1262 	    dmar_read4(unit, DMAR_GSTS_REG),
1263 	    dmar_read4(unit, DMAR_FSTS_REG),
1264 	    dmar_read4(unit, DMAR_FECTL_REG));
1265 	if (unit->ir_enabled) {
1266 		db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
1267 		    unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1268 	}
1269 	db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1270 	    dmar_read4(unit, DMAR_FEDATA_REG),
1271 	    dmar_read4(unit, DMAR_FEADDR_REG),
1272 	    dmar_read4(unit, DMAR_FEUADDR_REG));
1273 	db_printf("primary fault log:\n");
1274 	for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1275 		frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1276 		db_printf("  %d at 0x%x: %jx %jx\n", i, frir,
1277 		    (uintmax_t)dmar_read8(unit, frir),
1278 		    (uintmax_t)dmar_read8(unit, frir + 8));
1279 	}
1280 	if (DMAR_HAS_QI(unit)) {
1281 		db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1282 		    dmar_read4(unit, DMAR_IEDATA_REG),
1283 		    dmar_read4(unit, DMAR_IEADDR_REG),
1284 		    dmar_read4(unit, DMAR_IEUADDR_REG));
1285 		if (unit->qi_enabled) {
1286 			db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1287 			    "size 0x%jx\n"
1288 		    "  head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1289 		    "  hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1290 			    (uintmax_t)unit->inv_queue,
1291 			    (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1292 			    (uintmax_t)unit->inv_queue_size,
1293 			    dmar_read4(unit, DMAR_IQH_REG),
1294 			    dmar_read4(unit, DMAR_IQT_REG),
1295 			    unit->inv_queue_avail,
1296 			    dmar_read4(unit, DMAR_ICS_REG),
1297 			    dmar_read4(unit, DMAR_IECTL_REG),
1298 			    unit->inv_waitd_seq_hw,
1299 			    &unit->inv_waitd_seq_hw,
1300 			    (uintmax_t)unit->inv_waitd_seq_hw_phys,
1301 			    unit->inv_waitd_seq,
1302 			    unit->inv_waitd_gen);
1303 		} else {
1304 			db_printf("qi is disabled\n");
1305 		}
1306 	}
1307 	if (show_domains) {
1308 		db_printf("domains:\n");
1309 		LIST_FOREACH(domain, &unit->domains, link) {
1310 			dmar_print_domain(domain, show_mappings);
1311 			if (db_pager_quit)
1312 				break;
1313 		}
1314 	}
1315 }
1316 
1317 DB_SHOW_COMMAND(dmar, db_dmar_print)
1318 {
1319 	bool show_domains, show_mappings;
1320 
1321 	show_domains = strchr(modif, 'd') != NULL;
1322 	show_mappings = strchr(modif, 'm') != NULL;
1323 	if (!have_addr) {
1324 		db_printf("usage: show dmar [/d] [/m] index\n");
1325 		return;
1326 	}
1327 	dmar_print_one((int)addr, show_domains, show_mappings);
1328 }
1329 
1330 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1331 {
1332 	int i;
1333 	bool show_domains, show_mappings;
1334 
1335 	show_domains = strchr(modif, 'd') != NULL;
1336 	show_mappings = strchr(modif, 'm') != NULL;
1337 
1338 	for (i = 0; i < dmar_devcnt; i++) {
1339 		dmar_print_one(i, show_domains, show_mappings);
1340 		if (db_pager_quit)
1341 			break;
1342 	}
1343 }
1344 #endif
1345