1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "opt_acpi.h" 32 #if defined(__amd64__) 33 #define DEV_APIC 34 #else 35 #include "opt_apic.h" 36 #endif 37 #include "opt_ddb.h" 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/memdesc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/rman.h> 48 #include <sys/rwlock.h> 49 #include <sys/smp.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 #include <sys/vmem.h> 53 #include <vm/vm.h> 54 #include <vm/vm_extern.h> 55 #include <vm/vm_kern.h> 56 #include <vm/vm_object.h> 57 #include <vm/vm_page.h> 58 #include <vm/vm_pager.h> 59 #include <vm/vm_map.h> 60 #include <contrib/dev/acpica/include/acpi.h> 61 #include <contrib/dev/acpica/include/accommon.h> 62 #include <dev/acpica/acpivar.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <machine/bus.h> 66 #include <machine/pci_cfgreg.h> 67 #include <x86/include/busdma_impl.h> 68 #include <dev/iommu/busdma_iommu.h> 69 #include <x86/iommu/intel_reg.h> 70 #include <x86/iommu/x86_iommu.h> 71 #include <x86/iommu/intel_dmar.h> 72 73 #ifdef DEV_APIC 74 #include "pcib_if.h" 75 #include <machine/intr_machdep.h> 76 #include <x86/apicreg.h> 77 #include <x86/apicvar.h> 78 #endif 79 80 #define DMAR_FAULT_IRQ_RID 0 81 #define DMAR_QI_IRQ_RID 1 82 #define DMAR_REG_RID 2 83 84 static device_t *dmar_devs; 85 static int dmar_devcnt; 86 87 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 88 89 static void 90 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 91 { 92 ACPI_TABLE_DMAR *dmartbl; 93 ACPI_DMAR_HEADER *dmarh; 94 char *ptr, *ptrend; 95 ACPI_STATUS status; 96 97 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 98 if (ACPI_FAILURE(status)) 99 return; 100 ptr = (char *)dmartbl + sizeof(*dmartbl); 101 ptrend = (char *)dmartbl + dmartbl->Header.Length; 102 for (;;) { 103 if (ptr >= ptrend) 104 break; 105 dmarh = (ACPI_DMAR_HEADER *)ptr; 106 if (dmarh->Length <= 0) { 107 printf("dmar_identify: corrupted DMAR table, l %d\n", 108 dmarh->Length); 109 break; 110 } 111 ptr += dmarh->Length; 112 if (!iter(dmarh, arg)) 113 break; 114 } 115 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 116 } 117 118 struct find_iter_args { 119 int i; 120 ACPI_DMAR_HARDWARE_UNIT *res; 121 }; 122 123 static int 124 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 125 { 126 struct find_iter_args *fia; 127 128 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 129 return (1); 130 131 fia = arg; 132 if (fia->i == 0) { 133 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 134 return (0); 135 } 136 fia->i--; 137 return (1); 138 } 139 140 static ACPI_DMAR_HARDWARE_UNIT * 141 dmar_find_by_index(int idx) 142 { 143 struct find_iter_args fia; 144 145 fia.i = idx; 146 fia.res = NULL; 147 dmar_iterate_tbl(dmar_find_iter, &fia); 148 return (fia.res); 149 } 150 151 static int 152 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 153 { 154 155 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 156 dmar_devcnt++; 157 return (1); 158 } 159 160 int dmar_rmrr_enable = 1; 161 162 static int dmar_enable = 0; 163 static void 164 dmar_identify(driver_t *driver, device_t parent) 165 { 166 ACPI_TABLE_DMAR *dmartbl; 167 ACPI_DMAR_HARDWARE_UNIT *dmarh; 168 ACPI_STATUS status; 169 int i, error; 170 171 if (acpi_disabled("dmar")) 172 return; 173 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 174 if (!dmar_enable) 175 return; 176 TUNABLE_INT_FETCH("hw.dmar.rmrr_enable", &dmar_rmrr_enable); 177 178 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 179 if (ACPI_FAILURE(status)) 180 return; 181 haw = dmartbl->Width + 1; 182 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 183 iommu_high = BUS_SPACE_MAXADDR; 184 else 185 iommu_high = 1ULL << (haw + 1); 186 if (bootverbose) { 187 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 188 (unsigned)dmartbl->Flags, 189 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 190 } 191 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 192 193 dmar_iterate_tbl(dmar_count_iter, NULL); 194 if (dmar_devcnt == 0) 195 return; 196 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 197 M_WAITOK | M_ZERO); 198 for (i = 0; i < dmar_devcnt; i++) { 199 dmarh = dmar_find_by_index(i); 200 if (dmarh == NULL) { 201 printf("dmar_identify: cannot find HWUNIT %d\n", i); 202 continue; 203 } 204 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 205 if (dmar_devs[i] == NULL) { 206 printf("dmar_identify: cannot create instance %d\n", i); 207 continue; 208 } 209 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 210 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 211 if (error != 0) { 212 printf( 213 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 214 i, (uintmax_t)dmarh->Address, error); 215 device_delete_child(parent, dmar_devs[i]); 216 dmar_devs[i] = NULL; 217 } 218 } 219 } 220 221 static int 222 dmar_probe(device_t dev) 223 { 224 225 if (acpi_get_handle(dev) != NULL) 226 return (ENXIO); 227 device_set_desc(dev, "DMA remap"); 228 return (BUS_PROBE_NOWILDCARD); 229 } 230 231 static void 232 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx) 233 { 234 struct dmar_msi_data *dmd; 235 236 dmd = &unit->intrs[idx]; 237 if (dmd->irq == -1) 238 return; 239 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 240 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 241 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 242 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)), 243 dev, dmd->irq); 244 dmd->irq = -1; 245 } 246 247 static void 248 dmar_release_resources(device_t dev, struct dmar_unit *unit) 249 { 250 int i; 251 252 iommu_fini_busdma(&unit->iommu); 253 dmar_fini_irt(unit); 254 dmar_fini_qi(unit); 255 dmar_fini_fault_log(unit); 256 for (i = 0; i < DMAR_INTR_TOTAL; i++) 257 dmar_release_intr(dev, unit, i); 258 if (unit->regs != NULL) { 259 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 260 unit->regs); 261 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 262 unit->regs); 263 unit->regs = NULL; 264 } 265 if (unit->domids != NULL) { 266 delete_unrhdr(unit->domids); 267 unit->domids = NULL; 268 } 269 if (unit->ctx_obj != NULL) { 270 vm_object_deallocate(unit->ctx_obj); 271 unit->ctx_obj = NULL; 272 } 273 } 274 275 static int 276 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx) 277 { 278 device_t pcib; 279 struct dmar_msi_data *dmd; 280 uint64_t msi_addr; 281 uint32_t msi_data; 282 int error; 283 284 dmd = &unit->intrs[idx]; 285 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */ 286 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq); 287 if (error != 0) { 288 device_printf(dev, "cannot allocate %s interrupt, %d\n", 289 dmd->name, error); 290 goto err1; 291 } 292 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid, 293 dmd->irq, 1); 294 if (error != 0) { 295 device_printf(dev, "cannot set %s interrupt resource, %d\n", 296 dmd->name, error); 297 goto err2; 298 } 299 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 300 &dmd->irq_rid, RF_ACTIVE); 301 if (dmd->irq_res == NULL) { 302 device_printf(dev, 303 "cannot allocate resource for %s interrupt\n", dmd->name); 304 error = ENXIO; 305 goto err3; 306 } 307 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC, 308 dmd->handler, NULL, unit, &dmd->intr_handle); 309 if (error != 0) { 310 device_printf(dev, "cannot setup %s interrupt, %d\n", 311 dmd->name, error); 312 goto err4; 313 } 314 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name); 315 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data); 316 if (error != 0) { 317 device_printf(dev, "cannot map %s interrupt, %d\n", 318 dmd->name, error); 319 goto err5; 320 } 321 dmar_write4(unit, dmd->msi_data_reg, msi_data); 322 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 323 /* Only for xAPIC mode */ 324 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 325 return (0); 326 327 err5: 328 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 329 err4: 330 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 331 err3: 332 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 333 err2: 334 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq); 335 dmd->irq = -1; 336 err1: 337 return (error); 338 } 339 340 #ifdef DEV_APIC 341 static int 342 dmar_remap_intr(device_t dev, device_t child, u_int irq) 343 { 344 struct dmar_unit *unit; 345 struct dmar_msi_data *dmd; 346 uint64_t msi_addr; 347 uint32_t msi_data; 348 int i, error; 349 350 unit = device_get_softc(dev); 351 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 352 dmd = &unit->intrs[i]; 353 if (irq == dmd->irq) { 354 error = PCIB_MAP_MSI(device_get_parent( 355 device_get_parent(dev)), 356 dev, irq, &msi_addr, &msi_data); 357 if (error != 0) 358 return (error); 359 DMAR_LOCK(unit); 360 (dmd->disable_intr)(unit); 361 dmar_write4(unit, dmd->msi_data_reg, msi_data); 362 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 363 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 364 (dmd->enable_intr)(unit); 365 DMAR_UNLOCK(unit); 366 return (0); 367 } 368 } 369 return (ENOENT); 370 } 371 #endif 372 373 static void 374 dmar_print_caps(device_t dev, struct dmar_unit *unit, 375 ACPI_DMAR_HARDWARE_UNIT *dmaru) 376 { 377 uint32_t caphi, ecaphi; 378 379 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 380 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 381 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 382 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 383 caphi = unit->hw_cap >> 32; 384 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 385 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 386 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 387 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 388 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 389 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 390 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 391 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 392 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 393 printf("\n"); 394 ecaphi = unit->hw_ecap >> 32; 395 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 396 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 397 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 398 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 399 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 400 DMAR_ECAP_IRO(unit->hw_ecap)); 401 } 402 403 static int 404 dmar_attach(device_t dev) 405 { 406 struct dmar_unit *unit; 407 ACPI_DMAR_HARDWARE_UNIT *dmaru; 408 uint64_t timeout; 409 int disable_pmr; 410 int i, error; 411 412 unit = device_get_softc(dev); 413 unit->iommu.unit = device_get_unit(dev); 414 unit->iommu.dev = dev; 415 dmaru = dmar_find_by_index(unit->iommu.unit); 416 if (dmaru == NULL) 417 return (EINVAL); 418 unit->segment = dmaru->Segment; 419 unit->base = dmaru->Address; 420 unit->reg_rid = DMAR_REG_RID; 421 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 422 &unit->reg_rid, RF_ACTIVE); 423 if (unit->regs == NULL) { 424 device_printf(dev, "cannot allocate register window\n"); 425 dmar_devs[unit->iommu.unit] = NULL; 426 return (ENOMEM); 427 } 428 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 429 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 430 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 431 if (bootverbose) 432 dmar_print_caps(dev, unit, dmaru); 433 dmar_quirks_post_ident(unit); 434 435 timeout = dmar_get_timeout(); 436 TUNABLE_UINT64_FETCH("hw.iommu.dmar.timeout", &timeout); 437 dmar_update_timeout(timeout); 438 439 for (i = 0; i < DMAR_INTR_TOTAL; i++) 440 unit->intrs[i].irq = -1; 441 442 unit->intrs[DMAR_INTR_FAULT].name = "fault"; 443 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; 444 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; 445 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; 446 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; 447 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; 448 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr; 449 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr; 450 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT); 451 if (error != 0) { 452 dmar_release_resources(dev, unit); 453 dmar_devs[unit->iommu.unit] = NULL; 454 return (error); 455 } 456 if (DMAR_HAS_QI(unit)) { 457 unit->intrs[DMAR_INTR_QI].name = "qi"; 458 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID; 459 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr; 460 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG; 461 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG; 462 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG; 463 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr; 464 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr; 465 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI); 466 if (error != 0) { 467 dmar_release_resources(dev, unit); 468 dmar_devs[unit->iommu.unit] = NULL; 469 return (error); 470 } 471 } 472 473 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); 474 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 475 &unit->iommu.lock); 476 LIST_INIT(&unit->domains); 477 478 /* 479 * 9.2 "Context Entry": 480 * When Caching Mode (CM) field is reported as Set, the 481 * domain-id value of zero is architecturally reserved. 482 * Software must not use domain-id value of zero 483 * when CM is Set. 484 */ 485 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 486 alloc_unr_specific(unit->domids, 0); 487 488 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 489 DMAR_CTX_CNT), 0, 0, NULL); 490 491 /* 492 * Allocate and load the root entry table pointer. Enable the 493 * address translation after the required invalidations are 494 * done. 495 */ 496 iommu_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); 497 DMAR_LOCK(unit); 498 error = dmar_load_root_entry_ptr(unit); 499 if (error != 0) { 500 DMAR_UNLOCK(unit); 501 dmar_release_resources(dev, unit); 502 dmar_devs[unit->iommu.unit] = NULL; 503 return (error); 504 } 505 error = dmar_inv_ctx_glob(unit); 506 if (error != 0) { 507 DMAR_UNLOCK(unit); 508 dmar_release_resources(dev, unit); 509 dmar_devs[unit->iommu.unit] = NULL; 510 return (error); 511 } 512 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 513 error = dmar_inv_iotlb_glob(unit); 514 if (error != 0) { 515 DMAR_UNLOCK(unit); 516 dmar_release_resources(dev, unit); 517 dmar_devs[unit->iommu.unit] = NULL; 518 return (error); 519 } 520 } 521 522 DMAR_UNLOCK(unit); 523 error = dmar_init_fault_log(unit); 524 if (error != 0) { 525 dmar_release_resources(dev, unit); 526 dmar_devs[unit->iommu.unit] = NULL; 527 return (error); 528 } 529 error = dmar_init_qi(unit); 530 if (error != 0) { 531 dmar_release_resources(dev, unit); 532 dmar_devs[unit->iommu.unit] = NULL; 533 return (error); 534 } 535 error = dmar_init_irt(unit); 536 if (error != 0) { 537 dmar_release_resources(dev, unit); 538 dmar_devs[unit->iommu.unit] = NULL; 539 return (error); 540 } 541 542 disable_pmr = 0; 543 TUNABLE_INT_FETCH("hw.dmar.pmr.disable", &disable_pmr); 544 if (disable_pmr) { 545 error = dmar_disable_protected_regions(unit); 546 if (error != 0) 547 device_printf(dev, 548 "Failed to disable protected regions\n"); 549 } 550 551 error = iommu_init_busdma(&unit->iommu); 552 if (error != 0) { 553 dmar_release_resources(dev, unit); 554 dmar_devs[unit->iommu.unit] = NULL; 555 return (error); 556 } 557 558 #ifdef NOTYET 559 DMAR_LOCK(unit); 560 error = dmar_enable_translation(unit); 561 if (error != 0) { 562 DMAR_UNLOCK(unit); 563 dmar_release_resources(dev, unit); 564 dmar_devs[unit->iommu.unit] = NULL; 565 return (error); 566 } 567 DMAR_UNLOCK(unit); 568 #endif 569 570 return (0); 571 } 572 573 static int 574 dmar_detach(device_t dev) 575 { 576 577 return (EBUSY); 578 } 579 580 static int 581 dmar_suspend(device_t dev) 582 { 583 584 return (0); 585 } 586 587 static int 588 dmar_resume(device_t dev) 589 { 590 591 /* XXXKIB */ 592 return (0); 593 } 594 595 static device_method_t dmar_methods[] = { 596 DEVMETHOD(device_identify, dmar_identify), 597 DEVMETHOD(device_probe, dmar_probe), 598 DEVMETHOD(device_attach, dmar_attach), 599 DEVMETHOD(device_detach, dmar_detach), 600 DEVMETHOD(device_suspend, dmar_suspend), 601 DEVMETHOD(device_resume, dmar_resume), 602 #ifdef DEV_APIC 603 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 604 #endif 605 DEVMETHOD_END 606 }; 607 608 static driver_t dmar_driver = { 609 "dmar", 610 dmar_methods, 611 sizeof(struct dmar_unit), 612 }; 613 614 DRIVER_MODULE(dmar, acpi, dmar_driver, 0, 0); 615 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 616 617 static void 618 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 619 { 620 int i; 621 622 printf("[%d, ", busno); 623 for (i = 0; i < depth; i++) { 624 if (i != 0) 625 printf(", "); 626 printf("(%d, %d)", path[i].Device, path[i].Function); 627 } 628 printf("]"); 629 } 630 631 int 632 dmar_dev_depth(device_t child) 633 { 634 devclass_t pci_class; 635 device_t bus, pcib; 636 int depth; 637 638 pci_class = devclass_find("pci"); 639 for (depth = 1; ; depth++) { 640 bus = device_get_parent(child); 641 pcib = device_get_parent(bus); 642 if (device_get_devclass(device_get_parent(pcib)) != 643 pci_class) 644 return (depth); 645 child = pcib; 646 } 647 } 648 649 void 650 dmar_dev_path(device_t child, int *busno, void *path1, int depth) 651 { 652 devclass_t pci_class; 653 device_t bus, pcib; 654 ACPI_DMAR_PCI_PATH *path; 655 656 pci_class = devclass_find("pci"); 657 path = path1; 658 for (depth--; depth != -1; depth--) { 659 path[depth].Device = pci_get_slot(child); 660 path[depth].Function = pci_get_function(child); 661 bus = device_get_parent(child); 662 pcib = device_get_parent(bus); 663 if (device_get_devclass(device_get_parent(pcib)) != 664 pci_class) { 665 /* reached a host bridge */ 666 *busno = pcib_get_bus(bus); 667 return; 668 } 669 child = pcib; 670 } 671 panic("wrong depth"); 672 } 673 674 static int 675 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 676 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 677 enum AcpiDmarScopeType scope_type) 678 { 679 int i, depth; 680 681 if (busno1 != busno2) 682 return (0); 683 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 684 return (0); 685 depth = depth1; 686 if (depth2 < depth) 687 depth = depth2; 688 for (i = 0; i < depth; i++) { 689 if (path1[i].Device != path2[i].Device || 690 path1[i].Function != path2[i].Function) 691 return (0); 692 } 693 return (1); 694 } 695 696 static int 697 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 698 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 699 { 700 ACPI_DMAR_PCI_PATH *path; 701 int path_len; 702 703 if (devscope->Length < sizeof(*devscope)) { 704 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 705 devscope->Length); 706 return (-1); 707 } 708 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 709 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 710 return (0); 711 path_len = devscope->Length - sizeof(*devscope); 712 if (path_len % 2 != 0) { 713 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 714 devscope->Length); 715 return (-1); 716 } 717 path_len /= 2; 718 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 719 if (path_len == 0) { 720 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 721 devscope->Length); 722 return (-1); 723 } 724 725 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 726 dev_path, dev_path_len, devscope->EntryType)); 727 } 728 729 static bool 730 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 731 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 732 { 733 ACPI_DMAR_HARDWARE_UNIT *dmarh; 734 ACPI_DMAR_DEVICE_SCOPE *devscope; 735 char *ptr, *ptrend; 736 int match; 737 738 dmarh = dmar_find_by_index(unit->iommu.unit); 739 if (dmarh == NULL) 740 return (false); 741 if (dmarh->Segment != dev_domain) 742 return (false); 743 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 744 if (banner != NULL) 745 *banner = "INCLUDE_ALL"; 746 return (true); 747 } 748 ptr = (char *)dmarh + sizeof(*dmarh); 749 ptrend = (char *)dmarh + dmarh->Header.Length; 750 while (ptr < ptrend) { 751 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 752 ptr += devscope->Length; 753 match = dmar_match_devscope(devscope, dev_busno, dev_path, 754 dev_path_len); 755 if (match == -1) 756 return (false); 757 if (match == 1) { 758 if (banner != NULL) 759 *banner = "specific match"; 760 return (true); 761 } 762 } 763 return (false); 764 } 765 766 static struct dmar_unit * 767 dmar_find_by_scope(int dev_domain, int dev_busno, 768 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 769 { 770 struct dmar_unit *unit; 771 int i; 772 773 for (i = 0; i < dmar_devcnt; i++) { 774 if (dmar_devs[i] == NULL) 775 continue; 776 unit = device_get_softc(dmar_devs[i]); 777 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 778 dev_path_len, NULL)) 779 return (unit); 780 } 781 return (NULL); 782 } 783 784 struct dmar_unit * 785 dmar_find(device_t dev, bool verbose) 786 { 787 struct dmar_unit *unit; 788 const char *banner; 789 int i, dev_domain, dev_busno, dev_path_len; 790 791 /* 792 * This function can only handle PCI(e) devices. 793 */ 794 if (device_get_devclass(device_get_parent(dev)) != 795 devclass_find("pci")) 796 return (NULL); 797 798 dev_domain = pci_get_domain(dev); 799 dev_path_len = dmar_dev_depth(dev); 800 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 801 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 802 banner = ""; 803 804 for (i = 0; i < dmar_devcnt; i++) { 805 if (dmar_devs[i] == NULL) 806 continue; 807 unit = device_get_softc(dmar_devs[i]); 808 if (dmar_match_by_path(unit, dev_domain, dev_busno, 809 dev_path, dev_path_len, &banner)) 810 break; 811 } 812 if (i == dmar_devcnt) 813 return (NULL); 814 815 if (verbose) { 816 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 817 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 818 pci_get_function(dev), unit->iommu.unit, banner); 819 printf(" scope path "); 820 dmar_print_path(dev_busno, dev_path_len, dev_path); 821 printf("\n"); 822 } 823 return (unit); 824 } 825 826 static struct dmar_unit * 827 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 828 { 829 device_t dmar_dev; 830 struct dmar_unit *unit; 831 ACPI_DMAR_HARDWARE_UNIT *dmarh; 832 ACPI_DMAR_DEVICE_SCOPE *devscope; 833 ACPI_DMAR_PCI_PATH *path; 834 char *ptr, *ptrend; 835 #ifdef DEV_APIC 836 int error; 837 #endif 838 int i; 839 840 for (i = 0; i < dmar_devcnt; i++) { 841 dmar_dev = dmar_devs[i]; 842 if (dmar_dev == NULL) 843 continue; 844 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 845 dmarh = dmar_find_by_index(i); 846 if (dmarh == NULL) 847 continue; 848 ptr = (char *)dmarh + sizeof(*dmarh); 849 ptrend = (char *)dmarh + dmarh->Header.Length; 850 for (;;) { 851 if (ptr >= ptrend) 852 break; 853 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 854 ptr += devscope->Length; 855 if (devscope->EntryType != entry_type) 856 continue; 857 if (devscope->EnumerationId != id) 858 continue; 859 #ifdef DEV_APIC 860 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 861 error = ioapic_get_rid(id, rid); 862 /* 863 * If our IOAPIC has PCI bindings then 864 * use the PCI device rid. 865 */ 866 if (error == 0) 867 return (unit); 868 } 869 #endif 870 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 871 == 2) { 872 if (rid != NULL) { 873 path = (ACPI_DMAR_PCI_PATH *) 874 (devscope + 1); 875 *rid = PCI_RID(devscope->Bus, 876 path->Device, path->Function); 877 } 878 return (unit); 879 } 880 printf( 881 "dmar_find_nonpci: id %d type %d path length != 2\n", 882 id, entry_type); 883 break; 884 } 885 } 886 return (NULL); 887 } 888 889 struct dmar_unit * 890 dmar_find_hpet(device_t dev, uint16_t *rid) 891 { 892 893 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 894 rid)); 895 } 896 897 struct dmar_unit * 898 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 899 { 900 901 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 902 } 903 904 struct rmrr_iter_args { 905 struct dmar_domain *domain; 906 int dev_domain; 907 int dev_busno; 908 const ACPI_DMAR_PCI_PATH *dev_path; 909 int dev_path_len; 910 struct iommu_map_entries_tailq *rmrr_entries; 911 }; 912 913 static int 914 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 915 { 916 struct rmrr_iter_args *ria; 917 ACPI_DMAR_RESERVED_MEMORY *resmem; 918 ACPI_DMAR_DEVICE_SCOPE *devscope; 919 struct iommu_map_entry *entry; 920 char *ptr, *ptrend; 921 int match; 922 923 if (!dmar_rmrr_enable) 924 return (1); 925 926 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 927 return (1); 928 929 ria = arg; 930 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 931 if (resmem->Segment != ria->dev_domain) 932 return (1); 933 934 ptr = (char *)resmem + sizeof(*resmem); 935 ptrend = (char *)resmem + resmem->Header.Length; 936 for (;;) { 937 if (ptr >= ptrend) 938 break; 939 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 940 ptr += devscope->Length; 941 match = dmar_match_devscope(devscope, ria->dev_busno, 942 ria->dev_path, ria->dev_path_len); 943 if (match == 1) { 944 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), 945 IOMMU_PGF_WAITOK); 946 entry->start = resmem->BaseAddress; 947 /* The RMRR entry end address is inclusive. */ 948 entry->end = resmem->EndAddress; 949 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 950 dmamap_link); 951 } 952 } 953 954 return (1); 955 } 956 957 void 958 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 959 const void *dev_path, int dev_path_len, 960 struct iommu_map_entries_tailq *rmrr_entries) 961 { 962 struct rmrr_iter_args ria; 963 964 ria.domain = domain; 965 ria.dev_domain = dev_domain; 966 ria.dev_busno = dev_busno; 967 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 968 ria.dev_path_len = dev_path_len; 969 ria.rmrr_entries = rmrr_entries; 970 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 971 } 972 973 struct inst_rmrr_iter_args { 974 struct dmar_unit *dmar; 975 }; 976 977 static device_t 978 dmar_path_dev(int segment, int path_len, int busno, 979 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 980 { 981 device_t dev; 982 int i; 983 984 dev = NULL; 985 for (i = 0; i < path_len; i++) { 986 dev = pci_find_dbsf(segment, busno, path->Device, 987 path->Function); 988 if (i != path_len - 1) { 989 busno = pci_cfgregread(segment, busno, path->Device, 990 path->Function, PCIR_SECBUS_1, 1); 991 path++; 992 } 993 } 994 *rid = PCI_RID(busno, path->Device, path->Function); 995 return (dev); 996 } 997 998 static int 999 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 1000 { 1001 const ACPI_DMAR_RESERVED_MEMORY *resmem; 1002 const ACPI_DMAR_DEVICE_SCOPE *devscope; 1003 struct inst_rmrr_iter_args *iria; 1004 const char *ptr, *ptrend; 1005 device_t dev; 1006 struct dmar_unit *unit; 1007 int dev_path_len; 1008 uint16_t rid; 1009 1010 iria = arg; 1011 1012 if (!dmar_rmrr_enable) 1013 return (1); 1014 1015 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 1016 return (1); 1017 1018 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 1019 if (resmem->Segment != iria->dmar->segment) 1020 return (1); 1021 1022 ptr = (const char *)resmem + sizeof(*resmem); 1023 ptrend = (const char *)resmem + resmem->Header.Length; 1024 for (;;) { 1025 if (ptr >= ptrend) 1026 break; 1027 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 1028 ptr += devscope->Length; 1029 /* XXXKIB bridge */ 1030 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 1031 continue; 1032 rid = 0; 1033 dev_path_len = (devscope->Length - 1034 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 1035 dev = dmar_path_dev(resmem->Segment, dev_path_len, 1036 devscope->Bus, 1037 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 1038 if (dev == NULL) { 1039 if (bootverbose) { 1040 printf("dmar%d no dev found for RMRR " 1041 "[%#jx, %#jx] rid %#x scope path ", 1042 iria->dmar->iommu.unit, 1043 (uintmax_t)resmem->BaseAddress, 1044 (uintmax_t)resmem->EndAddress, 1045 rid); 1046 dmar_print_path(devscope->Bus, dev_path_len, 1047 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1048 printf("\n"); 1049 } 1050 unit = dmar_find_by_scope(resmem->Segment, 1051 devscope->Bus, 1052 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1053 dev_path_len); 1054 if (iria->dmar != unit) 1055 continue; 1056 dmar_get_ctx_for_devpath(iria->dmar, rid, 1057 resmem->Segment, devscope->Bus, 1058 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1059 dev_path_len, false, true); 1060 } else { 1061 unit = dmar_find(dev, false); 1062 if (iria->dmar != unit) 1063 continue; 1064 iommu_instantiate_ctx(&(iria)->dmar->iommu, 1065 dev, true); 1066 } 1067 } 1068 1069 return (1); 1070 1071 } 1072 1073 /* 1074 * Pre-create all contexts for the DMAR which have RMRR entries. 1075 */ 1076 int 1077 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) 1078 { 1079 struct dmar_unit *dmar; 1080 struct inst_rmrr_iter_args iria; 1081 int error; 1082 1083 dmar = IOMMU2DMAR(unit); 1084 1085 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1086 return (0); 1087 1088 error = 0; 1089 iria.dmar = dmar; 1090 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1091 DMAR_LOCK(dmar); 1092 if (!LIST_EMPTY(&dmar->domains)) { 1093 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1094 ("dmar%d: RMRR not handled but translation is already enabled", 1095 dmar->iommu.unit)); 1096 error = dmar_disable_protected_regions(dmar); 1097 if (error != 0) 1098 printf("dmar%d: Failed to disable protected regions\n", 1099 dmar->iommu.unit); 1100 error = dmar_enable_translation(dmar); 1101 if (bootverbose) { 1102 if (error == 0) { 1103 printf("dmar%d: enabled translation\n", 1104 dmar->iommu.unit); 1105 } else { 1106 printf("dmar%d: enabling translation failed, " 1107 "error %d\n", dmar->iommu.unit, error); 1108 } 1109 } 1110 } 1111 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1112 return (error); 1113 } 1114 1115 #ifdef DDB 1116 #include <ddb/ddb.h> 1117 #include <ddb/db_lex.h> 1118 1119 static void 1120 dmar_print_domain_entry(const struct iommu_map_entry *entry) 1121 { 1122 struct iommu_map_entry *l, *r; 1123 1124 db_printf( 1125 " start %jx end %jx first %jx last %jx free_down %jx flags %x ", 1126 entry->start, entry->end, entry->first, entry->last, 1127 entry->free_down, entry->flags); 1128 db_printf("left "); 1129 l = RB_LEFT(entry, rb_entry); 1130 if (l == NULL) 1131 db_printf("NULL "); 1132 else 1133 db_printf("%jx ", l->start); 1134 db_printf("right "); 1135 r = RB_RIGHT(entry, rb_entry); 1136 if (r == NULL) 1137 db_printf("NULL"); 1138 else 1139 db_printf("%jx", r->start); 1140 db_printf("\n"); 1141 } 1142 1143 static void 1144 dmar_print_ctx(struct dmar_ctx *ctx) 1145 { 1146 1147 db_printf( 1148 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n", 1149 ctx, pci_get_bus(ctx->context.tag->owner), 1150 pci_get_slot(ctx->context.tag->owner), 1151 pci_get_function(ctx->context.tag->owner), ctx->refs, 1152 ctx->context.flags, ctx->context.loads, ctx->context.unloads); 1153 } 1154 1155 static void 1156 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1157 { 1158 struct iommu_domain *iodom; 1159 struct iommu_map_entry *entry; 1160 struct dmar_ctx *ctx; 1161 1162 iodom = DOM2IODOM(domain); 1163 1164 db_printf( 1165 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1166 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1167 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1168 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt, 1169 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt); 1170 if (!LIST_EMPTY(&domain->contexts)) { 1171 db_printf(" Contexts:\n"); 1172 LIST_FOREACH(ctx, &domain->contexts, link) 1173 dmar_print_ctx(ctx); 1174 } 1175 if (!show_mappings) 1176 return; 1177 db_printf(" mapped:\n"); 1178 RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) { 1179 dmar_print_domain_entry(entry); 1180 if (db_pager_quit) 1181 break; 1182 } 1183 if (db_pager_quit) 1184 return; 1185 db_printf(" unloading:\n"); 1186 TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) { 1187 dmar_print_domain_entry(entry); 1188 if (db_pager_quit) 1189 break; 1190 } 1191 } 1192 1193 DB_SHOW_COMMAND_FLAGS(dmar_domain, db_dmar_print_domain, CS_OWN) 1194 { 1195 struct dmar_unit *unit; 1196 struct dmar_domain *domain; 1197 struct dmar_ctx *ctx; 1198 bool show_mappings, valid; 1199 int pci_domain, bus, device, function, i, t; 1200 db_expr_t radix; 1201 1202 valid = false; 1203 radix = db_radix; 1204 db_radix = 10; 1205 t = db_read_token(); 1206 if (t == tSLASH) { 1207 t = db_read_token(); 1208 if (t != tIDENT) { 1209 db_printf("Bad modifier\n"); 1210 db_radix = radix; 1211 db_skip_to_eol(); 1212 return; 1213 } 1214 show_mappings = strchr(db_tok_string, 'm') != NULL; 1215 t = db_read_token(); 1216 } else { 1217 show_mappings = false; 1218 } 1219 if (t == tNUMBER) { 1220 pci_domain = db_tok_number; 1221 t = db_read_token(); 1222 if (t == tNUMBER) { 1223 bus = db_tok_number; 1224 t = db_read_token(); 1225 if (t == tNUMBER) { 1226 device = db_tok_number; 1227 t = db_read_token(); 1228 if (t == tNUMBER) { 1229 function = db_tok_number; 1230 valid = true; 1231 } 1232 } 1233 } 1234 } 1235 db_radix = radix; 1236 db_skip_to_eol(); 1237 if (!valid) { 1238 db_printf("usage: show dmar_domain [/m] " 1239 "<domain> <bus> <device> <func>\n"); 1240 return; 1241 } 1242 for (i = 0; i < dmar_devcnt; i++) { 1243 unit = device_get_softc(dmar_devs[i]); 1244 LIST_FOREACH(domain, &unit->domains, link) { 1245 LIST_FOREACH(ctx, &domain->contexts, link) { 1246 if (pci_domain == unit->segment && 1247 bus == pci_get_bus(ctx->context.tag->owner) && 1248 device == 1249 pci_get_slot(ctx->context.tag->owner) && 1250 function == 1251 pci_get_function(ctx->context.tag->owner)) { 1252 dmar_print_domain(domain, 1253 show_mappings); 1254 goto out; 1255 } 1256 } 1257 } 1258 } 1259 out:; 1260 } 1261 1262 static void 1263 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1264 { 1265 struct dmar_unit *unit; 1266 struct dmar_domain *domain; 1267 int i, frir; 1268 1269 unit = device_get_softc(dmar_devs[idx]); 1270 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, 1271 unit, dmar_read8(unit, DMAR_RTADDR_REG), 1272 dmar_read4(unit, DMAR_VER_REG)); 1273 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1274 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1275 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1276 dmar_read4(unit, DMAR_GSTS_REG), 1277 dmar_read4(unit, DMAR_FSTS_REG), 1278 dmar_read4(unit, DMAR_FECTL_REG)); 1279 if (unit->ir_enabled) { 1280 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1281 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1282 } 1283 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1284 dmar_read4(unit, DMAR_FEDATA_REG), 1285 dmar_read4(unit, DMAR_FEADDR_REG), 1286 dmar_read4(unit, DMAR_FEUADDR_REG)); 1287 db_printf("primary fault log:\n"); 1288 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1289 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1290 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1291 (uintmax_t)dmar_read8(unit, frir), 1292 (uintmax_t)dmar_read8(unit, frir + 8)); 1293 } 1294 if (DMAR_HAS_QI(unit)) { 1295 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1296 dmar_read4(unit, DMAR_IEDATA_REG), 1297 dmar_read4(unit, DMAR_IEADDR_REG), 1298 dmar_read4(unit, DMAR_IEUADDR_REG)); 1299 if (unit->qi_enabled) { 1300 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1301 "size 0x%jx\n" 1302 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1303 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1304 (uintmax_t)unit->inv_queue, 1305 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1306 (uintmax_t)unit->inv_queue_size, 1307 dmar_read4(unit, DMAR_IQH_REG), 1308 dmar_read4(unit, DMAR_IQT_REG), 1309 unit->inv_queue_avail, 1310 dmar_read4(unit, DMAR_ICS_REG), 1311 dmar_read4(unit, DMAR_IECTL_REG), 1312 unit->inv_waitd_seq_hw, 1313 &unit->inv_waitd_seq_hw, 1314 (uintmax_t)unit->inv_waitd_seq_hw_phys, 1315 unit->inv_waitd_seq, 1316 unit->inv_waitd_gen); 1317 } else { 1318 db_printf("qi is disabled\n"); 1319 } 1320 } 1321 if (show_domains) { 1322 db_printf("domains:\n"); 1323 LIST_FOREACH(domain, &unit->domains, link) { 1324 dmar_print_domain(domain, show_mappings); 1325 if (db_pager_quit) 1326 break; 1327 } 1328 } 1329 } 1330 1331 DB_SHOW_COMMAND(dmar, db_dmar_print) 1332 { 1333 bool show_domains, show_mappings; 1334 1335 show_domains = strchr(modif, 'd') != NULL; 1336 show_mappings = strchr(modif, 'm') != NULL; 1337 if (!have_addr) { 1338 db_printf("usage: show dmar [/d] [/m] index\n"); 1339 return; 1340 } 1341 dmar_print_one((int)addr, show_domains, show_mappings); 1342 } 1343 1344 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1345 { 1346 int i; 1347 bool show_domains, show_mappings; 1348 1349 show_domains = strchr(modif, 'd') != NULL; 1350 show_mappings = strchr(modif, 'm') != NULL; 1351 1352 for (i = 0; i < dmar_devcnt; i++) { 1353 dmar_print_one(i, show_domains, show_mappings); 1354 if (db_pager_quit) 1355 break; 1356 } 1357 } 1358 #endif 1359 1360 struct iommu_unit * 1361 iommu_find(device_t dev, bool verbose) 1362 { 1363 struct dmar_unit *dmar; 1364 1365 dmar = dmar_find(dev, verbose); 1366 1367 return (&dmar->iommu); 1368 } 1369