1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef __X86_IOMMU_INTEL_DMAR_H 35 #define __X86_IOMMU_INTEL_DMAR_H 36 37 #include <sys/iommu.h> 38 39 struct dmar_unit; 40 41 RB_HEAD(dmar_gas_entries_tree, iommu_map_entry); 42 RB_PROTOTYPE(dmar_gas_entries_tree, iommu_map_entry, rb_entry, 43 dmar_gas_cmp_entries); 44 45 /* 46 * Locking annotations: 47 * (u) - Protected by iommu unit lock 48 * (d) - Protected by domain lock 49 * (c) - Immutable after initialization 50 */ 51 52 /* 53 * The domain abstraction. Most non-constant members of the domain 54 * are protected by owning dmar unit lock, not by the domain lock. 55 * Most important, the dmar lock protects the contexts list. 56 * 57 * The domain lock protects the address map for the domain, and list 58 * of unload entries delayed. 59 * 60 * Page tables pages and pages content is protected by the vm object 61 * lock pgtbl_obj, which contains the page tables pages. 62 */ 63 struct dmar_domain { 64 struct iommu_domain iodom; 65 int domain; /* (c) DID, written in context entry */ 66 int mgaw; /* (c) Real max address width */ 67 int agaw; /* (c) Adjusted guest address width */ 68 int pglvl; /* (c) The pagelevel */ 69 int awlvl; /* (c) The pagelevel as the bitmask, 70 to set in context entry */ 71 iommu_gaddr_t end; /* (c) Highest address + 1 in 72 the guest AS */ 73 u_int ctx_cnt; /* (u) Number of contexts owned */ 74 u_int refs; /* (u) Refs, including ctx */ 75 struct dmar_unit *dmar; /* (c) */ 76 LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */ 77 LIST_HEAD(, dmar_ctx) contexts; /* (u) */ 78 vm_object_t pgtbl_obj; /* (c) Page table pages */ 79 u_int flags; /* (u) */ 80 u_int entries_cnt; /* (d) */ 81 struct dmar_gas_entries_tree rb_root; /* (d) */ 82 struct iommu_map_entry *first_place, *last_place; /* (d) */ 83 u_int batch_no; 84 }; 85 86 struct dmar_ctx { 87 struct iommu_ctx context; 88 uint16_t rid; /* (c) pci RID */ 89 uint64_t last_fault_rec[2]; /* Last fault reported */ 90 LIST_ENTRY(dmar_ctx) link; /* (u) Member in the domain list */ 91 u_int refs; /* (u) References from tags */ 92 }; 93 94 #define DMAR_DOMAIN_GAS_INITED 0x0001 95 #define DMAR_DOMAIN_PGTBL_INITED 0x0002 96 #define DMAR_DOMAIN_IDMAP 0x0010 /* Domain uses identity 97 page table */ 98 #define DMAR_DOMAIN_RMRR 0x0020 /* Domain contains RMRR entry, 99 cannot be turned off */ 100 101 #define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj) 102 #define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj) 103 #define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj) 104 #define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \ 105 VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj) 106 107 #define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->iodom.lock) 108 #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->iodom.lock) 109 #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->iodom.lock, MA_OWNED) 110 111 struct dmar_msi_data { 112 int irq; 113 int irq_rid; 114 struct resource *irq_res; 115 void *intr_handle; 116 int (*handler)(void *); 117 int msi_data_reg; 118 int msi_addr_reg; 119 int msi_uaddr_reg; 120 void (*enable_intr)(struct dmar_unit *); 121 void (*disable_intr)(struct dmar_unit *); 122 const char *name; 123 }; 124 125 #define DMAR_INTR_FAULT 0 126 #define DMAR_INTR_QI 1 127 #define DMAR_INTR_TOTAL 2 128 129 struct dmar_unit { 130 struct iommu_unit iommu; 131 device_t dev; 132 uint16_t segment; 133 uint64_t base; 134 135 /* Resources */ 136 int reg_rid; 137 struct resource *regs; 138 139 struct dmar_msi_data intrs[DMAR_INTR_TOTAL]; 140 141 /* Hardware registers cache */ 142 uint32_t hw_ver; 143 uint64_t hw_cap; 144 uint64_t hw_ecap; 145 uint32_t hw_gcmd; 146 147 /* Data for being a dmar */ 148 LIST_HEAD(, dmar_domain) domains; 149 struct unrhdr *domids; 150 vm_object_t ctx_obj; 151 u_int barrier_flags; 152 153 /* Fault handler data */ 154 struct mtx fault_lock; 155 uint64_t *fault_log; 156 int fault_log_head; 157 int fault_log_tail; 158 int fault_log_size; 159 struct task fault_task; 160 struct taskqueue *fault_taskqueue; 161 162 /* QI */ 163 int qi_enabled; 164 vm_offset_t inv_queue; 165 vm_size_t inv_queue_size; 166 uint32_t inv_queue_avail; 167 uint32_t inv_queue_tail; 168 volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait 169 descr completion */ 170 uint64_t inv_waitd_seq_hw_phys; 171 uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */ 172 u_int inv_waitd_gen; /* seq number generation AKA seq overflows */ 173 u_int inv_seq_waiters; /* count of waiters for seq */ 174 u_int inv_queue_full; /* informational counter */ 175 176 /* IR */ 177 int ir_enabled; 178 vm_paddr_t irt_phys; 179 dmar_irte_t *irt; 180 u_int irte_cnt; 181 vmem_t *irtids; 182 183 /* Delayed freeing of map entries queue processing */ 184 struct iommu_map_entries_tailq tlb_flush_entries; 185 struct task qi_task; 186 struct taskqueue *qi_taskqueue; 187 188 /* 189 * Bitmap of buses for which context must ignore slot:func, 190 * duplicating the page table pointer into all context table 191 * entries. This is a client-controlled quirk to support some 192 * NTBs. 193 */ 194 uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)]; 195 196 }; 197 198 #define DMAR_LOCK(dmar) mtx_lock(&(dmar)->iommu.lock) 199 #define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->iommu.lock) 200 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->iommu.lock, MA_OWNED) 201 202 #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) 203 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) 204 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) 205 206 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 207 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 208 #define DMAR_X2APIC(dmar) \ 209 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0) 210 211 /* Barrier ids */ 212 #define DMAR_BARRIER_RMRR 0 213 #define DMAR_BARRIER_USEQ 1 214 215 struct dmar_unit *dmar_find(device_t dev, bool verbose); 216 struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid); 217 struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid); 218 219 u_int dmar_nd2mask(u_int nd); 220 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl); 221 int domain_set_agaw(struct dmar_domain *domain, int mgaw); 222 int dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, 223 bool allow_less); 224 vm_pindex_t pglvl_max_pages(int pglvl); 225 int domain_is_sp_lvl(struct dmar_domain *domain, int lvl); 226 iommu_gaddr_t pglvl_page_size(int total_pglvl, int lvl); 227 iommu_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl); 228 int calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size, 229 iommu_gaddr_t *isizep); 230 struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags); 231 void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags); 232 void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 233 struct sf_buf **sf); 234 void dmar_unmap_pgtbl(struct sf_buf *sf); 235 int dmar_load_root_entry_ptr(struct dmar_unit *unit); 236 int dmar_inv_ctx_glob(struct dmar_unit *unit); 237 int dmar_inv_iotlb_glob(struct dmar_unit *unit); 238 int dmar_flush_write_bufs(struct dmar_unit *unit); 239 void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst); 240 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst); 241 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst); 242 int dmar_enable_translation(struct dmar_unit *unit); 243 int dmar_disable_translation(struct dmar_unit *unit); 244 int dmar_load_irt_ptr(struct dmar_unit *unit); 245 int dmar_enable_ir(struct dmar_unit *unit); 246 int dmar_disable_ir(struct dmar_unit *unit); 247 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id); 248 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id); 249 uint64_t dmar_get_timeout(void); 250 void dmar_update_timeout(uint64_t newval); 251 252 int dmar_fault_intr(void *arg); 253 void dmar_enable_fault_intr(struct dmar_unit *unit); 254 void dmar_disable_fault_intr(struct dmar_unit *unit); 255 int dmar_init_fault_log(struct dmar_unit *unit); 256 void dmar_fini_fault_log(struct dmar_unit *unit); 257 258 int dmar_qi_intr(void *arg); 259 void dmar_enable_qi_intr(struct dmar_unit *unit); 260 void dmar_disable_qi_intr(struct dmar_unit *unit); 261 int dmar_init_qi(struct dmar_unit *unit); 262 void dmar_fini_qi(struct dmar_unit *unit); 263 void dmar_qi_invalidate_locked(struct dmar_domain *domain, iommu_gaddr_t start, 264 iommu_gaddr_t size, struct iommu_qi_genseq *psec, bool emit_wait); 265 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit); 266 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit); 267 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit); 268 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt); 269 270 vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain, 271 iommu_gaddr_t maxaddr); 272 void put_idmap_pgtbl(vm_object_t obj); 273 int domain_map_buf(struct dmar_domain *domain, iommu_gaddr_t base, 274 iommu_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags); 275 int domain_unmap_buf(struct dmar_domain *domain, iommu_gaddr_t base, 276 iommu_gaddr_t size, int flags); 277 void domain_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, 278 iommu_gaddr_t size); 279 int domain_alloc_pgtbl(struct dmar_domain *domain); 280 void domain_free_pgtbl(struct dmar_domain *domain); 281 282 int dmar_dev_depth(device_t child); 283 void dmar_dev_path(device_t child, int *busno, void *path1, int depth); 284 285 struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, 286 uint16_t rid, bool id_mapped, bool rmrr_init); 287 struct dmar_ctx *dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid, 288 int dev_domain, int dev_busno, const void *dev_path, int dev_path_len, 289 bool id_mapped, bool rmrr_init); 290 int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx); 291 void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx); 292 void dmar_free_ctx(struct dmar_ctx *ctx); 293 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid); 294 void dmar_domain_unload_entry(struct iommu_map_entry *entry, bool free); 295 void dmar_domain_unload(struct dmar_domain *domain, 296 struct iommu_map_entries_tailq *entries, bool cansleep); 297 void dmar_domain_free_entry(struct iommu_map_entry *entry, bool free); 298 299 void dmar_gas_init_domain(struct dmar_domain *domain); 300 void dmar_gas_fini_domain(struct dmar_domain *domain); 301 struct iommu_map_entry *dmar_gas_alloc_entry(struct dmar_domain *domain, 302 u_int flags); 303 void dmar_gas_free_entry(struct dmar_domain *domain, 304 struct iommu_map_entry *entry); 305 void dmar_gas_free_space(struct dmar_domain *domain, 306 struct iommu_map_entry *entry); 307 int dmar_gas_map(struct dmar_domain *domain, 308 const struct bus_dma_tag_common *common, iommu_gaddr_t size, int offset, 309 u_int eflags, u_int flags, vm_page_t *ma, struct iommu_map_entry **res); 310 void dmar_gas_free_region(struct dmar_domain *domain, 311 struct iommu_map_entry *entry); 312 int dmar_gas_map_region(struct dmar_domain *domain, 313 struct iommu_map_entry *entry, u_int eflags, u_int flags, vm_page_t *ma); 314 int dmar_gas_reserve_region(struct dmar_domain *domain, iommu_gaddr_t start, 315 iommu_gaddr_t end); 316 317 void dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, 318 int dev_busno, const void *dev_path, int dev_path_len, 319 struct iommu_map_entries_tailq *rmrr_entries); 320 int dmar_instantiate_rmrr_ctxs(struct iommu_unit *dmar); 321 322 void dmar_quirks_post_ident(struct dmar_unit *dmar); 323 void dmar_quirks_pre_use(struct iommu_unit *dmar); 324 325 int dmar_init_irt(struct dmar_unit *unit); 326 void dmar_fini_irt(struct dmar_unit *unit); 327 328 void dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno); 329 bool dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno); 330 331 /* Map flags */ 332 #define IOMMU_MF_CANWAIT 0x0001 333 #define IOMMU_MF_CANSPLIT 0x0002 334 #define IOMMU_MF_RMRR 0x0004 335 336 #define DMAR_PGF_WAITOK 0x0001 337 #define DMAR_PGF_ZERO 0x0002 338 #define DMAR_PGF_ALLOC 0x0004 339 #define DMAR_PGF_NOALLOC 0x0008 340 #define DMAR_PGF_OBJL 0x0010 341 342 extern iommu_haddr_t dmar_high; 343 extern int haw; 344 extern int dmar_tbl_pagecnt; 345 extern int dmar_batch_coalesce; 346 extern int dmar_check_free; 347 348 static inline uint32_t 349 dmar_read4(const struct dmar_unit *unit, int reg) 350 { 351 352 return (bus_read_4(unit->regs, reg)); 353 } 354 355 static inline uint64_t 356 dmar_read8(const struct dmar_unit *unit, int reg) 357 { 358 #ifdef __i386__ 359 uint32_t high, low; 360 361 low = bus_read_4(unit->regs, reg); 362 high = bus_read_4(unit->regs, reg + 4); 363 return (low | ((uint64_t)high << 32)); 364 #else 365 return (bus_read_8(unit->regs, reg)); 366 #endif 367 } 368 369 static inline void 370 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val) 371 { 372 373 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) == 374 (unit->hw_gcmd & DMAR_GCMD_TE), 375 ("dmar%d clearing TE 0x%08x 0x%08x", unit->iommu.unit, 376 unit->hw_gcmd, val)); 377 bus_write_4(unit->regs, reg, val); 378 } 379 380 static inline void 381 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val) 382 { 383 384 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write")); 385 #ifdef __i386__ 386 uint32_t high, low; 387 388 low = val; 389 high = val >> 32; 390 bus_write_4(unit->regs, reg, low); 391 bus_write_4(unit->regs, reg + 4, high); 392 #else 393 bus_write_8(unit->regs, reg, val); 394 #endif 395 } 396 397 /* 398 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes 399 * are issued in the correct order. For store, the lower word, 400 * containing the P or R and W bits, is set only after the high word 401 * is written. For clear, the P bit is cleared first, then the high 402 * word is cleared. 403 * 404 * dmar_pte_update updates the pte. For amd64, the update is atomic. 405 * For i386, it first disables the entry by clearing the word 406 * containing the P bit, and then defer to dmar_pte_store. The locked 407 * cmpxchg8b is probably available on any machine having DMAR support, 408 * but interrupt translation table may be mapped uncached. 409 */ 410 static inline void 411 dmar_pte_store1(volatile uint64_t *dst, uint64_t val) 412 { 413 #ifdef __i386__ 414 volatile uint32_t *p; 415 uint32_t hi, lo; 416 417 hi = val >> 32; 418 lo = val; 419 p = (volatile uint32_t *)dst; 420 *(p + 1) = hi; 421 *p = lo; 422 #else 423 *dst = val; 424 #endif 425 } 426 427 static inline void 428 dmar_pte_store(volatile uint64_t *dst, uint64_t val) 429 { 430 431 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx", 432 dst, (uintmax_t)*dst, (uintmax_t)val)); 433 dmar_pte_store1(dst, val); 434 } 435 436 static inline void 437 dmar_pte_update(volatile uint64_t *dst, uint64_t val) 438 { 439 440 #ifdef __i386__ 441 volatile uint32_t *p; 442 443 p = (volatile uint32_t *)dst; 444 *p = 0; 445 #endif 446 dmar_pte_store1(dst, val); 447 } 448 449 static inline void 450 dmar_pte_clear(volatile uint64_t *dst) 451 { 452 #ifdef __i386__ 453 volatile uint32_t *p; 454 455 p = (volatile uint32_t *)dst; 456 *p = 0; 457 *(p + 1) = 0; 458 #else 459 *dst = 0; 460 #endif 461 } 462 463 static inline bool 464 iommu_test_boundary(iommu_gaddr_t start, iommu_gaddr_t size, 465 iommu_gaddr_t boundary) 466 { 467 468 if (boundary == 0) 469 return (true); 470 return (start + size <= ((start + boundary) & ~(boundary - 1))); 471 } 472 473 extern struct timespec dmar_hw_timeout; 474 475 #define DMAR_WAIT_UNTIL(cond) \ 476 { \ 477 struct timespec last, curr; \ 478 bool forever; \ 479 \ 480 if (dmar_hw_timeout.tv_sec == 0 && \ 481 dmar_hw_timeout.tv_nsec == 0) { \ 482 forever = true; \ 483 } else { \ 484 forever = false; \ 485 nanouptime(&curr); \ 486 timespecadd(&curr, &dmar_hw_timeout, &last); \ 487 } \ 488 for (;;) { \ 489 if (cond) { \ 490 error = 0; \ 491 break; \ 492 } \ 493 nanouptime(&curr); \ 494 if (!forever && timespeccmp(&last, &curr, <)) { \ 495 error = ETIMEDOUT; \ 496 break; \ 497 } \ 498 cpu_spinwait(); \ 499 } \ 500 } 501 502 #ifdef INVARIANTS 503 #define TD_PREP_PINNED_ASSERT \ 504 int old_td_pinned; \ 505 old_td_pinned = curthread->td_pinned 506 #define TD_PINNED_ASSERT \ 507 KASSERT(curthread->td_pinned == old_td_pinned, \ 508 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \ 509 old_td_pinned, __FILE__, __LINE__)) 510 #else 511 #define TD_PREP_PINNED_ASSERT 512 #define TD_PINNED_ASSERT 513 #endif 514 515 #endif 516