1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef __X86_IOMMU_INTEL_DMAR_H 32 #define __X86_IOMMU_INTEL_DMAR_H 33 34 #include <dev/iommu/iommu.h> 35 36 struct dmar_unit; 37 38 /* 39 * Locking annotations: 40 * (u) - Protected by iommu unit lock 41 * (d) - Protected by domain lock 42 * (c) - Immutable after initialization 43 */ 44 45 /* 46 * The domain abstraction. Most non-constant members of the domain 47 * are protected by owning dmar unit lock, not by the domain lock. 48 * Most important, the dmar lock protects the contexts list. 49 * 50 * The domain lock protects the address map for the domain, and list 51 * of unload entries delayed. 52 * 53 * Page tables pages and pages content is protected by the vm object 54 * lock pgtbl_obj, which contains the page tables pages. 55 */ 56 struct dmar_domain { 57 struct iommu_domain iodom; 58 int domain; /* (c) DID, written in context entry */ 59 int mgaw; /* (c) Real max address width */ 60 int agaw; /* (c) Adjusted guest address width */ 61 int pglvl; /* (c) The pagelevel */ 62 int awlvl; /* (c) The pagelevel as the bitmask, 63 to set in context entry */ 64 u_int ctx_cnt; /* (u) Number of contexts owned */ 65 u_int refs; /* (u) Refs, including ctx */ 66 struct dmar_unit *dmar; /* (c) */ 67 LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */ 68 vm_object_t pgtbl_obj; /* (c) Page table pages */ 69 u_int batch_no; 70 }; 71 72 struct dmar_ctx { 73 struct iommu_ctx context; 74 uint64_t last_fault_rec[2]; /* Last fault reported */ 75 }; 76 77 #define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj) 78 #define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj) 79 #define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj) 80 #define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \ 81 VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj) 82 83 #define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->iodom.lock) 84 #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->iodom.lock) 85 #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->iodom.lock, MA_OWNED) 86 87 #define DMAR2IOMMU(dmar) (&((dmar)->iommu)) 88 #define IOMMU2DMAR(dmar) \ 89 __containerof((dmar), struct dmar_unit, iommu) 90 91 #define DOM2IODOM(domain) (&((domain)->iodom)) 92 #define IODOM2DOM(domain) \ 93 __containerof((domain), struct dmar_domain, iodom) 94 95 #define CTX2IOCTX(ctx) (&((ctx)->context)) 96 #define IOCTX2CTX(ctx) \ 97 __containerof((ctx), struct dmar_ctx, context) 98 99 #define CTX2DOM(ctx) IODOM2DOM((ctx)->context.domain) 100 #define CTX2DMAR(ctx) (CTX2DOM(ctx)->dmar) 101 #define DOM2DMAR(domain) ((domain)->dmar) 102 103 #define DMAR_INTR_FAULT 0 104 #define DMAR_INTR_QI 1 105 #define DMAR_INTR_TOTAL 2 106 107 struct dmar_unit { 108 struct iommu_unit iommu; 109 struct x86_unit_common x86c; 110 uint16_t segment; 111 uint64_t base; 112 int memdomain; 113 114 /* Resources */ 115 int reg_rid; 116 struct resource *regs; 117 118 /* Hardware registers cache */ 119 uint32_t hw_ver; 120 uint64_t hw_cap; 121 uint64_t hw_ecap; 122 uint32_t hw_gcmd; 123 124 /* Data for being a dmar */ 125 LIST_HEAD(, dmar_domain) domains; 126 struct unrhdr *domids; 127 vm_object_t ctx_obj; 128 u_int barrier_flags; 129 130 /* Fault handler data */ 131 struct mtx fault_lock; 132 uint64_t *fault_log; 133 int fault_log_head; 134 int fault_log_tail; 135 int fault_log_size; 136 struct task fault_task; 137 struct taskqueue *fault_taskqueue; 138 139 /* QI */ 140 int qi_enabled; 141 142 /* IR */ 143 int ir_enabled; 144 vm_paddr_t irt_phys; 145 dmar_irte_t *irt; 146 u_int irte_cnt; 147 vmem_t *irtids; 148 }; 149 150 #define DMAR_LOCK(dmar) mtx_lock(&DMAR2IOMMU(dmar)->lock) 151 #define DMAR_UNLOCK(dmar) mtx_unlock(&DMAR2IOMMU(dmar)->lock) 152 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&DMAR2IOMMU(dmar)->lock, MA_OWNED) 153 154 #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) 155 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) 156 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) 157 158 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 159 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 160 #define DMAR_X2APIC(dmar) \ 161 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0) 162 163 /* Barrier ids */ 164 #define DMAR_BARRIER_RMRR 0 165 #define DMAR_BARRIER_USEQ 1 166 167 SYSCTL_DECL(_hw_iommu_dmar); 168 169 struct dmar_unit *dmar_find(device_t dev, bool verbose); 170 struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid); 171 struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid); 172 173 u_int dmar_nd2mask(u_int nd); 174 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl); 175 int domain_set_agaw(struct dmar_domain *domain, int mgaw); 176 int dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, 177 bool allow_less); 178 int domain_is_sp_lvl(struct dmar_domain *domain, int lvl); 179 iommu_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl); 180 int calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size, 181 iommu_gaddr_t *isizep); 182 int dmar_load_root_entry_ptr(struct dmar_unit *unit); 183 int dmar_inv_ctx_glob(struct dmar_unit *unit); 184 int dmar_inv_iotlb_glob(struct dmar_unit *unit); 185 int dmar_flush_write_bufs(struct dmar_unit *unit); 186 void dmar_flush_pte_to_ram(struct dmar_unit *unit, iommu_pte_t *dst); 187 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst); 188 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst); 189 int dmar_disable_protected_regions(struct dmar_unit *unit); 190 int dmar_enable_translation(struct dmar_unit *unit); 191 int dmar_disable_translation(struct dmar_unit *unit); 192 int dmar_load_irt_ptr(struct dmar_unit *unit); 193 int dmar_enable_ir(struct dmar_unit *unit); 194 int dmar_disable_ir(struct dmar_unit *unit); 195 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id); 196 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id); 197 uint64_t dmar_get_timeout(void); 198 void dmar_update_timeout(uint64_t newval); 199 200 int dmar_fault_intr(void *arg); 201 void dmar_enable_fault_intr(struct iommu_unit *unit); 202 void dmar_disable_fault_intr(struct iommu_unit *unit); 203 int dmar_init_fault_log(struct dmar_unit *unit); 204 void dmar_fini_fault_log(struct dmar_unit *unit); 205 206 int dmar_qi_intr(void *arg); 207 void dmar_enable_qi_intr(struct iommu_unit *unit); 208 void dmar_disable_qi_intr(struct iommu_unit *unit); 209 int dmar_init_qi(struct dmar_unit *unit); 210 void dmar_fini_qi(struct dmar_unit *unit); 211 void dmar_qi_invalidate_locked(struct dmar_domain *domain, 212 struct iommu_map_entry *entry, bool emit_wait); 213 void dmar_qi_invalidate_sync(struct dmar_domain *domain, iommu_gaddr_t start, 214 iommu_gaddr_t size, bool cansleep); 215 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit); 216 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit); 217 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit); 218 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt); 219 220 vm_object_t dmar_get_idmap_pgtbl(struct dmar_domain *domain, 221 iommu_gaddr_t maxaddr); 222 void dmar_put_idmap_pgtbl(vm_object_t obj); 223 void dmar_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, 224 iommu_gaddr_t size); 225 int dmar_domain_alloc_pgtbl(struct dmar_domain *domain); 226 void dmar_domain_free_pgtbl(struct dmar_domain *domain); 227 extern const struct iommu_domain_map_ops dmar_domain_map_ops; 228 229 int dmar_dev_depth(device_t child); 230 void dmar_dev_path(device_t child, int *busno, void *path1, int depth); 231 232 struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, 233 uint16_t rid, bool id_mapped, bool rmrr_init); 234 struct dmar_ctx *dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid, 235 int dev_domain, int dev_busno, const void *dev_path, int dev_path_len, 236 bool id_mapped, bool rmrr_init); 237 int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx); 238 void dmar_free_ctx_locked_method(struct iommu_unit *dmar, 239 struct iommu_ctx *ctx); 240 void dmar_free_ctx_method(struct iommu_ctx *ctx); 241 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid); 242 struct iommu_ctx *dmar_get_ctx(struct iommu_unit *iommu, device_t dev, 243 uint16_t rid, bool id_mapped, bool rmrr_init); 244 void dmar_domain_unload_entry(struct iommu_map_entry *entry, bool free, 245 bool cansleep); 246 void dmar_domain_unload(struct iommu_domain *iodom, 247 struct iommu_map_entries_tailq *entries, bool cansleep); 248 249 void dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, 250 int dev_busno, const void *dev_path, int dev_path_len, 251 struct iommu_map_entries_tailq *rmrr_entries); 252 int dmar_instantiate_rmrr_ctxs(struct iommu_unit *dmar); 253 254 void dmar_quirks_post_ident(struct dmar_unit *dmar); 255 void dmar_quirks_pre_use(struct iommu_unit *dmar); 256 257 int dmar_init_irt(struct dmar_unit *unit); 258 void dmar_fini_irt(struct dmar_unit *unit); 259 int dmar_alloc_msi_intr(device_t src, u_int *cookies, u_int count); 260 int dmar_map_msi_intr(device_t src, u_int cpu, u_int vector, u_int cookie, 261 uint64_t *addr, uint32_t *data); 262 int dmar_unmap_msi_intr(device_t src, u_int cookie); 263 int dmar_map_ioapic_intr(u_int ioapic_id, u_int cpu, u_int vector, bool edge, 264 bool activehi, int irq, u_int *cookie, uint32_t *hi, uint32_t *lo); 265 int dmar_unmap_ioapic_intr(u_int ioapic_id, u_int *cookie); 266 267 extern int haw; 268 extern int dmar_rmrr_enable; 269 270 static inline uint32_t 271 dmar_read4(const struct dmar_unit *unit, int reg) 272 { 273 274 return (bus_read_4(unit->regs, reg)); 275 } 276 277 static inline uint64_t 278 dmar_read8(const struct dmar_unit *unit, int reg) 279 { 280 #ifdef __i386__ 281 uint32_t high, low; 282 283 low = bus_read_4(unit->regs, reg); 284 high = bus_read_4(unit->regs, reg + 4); 285 return (low | ((uint64_t)high << 32)); 286 #else 287 return (bus_read_8(unit->regs, reg)); 288 #endif 289 } 290 291 static inline void 292 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val) 293 { 294 295 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) == 296 (unit->hw_gcmd & DMAR_GCMD_TE), 297 ("dmar%d clearing TE 0x%08x 0x%08x", unit->iommu.unit, 298 unit->hw_gcmd, val)); 299 bus_write_4(unit->regs, reg, val); 300 } 301 302 static inline void 303 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val) 304 { 305 306 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write")); 307 #ifdef __i386__ 308 uint32_t high, low; 309 310 low = val; 311 high = val >> 32; 312 bus_write_4(unit->regs, reg, low); 313 bus_write_4(unit->regs, reg + 4, high); 314 #else 315 bus_write_8(unit->regs, reg, val); 316 #endif 317 } 318 319 /* 320 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes 321 * are issued in the correct order. For store, the lower word, 322 * containing the P or R and W bits, is set only after the high word 323 * is written. For clear, the P bit is cleared first, then the high 324 * word is cleared. 325 * 326 * dmar_pte_update updates the pte. For amd64, the update is atomic. 327 * For i386, it first disables the entry by clearing the word 328 * containing the P bit, and then defer to dmar_pte_store. The locked 329 * cmpxchg8b is probably available on any machine having DMAR support, 330 * but interrupt translation table may be mapped uncached. 331 */ 332 static inline void 333 dmar_pte_store1(volatile uint64_t *dst, uint64_t val) 334 { 335 #ifdef __i386__ 336 volatile uint32_t *p; 337 uint32_t hi, lo; 338 339 hi = val >> 32; 340 lo = val; 341 p = (volatile uint32_t *)dst; 342 *(p + 1) = hi; 343 *p = lo; 344 #else 345 *dst = val; 346 #endif 347 } 348 349 static inline void 350 dmar_pte_store(volatile uint64_t *dst, uint64_t val) 351 { 352 353 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx", 354 dst, (uintmax_t)*dst, (uintmax_t)val)); 355 dmar_pte_store1(dst, val); 356 } 357 358 static inline void 359 dmar_pte_update(volatile uint64_t *dst, uint64_t val) 360 { 361 362 #ifdef __i386__ 363 volatile uint32_t *p; 364 365 p = (volatile uint32_t *)dst; 366 *p = 0; 367 #endif 368 dmar_pte_store1(dst, val); 369 } 370 371 static inline void 372 dmar_pte_clear(volatile uint64_t *dst) 373 { 374 #ifdef __i386__ 375 volatile uint32_t *p; 376 377 p = (volatile uint32_t *)dst; 378 *p = 0; 379 *(p + 1) = 0; 380 #else 381 *dst = 0; 382 #endif 383 } 384 385 extern struct timespec dmar_hw_timeout; 386 387 #define DMAR_WAIT_UNTIL(cond) \ 388 { \ 389 struct timespec last, curr; \ 390 bool forever; \ 391 \ 392 if (dmar_hw_timeout.tv_sec == 0 && \ 393 dmar_hw_timeout.tv_nsec == 0) { \ 394 forever = true; \ 395 } else { \ 396 forever = false; \ 397 nanouptime(&curr); \ 398 timespecadd(&curr, &dmar_hw_timeout, &last); \ 399 } \ 400 for (;;) { \ 401 if (cond) { \ 402 error = 0; \ 403 break; \ 404 } \ 405 nanouptime(&curr); \ 406 if (!forever && timespeccmp(&last, &curr, <)) { \ 407 error = ETIMEDOUT; \ 408 break; \ 409 } \ 410 cpu_spinwait(); \ 411 } \ 412 } 413 414 #ifdef INVARIANTS 415 #define TD_PREP_PINNED_ASSERT \ 416 int old_td_pinned; \ 417 old_td_pinned = curthread->td_pinned 418 #define TD_PINNED_ASSERT \ 419 KASSERT(curthread->td_pinned == old_td_pinned, \ 420 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \ 421 old_td_pinned, __FILE__, __LINE__)) 422 #else 423 #define TD_PREP_PINNED_ASSERT 424 #define TD_PINNED_ASSERT 425 #endif 426 427 #endif 428