1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef __X86_IOMMU_INTEL_DMAR_H 32 #define __X86_IOMMU_INTEL_DMAR_H 33 34 #include <dev/iommu/iommu.h> 35 36 struct dmar_unit; 37 38 /* 39 * Locking annotations: 40 * (u) - Protected by iommu unit lock 41 * (d) - Protected by domain lock 42 * (c) - Immutable after initialization 43 */ 44 45 /* 46 * The domain abstraction. Most non-constant members of the domain 47 * are protected by owning dmar unit lock, not by the domain lock. 48 * Most important, the dmar lock protects the contexts list. 49 * 50 * The domain lock protects the address map for the domain, and list 51 * of unload entries delayed. 52 * 53 * Page tables pages and pages content is protected by the vm object 54 * lock pgtbl_obj, which contains the page tables pages. 55 */ 56 struct dmar_domain { 57 struct iommu_domain iodom; 58 int domain; /* (c) DID, written in context entry */ 59 int mgaw; /* (c) Real max address width */ 60 int agaw; /* (c) Adjusted guest address width */ 61 int pglvl; /* (c) The pagelevel */ 62 int awlvl; /* (c) The pagelevel as the bitmask, 63 to set in context entry */ 64 u_int ctx_cnt; /* (u) Number of contexts owned */ 65 u_int refs; /* (u) Refs, including ctx */ 66 struct dmar_unit *dmar; /* (c) */ 67 LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */ 68 LIST_HEAD(, dmar_ctx) contexts; /* (u) */ 69 vm_object_t pgtbl_obj; /* (c) Page table pages */ 70 u_int batch_no; 71 }; 72 73 struct dmar_ctx { 74 struct iommu_ctx context; 75 uint64_t last_fault_rec[2]; /* Last fault reported */ 76 LIST_ENTRY(dmar_ctx) link; /* (u) Member in the domain list */ 77 u_int refs; /* (u) References from tags */ 78 }; 79 80 #define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj) 81 #define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj) 82 #define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj) 83 #define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \ 84 VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj) 85 86 #define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->iodom.lock) 87 #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->iodom.lock) 88 #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->iodom.lock, MA_OWNED) 89 90 #define DMAR2IOMMU(dmar) &((dmar)->iommu) 91 #define IOMMU2DMAR(dmar) \ 92 __containerof((dmar), struct dmar_unit, iommu) 93 94 #define DOM2IODOM(domain) &((domain)->iodom) 95 #define IODOM2DOM(domain) \ 96 __containerof((domain), struct dmar_domain, iodom) 97 98 #define CTX2IOCTX(ctx) &((ctx)->context) 99 #define IOCTX2CTX(ctx) \ 100 __containerof((ctx), struct dmar_ctx, context) 101 102 #define CTX2DOM(ctx) IODOM2DOM((ctx)->context.domain) 103 #define CTX2DMAR(ctx) (CTX2DOM(ctx)->dmar) 104 #define DOM2DMAR(domain) ((domain)->dmar) 105 106 struct dmar_msi_data { 107 int irq; 108 int irq_rid; 109 struct resource *irq_res; 110 void *intr_handle; 111 int (*handler)(void *); 112 int msi_data_reg; 113 int msi_addr_reg; 114 int msi_uaddr_reg; 115 void (*enable_intr)(struct dmar_unit *); 116 void (*disable_intr)(struct dmar_unit *); 117 const char *name; 118 }; 119 120 #define DMAR_INTR_FAULT 0 121 #define DMAR_INTR_QI 1 122 #define DMAR_INTR_TOTAL 2 123 124 struct dmar_unit { 125 struct iommu_unit iommu; 126 device_t dev; 127 uint16_t segment; 128 uint64_t base; 129 130 /* Resources */ 131 int reg_rid; 132 struct resource *regs; 133 134 struct dmar_msi_data intrs[DMAR_INTR_TOTAL]; 135 136 /* Hardware registers cache */ 137 uint32_t hw_ver; 138 uint64_t hw_cap; 139 uint64_t hw_ecap; 140 uint32_t hw_gcmd; 141 142 /* Data for being a dmar */ 143 LIST_HEAD(, dmar_domain) domains; 144 struct unrhdr *domids; 145 vm_object_t ctx_obj; 146 u_int barrier_flags; 147 148 /* Fault handler data */ 149 struct mtx fault_lock; 150 uint64_t *fault_log; 151 int fault_log_head; 152 int fault_log_tail; 153 int fault_log_size; 154 struct task fault_task; 155 struct taskqueue *fault_taskqueue; 156 157 /* QI */ 158 int qi_enabled; 159 char *inv_queue; 160 vm_size_t inv_queue_size; 161 uint32_t inv_queue_avail; 162 uint32_t inv_queue_tail; 163 volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait 164 descr completion */ 165 uint64_t inv_waitd_seq_hw_phys; 166 uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */ 167 u_int inv_waitd_gen; /* seq number generation AKA seq overflows */ 168 u_int inv_seq_waiters; /* count of waiters for seq */ 169 u_int inv_queue_full; /* informational counter */ 170 171 /* IR */ 172 int ir_enabled; 173 vm_paddr_t irt_phys; 174 dmar_irte_t *irt; 175 u_int irte_cnt; 176 vmem_t *irtids; 177 178 /* 179 * Delayed freeing of map entries queue processing: 180 * 181 * tlb_flush_head and tlb_flush_tail are used to implement a FIFO 182 * queue that supports concurrent dequeues and enqueues. However, 183 * there can only be a single dequeuer (accessing tlb_flush_head) and 184 * a single enqueuer (accessing tlb_flush_tail) at a time. Since the 185 * unit's qi_task is the only dequeuer, it can access tlb_flush_head 186 * without any locking. In contrast, there may be multiple enqueuers, 187 * so the enqueuers acquire the iommu unit lock to serialize their 188 * accesses to tlb_flush_tail. 189 * 190 * In this FIFO queue implementation, the key to enabling concurrent 191 * dequeues and enqueues is that the dequeuer never needs to access 192 * tlb_flush_tail and the enqueuer never needs to access 193 * tlb_flush_head. In particular, tlb_flush_head and tlb_flush_tail 194 * are never NULL, so neither a dequeuer nor an enqueuer ever needs to 195 * update both. Instead, tlb_flush_head always points to a "zombie" 196 * struct, which previously held the last dequeued item. Thus, the 197 * zombie's next field actually points to the struct holding the first 198 * item in the queue. When an item is dequeued, the current zombie is 199 * finally freed, and the struct that held the just dequeued item 200 * becomes the new zombie. When the queue is empty, tlb_flush_tail 201 * also points to the zombie. 202 */ 203 struct iommu_map_entry *tlb_flush_head; 204 struct iommu_map_entry *tlb_flush_tail; 205 struct task qi_task; 206 struct taskqueue *qi_taskqueue; 207 }; 208 209 #define DMAR_LOCK(dmar) mtx_lock(&(dmar)->iommu.lock) 210 #define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->iommu.lock) 211 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->iommu.lock, MA_OWNED) 212 213 #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) 214 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) 215 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) 216 217 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 218 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 219 #define DMAR_X2APIC(dmar) \ 220 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0) 221 222 /* Barrier ids */ 223 #define DMAR_BARRIER_RMRR 0 224 #define DMAR_BARRIER_USEQ 1 225 226 struct dmar_unit *dmar_find(device_t dev, bool verbose); 227 struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid); 228 struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid); 229 230 u_int dmar_nd2mask(u_int nd); 231 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl); 232 int domain_set_agaw(struct dmar_domain *domain, int mgaw); 233 int dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, 234 bool allow_less); 235 vm_pindex_t pglvl_max_pages(int pglvl); 236 int domain_is_sp_lvl(struct dmar_domain *domain, int lvl); 237 iommu_gaddr_t pglvl_page_size(int total_pglvl, int lvl); 238 iommu_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl); 239 int calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size, 240 iommu_gaddr_t *isizep); 241 struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags); 242 void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags); 243 void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 244 struct sf_buf **sf); 245 void dmar_unmap_pgtbl(struct sf_buf *sf); 246 int dmar_load_root_entry_ptr(struct dmar_unit *unit); 247 int dmar_inv_ctx_glob(struct dmar_unit *unit); 248 int dmar_inv_iotlb_glob(struct dmar_unit *unit); 249 int dmar_flush_write_bufs(struct dmar_unit *unit); 250 void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst); 251 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst); 252 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst); 253 int dmar_disable_protected_regions(struct dmar_unit *unit); 254 int dmar_enable_translation(struct dmar_unit *unit); 255 int dmar_disable_translation(struct dmar_unit *unit); 256 int dmar_load_irt_ptr(struct dmar_unit *unit); 257 int dmar_enable_ir(struct dmar_unit *unit); 258 int dmar_disable_ir(struct dmar_unit *unit); 259 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id); 260 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id); 261 uint64_t dmar_get_timeout(void); 262 void dmar_update_timeout(uint64_t newval); 263 264 int dmar_fault_intr(void *arg); 265 void dmar_enable_fault_intr(struct dmar_unit *unit); 266 void dmar_disable_fault_intr(struct dmar_unit *unit); 267 int dmar_init_fault_log(struct dmar_unit *unit); 268 void dmar_fini_fault_log(struct dmar_unit *unit); 269 270 int dmar_qi_intr(void *arg); 271 void dmar_enable_qi_intr(struct dmar_unit *unit); 272 void dmar_disable_qi_intr(struct dmar_unit *unit); 273 int dmar_init_qi(struct dmar_unit *unit); 274 void dmar_fini_qi(struct dmar_unit *unit); 275 void dmar_qi_invalidate_locked(struct dmar_domain *domain, 276 struct iommu_map_entry *entry, bool emit_wait); 277 void dmar_qi_invalidate_sync(struct dmar_domain *domain, iommu_gaddr_t start, 278 iommu_gaddr_t size, bool cansleep); 279 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit); 280 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit); 281 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit); 282 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt); 283 284 vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain, 285 iommu_gaddr_t maxaddr); 286 void put_idmap_pgtbl(vm_object_t obj); 287 void domain_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, 288 iommu_gaddr_t size); 289 int domain_alloc_pgtbl(struct dmar_domain *domain); 290 void domain_free_pgtbl(struct dmar_domain *domain); 291 extern const struct iommu_domain_map_ops dmar_domain_map_ops; 292 293 int dmar_dev_depth(device_t child); 294 void dmar_dev_path(device_t child, int *busno, void *path1, int depth); 295 296 struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, 297 uint16_t rid, bool id_mapped, bool rmrr_init); 298 struct dmar_ctx *dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid, 299 int dev_domain, int dev_busno, const void *dev_path, int dev_path_len, 300 bool id_mapped, bool rmrr_init); 301 int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx); 302 void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx); 303 void dmar_free_ctx(struct dmar_ctx *ctx); 304 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid); 305 void dmar_domain_free_entry(struct iommu_map_entry *entry, bool free); 306 307 void dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, 308 int dev_busno, const void *dev_path, int dev_path_len, 309 struct iommu_map_entries_tailq *rmrr_entries); 310 int dmar_instantiate_rmrr_ctxs(struct iommu_unit *dmar); 311 312 void dmar_quirks_post_ident(struct dmar_unit *dmar); 313 void dmar_quirks_pre_use(struct iommu_unit *dmar); 314 315 int dmar_init_irt(struct dmar_unit *unit); 316 void dmar_fini_irt(struct dmar_unit *unit); 317 318 extern iommu_haddr_t dmar_high; 319 extern int haw; 320 extern int dmar_tbl_pagecnt; 321 extern int dmar_batch_coalesce; 322 extern int dmar_rmrr_enable; 323 324 static inline uint32_t 325 dmar_read4(const struct dmar_unit *unit, int reg) 326 { 327 328 return (bus_read_4(unit->regs, reg)); 329 } 330 331 static inline uint64_t 332 dmar_read8(const struct dmar_unit *unit, int reg) 333 { 334 #ifdef __i386__ 335 uint32_t high, low; 336 337 low = bus_read_4(unit->regs, reg); 338 high = bus_read_4(unit->regs, reg + 4); 339 return (low | ((uint64_t)high << 32)); 340 #else 341 return (bus_read_8(unit->regs, reg)); 342 #endif 343 } 344 345 static inline void 346 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val) 347 { 348 349 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) == 350 (unit->hw_gcmd & DMAR_GCMD_TE), 351 ("dmar%d clearing TE 0x%08x 0x%08x", unit->iommu.unit, 352 unit->hw_gcmd, val)); 353 bus_write_4(unit->regs, reg, val); 354 } 355 356 static inline void 357 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val) 358 { 359 360 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write")); 361 #ifdef __i386__ 362 uint32_t high, low; 363 364 low = val; 365 high = val >> 32; 366 bus_write_4(unit->regs, reg, low); 367 bus_write_4(unit->regs, reg + 4, high); 368 #else 369 bus_write_8(unit->regs, reg, val); 370 #endif 371 } 372 373 /* 374 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes 375 * are issued in the correct order. For store, the lower word, 376 * containing the P or R and W bits, is set only after the high word 377 * is written. For clear, the P bit is cleared first, then the high 378 * word is cleared. 379 * 380 * dmar_pte_update updates the pte. For amd64, the update is atomic. 381 * For i386, it first disables the entry by clearing the word 382 * containing the P bit, and then defer to dmar_pte_store. The locked 383 * cmpxchg8b is probably available on any machine having DMAR support, 384 * but interrupt translation table may be mapped uncached. 385 */ 386 static inline void 387 dmar_pte_store1(volatile uint64_t *dst, uint64_t val) 388 { 389 #ifdef __i386__ 390 volatile uint32_t *p; 391 uint32_t hi, lo; 392 393 hi = val >> 32; 394 lo = val; 395 p = (volatile uint32_t *)dst; 396 *(p + 1) = hi; 397 *p = lo; 398 #else 399 *dst = val; 400 #endif 401 } 402 403 static inline void 404 dmar_pte_store(volatile uint64_t *dst, uint64_t val) 405 { 406 407 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx", 408 dst, (uintmax_t)*dst, (uintmax_t)val)); 409 dmar_pte_store1(dst, val); 410 } 411 412 static inline void 413 dmar_pte_update(volatile uint64_t *dst, uint64_t val) 414 { 415 416 #ifdef __i386__ 417 volatile uint32_t *p; 418 419 p = (volatile uint32_t *)dst; 420 *p = 0; 421 #endif 422 dmar_pte_store1(dst, val); 423 } 424 425 static inline void 426 dmar_pte_clear(volatile uint64_t *dst) 427 { 428 #ifdef __i386__ 429 volatile uint32_t *p; 430 431 p = (volatile uint32_t *)dst; 432 *p = 0; 433 *(p + 1) = 0; 434 #else 435 *dst = 0; 436 #endif 437 } 438 439 extern struct timespec dmar_hw_timeout; 440 441 #define DMAR_WAIT_UNTIL(cond) \ 442 { \ 443 struct timespec last, curr; \ 444 bool forever; \ 445 \ 446 if (dmar_hw_timeout.tv_sec == 0 && \ 447 dmar_hw_timeout.tv_nsec == 0) { \ 448 forever = true; \ 449 } else { \ 450 forever = false; \ 451 nanouptime(&curr); \ 452 timespecadd(&curr, &dmar_hw_timeout, &last); \ 453 } \ 454 for (;;) { \ 455 if (cond) { \ 456 error = 0; \ 457 break; \ 458 } \ 459 nanouptime(&curr); \ 460 if (!forever && timespeccmp(&last, &curr, <)) { \ 461 error = ETIMEDOUT; \ 462 break; \ 463 } \ 464 cpu_spinwait(); \ 465 } \ 466 } 467 468 #ifdef INVARIANTS 469 #define TD_PREP_PINNED_ASSERT \ 470 int old_td_pinned; \ 471 old_td_pinned = curthread->td_pinned 472 #define TD_PINNED_ASSERT \ 473 KASSERT(curthread->td_pinned == old_td_pinned, \ 474 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \ 475 old_td_pinned, __FILE__, __LINE__)) 476 #else 477 #define TD_PREP_PINNED_ASSERT 478 #define TD_PINNED_ASSERT 479 #endif 480 481 #endif 482