1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef __X86_IOMMU_INTEL_DMAR_H 32 #define __X86_IOMMU_INTEL_DMAR_H 33 34 #include <dev/iommu/iommu.h> 35 36 struct dmar_unit; 37 38 /* 39 * Locking annotations: 40 * (u) - Protected by iommu unit lock 41 * (d) - Protected by domain lock 42 * (c) - Immutable after initialization 43 */ 44 45 /* 46 * The domain abstraction. Most non-constant members of the domain 47 * are protected by owning dmar unit lock, not by the domain lock. 48 * Most important, the dmar lock protects the contexts list. 49 * 50 * The domain lock protects the address map for the domain, and list 51 * of unload entries delayed. 52 * 53 * Page tables pages and pages content is protected by the vm object 54 * lock pgtbl_obj, which contains the page tables pages. 55 */ 56 struct dmar_domain { 57 struct iommu_domain iodom; 58 int domain; /* (c) DID, written in context entry */ 59 int mgaw; /* (c) Real max address width */ 60 int agaw; /* (c) Adjusted guest address width */ 61 int pglvl; /* (c) The pagelevel */ 62 int awlvl; /* (c) The pagelevel as the bitmask, 63 to set in context entry */ 64 u_int ctx_cnt; /* (u) Number of contexts owned */ 65 u_int refs; /* (u) Refs, including ctx */ 66 struct dmar_unit *dmar; /* (c) */ 67 LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */ 68 LIST_HEAD(, dmar_ctx) contexts; /* (u) */ 69 vm_object_t pgtbl_obj; /* (c) Page table pages */ 70 u_int batch_no; 71 }; 72 73 struct dmar_ctx { 74 struct iommu_ctx context; 75 uint64_t last_fault_rec[2]; /* Last fault reported */ 76 LIST_ENTRY(dmar_ctx) link; /* (u) Member in the domain list */ 77 u_int refs; /* (u) References from tags */ 78 }; 79 80 #define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj) 81 #define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj) 82 #define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj) 83 #define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \ 84 VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj) 85 86 #define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->iodom.lock) 87 #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->iodom.lock) 88 #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->iodom.lock, MA_OWNED) 89 90 #define DMAR2IOMMU(dmar) (&((dmar)->iommu)) 91 #define IOMMU2DMAR(dmar) \ 92 __containerof((dmar), struct dmar_unit, iommu) 93 94 #define DOM2IODOM(domain) (&((domain)->iodom)) 95 #define IODOM2DOM(domain) \ 96 __containerof((domain), struct dmar_domain, iodom) 97 98 #define CTX2IOCTX(ctx) (&((ctx)->context)) 99 #define IOCTX2CTX(ctx) \ 100 __containerof((ctx), struct dmar_ctx, context) 101 102 #define CTX2DOM(ctx) IODOM2DOM((ctx)->context.domain) 103 #define CTX2DMAR(ctx) (CTX2DOM(ctx)->dmar) 104 #define DOM2DMAR(domain) ((domain)->dmar) 105 106 #define DMAR_INTR_FAULT 0 107 #define DMAR_INTR_QI 1 108 #define DMAR_INTR_TOTAL 2 109 110 struct dmar_unit { 111 struct iommu_unit iommu; 112 struct x86_unit_common x86c; 113 uint16_t segment; 114 uint64_t base; 115 116 /* Resources */ 117 int reg_rid; 118 struct resource *regs; 119 120 /* Hardware registers cache */ 121 uint32_t hw_ver; 122 uint64_t hw_cap; 123 uint64_t hw_ecap; 124 uint32_t hw_gcmd; 125 126 /* Data for being a dmar */ 127 LIST_HEAD(, dmar_domain) domains; 128 struct unrhdr *domids; 129 vm_object_t ctx_obj; 130 u_int barrier_flags; 131 132 /* Fault handler data */ 133 struct mtx fault_lock; 134 uint64_t *fault_log; 135 int fault_log_head; 136 int fault_log_tail; 137 int fault_log_size; 138 struct task fault_task; 139 struct taskqueue *fault_taskqueue; 140 141 /* QI */ 142 int qi_enabled; 143 144 /* IR */ 145 int ir_enabled; 146 vm_paddr_t irt_phys; 147 dmar_irte_t *irt; 148 u_int irte_cnt; 149 vmem_t *irtids; 150 }; 151 152 #define DMAR_LOCK(dmar) mtx_lock(&DMAR2IOMMU(dmar)->lock) 153 #define DMAR_UNLOCK(dmar) mtx_unlock(&DMAR2IOMMU(dmar)->lock) 154 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&DMAR2IOMMU(dmar)->lock, MA_OWNED) 155 156 #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) 157 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) 158 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) 159 160 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 161 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 162 #define DMAR_X2APIC(dmar) \ 163 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0) 164 165 /* Barrier ids */ 166 #define DMAR_BARRIER_RMRR 0 167 #define DMAR_BARRIER_USEQ 1 168 169 SYSCTL_DECL(_hw_iommu_dmar); 170 171 struct dmar_unit *dmar_find(device_t dev, bool verbose); 172 struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid); 173 struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid); 174 175 u_int dmar_nd2mask(u_int nd); 176 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl); 177 int domain_set_agaw(struct dmar_domain *domain, int mgaw); 178 int dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, 179 bool allow_less); 180 int domain_is_sp_lvl(struct dmar_domain *domain, int lvl); 181 iommu_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl); 182 int calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size, 183 iommu_gaddr_t *isizep); 184 int dmar_load_root_entry_ptr(struct dmar_unit *unit); 185 int dmar_inv_ctx_glob(struct dmar_unit *unit); 186 int dmar_inv_iotlb_glob(struct dmar_unit *unit); 187 int dmar_flush_write_bufs(struct dmar_unit *unit); 188 void dmar_flush_pte_to_ram(struct dmar_unit *unit, iommu_pte_t *dst); 189 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst); 190 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst); 191 int dmar_disable_protected_regions(struct dmar_unit *unit); 192 int dmar_enable_translation(struct dmar_unit *unit); 193 int dmar_disable_translation(struct dmar_unit *unit); 194 int dmar_load_irt_ptr(struct dmar_unit *unit); 195 int dmar_enable_ir(struct dmar_unit *unit); 196 int dmar_disable_ir(struct dmar_unit *unit); 197 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id); 198 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id); 199 uint64_t dmar_get_timeout(void); 200 void dmar_update_timeout(uint64_t newval); 201 202 int dmar_fault_intr(void *arg); 203 void dmar_enable_fault_intr(struct iommu_unit *unit); 204 void dmar_disable_fault_intr(struct iommu_unit *unit); 205 int dmar_init_fault_log(struct dmar_unit *unit); 206 void dmar_fini_fault_log(struct dmar_unit *unit); 207 208 int dmar_qi_intr(void *arg); 209 void dmar_enable_qi_intr(struct iommu_unit *unit); 210 void dmar_disable_qi_intr(struct iommu_unit *unit); 211 int dmar_init_qi(struct dmar_unit *unit); 212 void dmar_fini_qi(struct dmar_unit *unit); 213 void dmar_qi_invalidate_locked(struct dmar_domain *domain, 214 struct iommu_map_entry *entry, bool emit_wait); 215 void dmar_qi_invalidate_sync(struct dmar_domain *domain, iommu_gaddr_t start, 216 iommu_gaddr_t size, bool cansleep); 217 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit); 218 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit); 219 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit); 220 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt); 221 222 vm_object_t dmar_get_idmap_pgtbl(struct dmar_domain *domain, 223 iommu_gaddr_t maxaddr); 224 void dmar_put_idmap_pgtbl(vm_object_t obj); 225 void dmar_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, 226 iommu_gaddr_t size); 227 int dmar_domain_alloc_pgtbl(struct dmar_domain *domain); 228 void dmar_domain_free_pgtbl(struct dmar_domain *domain); 229 extern const struct iommu_domain_map_ops dmar_domain_map_ops; 230 231 int dmar_dev_depth(device_t child); 232 void dmar_dev_path(device_t child, int *busno, void *path1, int depth); 233 234 struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, 235 uint16_t rid, bool id_mapped, bool rmrr_init); 236 struct dmar_ctx *dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid, 237 int dev_domain, int dev_busno, const void *dev_path, int dev_path_len, 238 bool id_mapped, bool rmrr_init); 239 int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx); 240 void dmar_free_ctx_locked_method(struct iommu_unit *dmar, 241 struct iommu_ctx *ctx); 242 void dmar_free_ctx_method(struct iommu_ctx *ctx); 243 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid); 244 struct iommu_ctx *dmar_get_ctx(struct iommu_unit *iommu, device_t dev, 245 uint16_t rid, bool id_mapped, bool rmrr_init); 246 void dmar_domain_unload_entry(struct iommu_map_entry *entry, bool free, 247 bool cansleep); 248 void dmar_domain_unload(struct iommu_domain *iodom, 249 struct iommu_map_entries_tailq *entries, bool cansleep); 250 251 void dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, 252 int dev_busno, const void *dev_path, int dev_path_len, 253 struct iommu_map_entries_tailq *rmrr_entries); 254 int dmar_instantiate_rmrr_ctxs(struct iommu_unit *dmar); 255 256 void dmar_quirks_post_ident(struct dmar_unit *dmar); 257 void dmar_quirks_pre_use(struct iommu_unit *dmar); 258 259 int dmar_init_irt(struct dmar_unit *unit); 260 void dmar_fini_irt(struct dmar_unit *unit); 261 int dmar_alloc_msi_intr(device_t src, u_int *cookies, u_int count); 262 int dmar_map_msi_intr(device_t src, u_int cpu, u_int vector, u_int cookie, 263 uint64_t *addr, uint32_t *data); 264 int dmar_unmap_msi_intr(device_t src, u_int cookie); 265 int dmar_map_ioapic_intr(u_int ioapic_id, u_int cpu, u_int vector, bool edge, 266 bool activehi, int irq, u_int *cookie, uint32_t *hi, uint32_t *lo); 267 int dmar_unmap_ioapic_intr(u_int ioapic_id, u_int *cookie); 268 269 extern int haw; 270 extern int dmar_rmrr_enable; 271 272 static inline uint32_t 273 dmar_read4(const struct dmar_unit *unit, int reg) 274 { 275 276 return (bus_read_4(unit->regs, reg)); 277 } 278 279 static inline uint64_t 280 dmar_read8(const struct dmar_unit *unit, int reg) 281 { 282 #ifdef __i386__ 283 uint32_t high, low; 284 285 low = bus_read_4(unit->regs, reg); 286 high = bus_read_4(unit->regs, reg + 4); 287 return (low | ((uint64_t)high << 32)); 288 #else 289 return (bus_read_8(unit->regs, reg)); 290 #endif 291 } 292 293 static inline void 294 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val) 295 { 296 297 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) == 298 (unit->hw_gcmd & DMAR_GCMD_TE), 299 ("dmar%d clearing TE 0x%08x 0x%08x", unit->iommu.unit, 300 unit->hw_gcmd, val)); 301 bus_write_4(unit->regs, reg, val); 302 } 303 304 static inline void 305 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val) 306 { 307 308 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write")); 309 #ifdef __i386__ 310 uint32_t high, low; 311 312 low = val; 313 high = val >> 32; 314 bus_write_4(unit->regs, reg, low); 315 bus_write_4(unit->regs, reg + 4, high); 316 #else 317 bus_write_8(unit->regs, reg, val); 318 #endif 319 } 320 321 /* 322 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes 323 * are issued in the correct order. For store, the lower word, 324 * containing the P or R and W bits, is set only after the high word 325 * is written. For clear, the P bit is cleared first, then the high 326 * word is cleared. 327 * 328 * dmar_pte_update updates the pte. For amd64, the update is atomic. 329 * For i386, it first disables the entry by clearing the word 330 * containing the P bit, and then defer to dmar_pte_store. The locked 331 * cmpxchg8b is probably available on any machine having DMAR support, 332 * but interrupt translation table may be mapped uncached. 333 */ 334 static inline void 335 dmar_pte_store1(volatile uint64_t *dst, uint64_t val) 336 { 337 #ifdef __i386__ 338 volatile uint32_t *p; 339 uint32_t hi, lo; 340 341 hi = val >> 32; 342 lo = val; 343 p = (volatile uint32_t *)dst; 344 *(p + 1) = hi; 345 *p = lo; 346 #else 347 *dst = val; 348 #endif 349 } 350 351 static inline void 352 dmar_pte_store(volatile uint64_t *dst, uint64_t val) 353 { 354 355 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx", 356 dst, (uintmax_t)*dst, (uintmax_t)val)); 357 dmar_pte_store1(dst, val); 358 } 359 360 static inline void 361 dmar_pte_update(volatile uint64_t *dst, uint64_t val) 362 { 363 364 #ifdef __i386__ 365 volatile uint32_t *p; 366 367 p = (volatile uint32_t *)dst; 368 *p = 0; 369 #endif 370 dmar_pte_store1(dst, val); 371 } 372 373 static inline void 374 dmar_pte_clear(volatile uint64_t *dst) 375 { 376 #ifdef __i386__ 377 volatile uint32_t *p; 378 379 p = (volatile uint32_t *)dst; 380 *p = 0; 381 *(p + 1) = 0; 382 #else 383 *dst = 0; 384 #endif 385 } 386 387 extern struct timespec dmar_hw_timeout; 388 389 #define DMAR_WAIT_UNTIL(cond) \ 390 { \ 391 struct timespec last, curr; \ 392 bool forever; \ 393 \ 394 if (dmar_hw_timeout.tv_sec == 0 && \ 395 dmar_hw_timeout.tv_nsec == 0) { \ 396 forever = true; \ 397 } else { \ 398 forever = false; \ 399 nanouptime(&curr); \ 400 timespecadd(&curr, &dmar_hw_timeout, &last); \ 401 } \ 402 for (;;) { \ 403 if (cond) { \ 404 error = 0; \ 405 break; \ 406 } \ 407 nanouptime(&curr); \ 408 if (!forever && timespeccmp(&last, &curr, <)) { \ 409 error = ETIMEDOUT; \ 410 break; \ 411 } \ 412 cpu_spinwait(); \ 413 } \ 414 } 415 416 #ifdef INVARIANTS 417 #define TD_PREP_PINNED_ASSERT \ 418 int old_td_pinned; \ 419 old_td_pinned = curthread->td_pinned 420 #define TD_PINNED_ASSERT \ 421 KASSERT(curthread->td_pinned == old_td_pinned, \ 422 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \ 423 old_td_pinned, __FILE__, __LINE__)) 424 #else 425 #define TD_PREP_PINNED_ASSERT 426 #define TD_PINNED_ASSERT 427 #endif 428 429 #endif 430