1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef __X86_IOMMU_INTEL_DMAR_H 34 #define __X86_IOMMU_INTEL_DMAR_H 35 36 #include <dev/iommu/iommu.h> 37 38 struct dmar_unit; 39 40 /* 41 * Locking annotations: 42 * (u) - Protected by iommu unit lock 43 * (d) - Protected by domain lock 44 * (c) - Immutable after initialization 45 */ 46 47 /* 48 * The domain abstraction. Most non-constant members of the domain 49 * are protected by owning dmar unit lock, not by the domain lock. 50 * Most important, the dmar lock protects the contexts list. 51 * 52 * The domain lock protects the address map for the domain, and list 53 * of unload entries delayed. 54 * 55 * Page tables pages and pages content is protected by the vm object 56 * lock pgtbl_obj, which contains the page tables pages. 57 */ 58 struct dmar_domain { 59 struct iommu_domain iodom; 60 int domain; /* (c) DID, written in context entry */ 61 int mgaw; /* (c) Real max address width */ 62 int agaw; /* (c) Adjusted guest address width */ 63 int pglvl; /* (c) The pagelevel */ 64 int awlvl; /* (c) The pagelevel as the bitmask, 65 to set in context entry */ 66 u_int ctx_cnt; /* (u) Number of contexts owned */ 67 u_int refs; /* (u) Refs, including ctx */ 68 struct dmar_unit *dmar; /* (c) */ 69 LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */ 70 LIST_HEAD(, dmar_ctx) contexts; /* (u) */ 71 vm_object_t pgtbl_obj; /* (c) Page table pages */ 72 u_int batch_no; 73 }; 74 75 struct dmar_ctx { 76 struct iommu_ctx context; 77 uint64_t last_fault_rec[2]; /* Last fault reported */ 78 LIST_ENTRY(dmar_ctx) link; /* (u) Member in the domain list */ 79 u_int refs; /* (u) References from tags */ 80 }; 81 82 #define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj) 83 #define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj) 84 #define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj) 85 #define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \ 86 VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj) 87 88 #define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->iodom.lock) 89 #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->iodom.lock) 90 #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->iodom.lock, MA_OWNED) 91 92 #define DMAR2IOMMU(dmar) &((dmar)->iommu) 93 #define IOMMU2DMAR(dmar) \ 94 __containerof((dmar), struct dmar_unit, iommu) 95 96 #define DOM2IODOM(domain) &((domain)->iodom) 97 #define IODOM2DOM(domain) \ 98 __containerof((domain), struct dmar_domain, iodom) 99 100 #define CTX2IOCTX(ctx) &((ctx)->context) 101 #define IOCTX2CTX(ctx) \ 102 __containerof((ctx), struct dmar_ctx, context) 103 104 #define CTX2DOM(ctx) IODOM2DOM((ctx)->context.domain) 105 #define CTX2DMAR(ctx) (CTX2DOM(ctx)->dmar) 106 #define DOM2DMAR(domain) ((domain)->dmar) 107 108 struct dmar_msi_data { 109 int irq; 110 int irq_rid; 111 struct resource *irq_res; 112 void *intr_handle; 113 int (*handler)(void *); 114 int msi_data_reg; 115 int msi_addr_reg; 116 int msi_uaddr_reg; 117 void (*enable_intr)(struct dmar_unit *); 118 void (*disable_intr)(struct dmar_unit *); 119 const char *name; 120 }; 121 122 #define DMAR_INTR_FAULT 0 123 #define DMAR_INTR_QI 1 124 #define DMAR_INTR_TOTAL 2 125 126 struct dmar_unit { 127 struct iommu_unit iommu; 128 device_t dev; 129 uint16_t segment; 130 uint64_t base; 131 132 /* Resources */ 133 int reg_rid; 134 struct resource *regs; 135 136 struct dmar_msi_data intrs[DMAR_INTR_TOTAL]; 137 138 /* Hardware registers cache */ 139 uint32_t hw_ver; 140 uint64_t hw_cap; 141 uint64_t hw_ecap; 142 uint32_t hw_gcmd; 143 144 /* Data for being a dmar */ 145 LIST_HEAD(, dmar_domain) domains; 146 struct unrhdr *domids; 147 vm_object_t ctx_obj; 148 u_int barrier_flags; 149 150 /* Fault handler data */ 151 struct mtx fault_lock; 152 uint64_t *fault_log; 153 int fault_log_head; 154 int fault_log_tail; 155 int fault_log_size; 156 struct task fault_task; 157 struct taskqueue *fault_taskqueue; 158 159 /* QI */ 160 int qi_enabled; 161 vm_offset_t inv_queue; 162 vm_size_t inv_queue_size; 163 uint32_t inv_queue_avail; 164 uint32_t inv_queue_tail; 165 volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait 166 descr completion */ 167 uint64_t inv_waitd_seq_hw_phys; 168 uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */ 169 u_int inv_waitd_gen; /* seq number generation AKA seq overflows */ 170 u_int inv_seq_waiters; /* count of waiters for seq */ 171 u_int inv_queue_full; /* informational counter */ 172 173 /* IR */ 174 int ir_enabled; 175 vm_paddr_t irt_phys; 176 dmar_irte_t *irt; 177 u_int irte_cnt; 178 vmem_t *irtids; 179 180 /* Delayed freeing of map entries queue processing */ 181 struct iommu_map_entries_tailq tlb_flush_entries; 182 struct task qi_task; 183 struct taskqueue *qi_taskqueue; 184 }; 185 186 #define DMAR_LOCK(dmar) mtx_lock(&(dmar)->iommu.lock) 187 #define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->iommu.lock) 188 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->iommu.lock, MA_OWNED) 189 190 #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock) 191 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock) 192 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) 193 194 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0) 195 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0) 196 #define DMAR_X2APIC(dmar) \ 197 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0) 198 199 /* Barrier ids */ 200 #define DMAR_BARRIER_RMRR 0 201 #define DMAR_BARRIER_USEQ 1 202 203 struct dmar_unit *dmar_find(device_t dev, bool verbose); 204 struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid); 205 struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid); 206 207 u_int dmar_nd2mask(u_int nd); 208 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl); 209 int domain_set_agaw(struct dmar_domain *domain, int mgaw); 210 int dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, 211 bool allow_less); 212 vm_pindex_t pglvl_max_pages(int pglvl); 213 int domain_is_sp_lvl(struct dmar_domain *domain, int lvl); 214 iommu_gaddr_t pglvl_page_size(int total_pglvl, int lvl); 215 iommu_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl); 216 int calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size, 217 iommu_gaddr_t *isizep); 218 struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags); 219 void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags); 220 void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags, 221 struct sf_buf **sf); 222 void dmar_unmap_pgtbl(struct sf_buf *sf); 223 int dmar_load_root_entry_ptr(struct dmar_unit *unit); 224 int dmar_inv_ctx_glob(struct dmar_unit *unit); 225 int dmar_inv_iotlb_glob(struct dmar_unit *unit); 226 int dmar_flush_write_bufs(struct dmar_unit *unit); 227 void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst); 228 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst); 229 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst); 230 int dmar_disable_protected_regions(struct dmar_unit *unit); 231 int dmar_enable_translation(struct dmar_unit *unit); 232 int dmar_disable_translation(struct dmar_unit *unit); 233 int dmar_load_irt_ptr(struct dmar_unit *unit); 234 int dmar_enable_ir(struct dmar_unit *unit); 235 int dmar_disable_ir(struct dmar_unit *unit); 236 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id); 237 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id); 238 uint64_t dmar_get_timeout(void); 239 void dmar_update_timeout(uint64_t newval); 240 241 int dmar_fault_intr(void *arg); 242 void dmar_enable_fault_intr(struct dmar_unit *unit); 243 void dmar_disable_fault_intr(struct dmar_unit *unit); 244 int dmar_init_fault_log(struct dmar_unit *unit); 245 void dmar_fini_fault_log(struct dmar_unit *unit); 246 247 int dmar_qi_intr(void *arg); 248 void dmar_enable_qi_intr(struct dmar_unit *unit); 249 void dmar_disable_qi_intr(struct dmar_unit *unit); 250 int dmar_init_qi(struct dmar_unit *unit); 251 void dmar_fini_qi(struct dmar_unit *unit); 252 void dmar_qi_invalidate_locked(struct dmar_domain *domain, iommu_gaddr_t start, 253 iommu_gaddr_t size, struct iommu_qi_genseq *psec, bool emit_wait); 254 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit); 255 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit); 256 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit); 257 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt); 258 259 vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain, 260 iommu_gaddr_t maxaddr); 261 void put_idmap_pgtbl(vm_object_t obj); 262 void domain_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, 263 iommu_gaddr_t size); 264 int domain_alloc_pgtbl(struct dmar_domain *domain); 265 void domain_free_pgtbl(struct dmar_domain *domain); 266 extern const struct iommu_domain_map_ops dmar_domain_map_ops; 267 268 int dmar_dev_depth(device_t child); 269 void dmar_dev_path(device_t child, int *busno, void *path1, int depth); 270 271 struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, 272 uint16_t rid, bool id_mapped, bool rmrr_init); 273 struct dmar_ctx *dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid, 274 int dev_domain, int dev_busno, const void *dev_path, int dev_path_len, 275 bool id_mapped, bool rmrr_init); 276 int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx); 277 void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx); 278 void dmar_free_ctx(struct dmar_ctx *ctx); 279 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid); 280 void dmar_domain_unload_entry(struct iommu_map_entry *entry, bool free); 281 void dmar_domain_unload(struct dmar_domain *domain, 282 struct iommu_map_entries_tailq *entries, bool cansleep); 283 void dmar_domain_free_entry(struct iommu_map_entry *entry, bool free); 284 285 void dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, 286 int dev_busno, const void *dev_path, int dev_path_len, 287 struct iommu_map_entries_tailq *rmrr_entries); 288 int dmar_instantiate_rmrr_ctxs(struct iommu_unit *dmar); 289 290 void dmar_quirks_post_ident(struct dmar_unit *dmar); 291 void dmar_quirks_pre_use(struct iommu_unit *dmar); 292 293 int dmar_init_irt(struct dmar_unit *unit); 294 void dmar_fini_irt(struct dmar_unit *unit); 295 296 extern iommu_haddr_t dmar_high; 297 extern int haw; 298 extern int dmar_tbl_pagecnt; 299 extern int dmar_batch_coalesce; 300 301 static inline uint32_t 302 dmar_read4(const struct dmar_unit *unit, int reg) 303 { 304 305 return (bus_read_4(unit->regs, reg)); 306 } 307 308 static inline uint64_t 309 dmar_read8(const struct dmar_unit *unit, int reg) 310 { 311 #ifdef __i386__ 312 uint32_t high, low; 313 314 low = bus_read_4(unit->regs, reg); 315 high = bus_read_4(unit->regs, reg + 4); 316 return (low | ((uint64_t)high << 32)); 317 #else 318 return (bus_read_8(unit->regs, reg)); 319 #endif 320 } 321 322 static inline void 323 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val) 324 { 325 326 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) == 327 (unit->hw_gcmd & DMAR_GCMD_TE), 328 ("dmar%d clearing TE 0x%08x 0x%08x", unit->iommu.unit, 329 unit->hw_gcmd, val)); 330 bus_write_4(unit->regs, reg, val); 331 } 332 333 static inline void 334 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val) 335 { 336 337 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write")); 338 #ifdef __i386__ 339 uint32_t high, low; 340 341 low = val; 342 high = val >> 32; 343 bus_write_4(unit->regs, reg, low); 344 bus_write_4(unit->regs, reg + 4, high); 345 #else 346 bus_write_8(unit->regs, reg, val); 347 #endif 348 } 349 350 /* 351 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes 352 * are issued in the correct order. For store, the lower word, 353 * containing the P or R and W bits, is set only after the high word 354 * is written. For clear, the P bit is cleared first, then the high 355 * word is cleared. 356 * 357 * dmar_pte_update updates the pte. For amd64, the update is atomic. 358 * For i386, it first disables the entry by clearing the word 359 * containing the P bit, and then defer to dmar_pte_store. The locked 360 * cmpxchg8b is probably available on any machine having DMAR support, 361 * but interrupt translation table may be mapped uncached. 362 */ 363 static inline void 364 dmar_pte_store1(volatile uint64_t *dst, uint64_t val) 365 { 366 #ifdef __i386__ 367 volatile uint32_t *p; 368 uint32_t hi, lo; 369 370 hi = val >> 32; 371 lo = val; 372 p = (volatile uint32_t *)dst; 373 *(p + 1) = hi; 374 *p = lo; 375 #else 376 *dst = val; 377 #endif 378 } 379 380 static inline void 381 dmar_pte_store(volatile uint64_t *dst, uint64_t val) 382 { 383 384 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx", 385 dst, (uintmax_t)*dst, (uintmax_t)val)); 386 dmar_pte_store1(dst, val); 387 } 388 389 static inline void 390 dmar_pte_update(volatile uint64_t *dst, uint64_t val) 391 { 392 393 #ifdef __i386__ 394 volatile uint32_t *p; 395 396 p = (volatile uint32_t *)dst; 397 *p = 0; 398 #endif 399 dmar_pte_store1(dst, val); 400 } 401 402 static inline void 403 dmar_pte_clear(volatile uint64_t *dst) 404 { 405 #ifdef __i386__ 406 volatile uint32_t *p; 407 408 p = (volatile uint32_t *)dst; 409 *p = 0; 410 *(p + 1) = 0; 411 #else 412 *dst = 0; 413 #endif 414 } 415 416 extern struct timespec dmar_hw_timeout; 417 418 #define DMAR_WAIT_UNTIL(cond) \ 419 { \ 420 struct timespec last, curr; \ 421 bool forever; \ 422 \ 423 if (dmar_hw_timeout.tv_sec == 0 && \ 424 dmar_hw_timeout.tv_nsec == 0) { \ 425 forever = true; \ 426 } else { \ 427 forever = false; \ 428 nanouptime(&curr); \ 429 timespecadd(&curr, &dmar_hw_timeout, &last); \ 430 } \ 431 for (;;) { \ 432 if (cond) { \ 433 error = 0; \ 434 break; \ 435 } \ 436 nanouptime(&curr); \ 437 if (!forever && timespeccmp(&last, &curr, <)) { \ 438 error = ETIMEDOUT; \ 439 break; \ 440 } \ 441 cpu_spinwait(); \ 442 } \ 443 } 444 445 #ifdef INVARIANTS 446 #define TD_PREP_PINNED_ASSERT \ 447 int old_td_pinned; \ 448 old_td_pinned = curthread->td_pinned 449 #define TD_PINNED_ASSERT \ 450 KASSERT(curthread->td_pinned == old_td_pinned, \ 451 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \ 452 old_td_pinned, __FILE__, __LINE__)) 453 #else 454 #define TD_PREP_PINNED_ASSERT 455 #define TD_PINNED_ASSERT 456 #endif 457 458 #endif 459