1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/bus.h> 39 #include <sys/interrupt.h> 40 #include <sys/kernel.h> 41 #include <sys/ktr.h> 42 #include <sys/limits.h> 43 #include <sys/lock.h> 44 #include <sys/memdesc.h> 45 #include <sys/mutex.h> 46 #include <sys/proc.h> 47 #include <sys/rwlock.h> 48 #include <sys/rman.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 #include <sys/uio.h> 53 #include <sys/vmem.h> 54 #include <vm/vm.h> 55 #include <vm/vm_extern.h> 56 #include <vm/vm_kern.h> 57 #include <vm/vm_object.h> 58 #include <vm/vm_page.h> 59 #include <vm/vm_pager.h> 60 #include <vm/vm_map.h> 61 #include <contrib/dev/acpica/include/acpi.h> 62 #include <contrib/dev/acpica/include/accommon.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <machine/atomic.h> 66 #include <machine/bus.h> 67 #include <machine/md_var.h> 68 #include <machine/specialreg.h> 69 #include <x86/include/busdma_impl.h> 70 #include <dev/iommu/busdma_iommu.h> 71 #include <x86/iommu/intel_reg.h> 72 #include <x86/iommu/intel_dmar.h> 73 74 static MALLOC_DEFINE(M_DMAR_CTX, "dmar_ctx", "Intel DMAR Context"); 75 static MALLOC_DEFINE(M_DMAR_DOMAIN, "dmar_dom", "Intel DMAR Domain"); 76 77 static void dmar_domain_unload_task(void *arg, int pending); 78 static void dmar_unref_domain_locked(struct dmar_unit *dmar, 79 struct dmar_domain *domain); 80 static void dmar_domain_destroy(struct dmar_domain *domain); 81 82 static void 83 dmar_ensure_ctx_page(struct dmar_unit *dmar, int bus) 84 { 85 struct sf_buf *sf; 86 dmar_root_entry_t *re; 87 vm_page_t ctxm; 88 89 /* 90 * Allocated context page must be linked. 91 */ 92 ctxm = dmar_pgalloc(dmar->ctx_obj, 1 + bus, IOMMU_PGF_NOALLOC); 93 if (ctxm != NULL) 94 return; 95 96 /* 97 * Page not present, allocate and link. Note that other 98 * thread might execute this sequence in parallel. This 99 * should be safe, because the context entries written by both 100 * threads are equal. 101 */ 102 TD_PREP_PINNED_ASSERT; 103 ctxm = dmar_pgalloc(dmar->ctx_obj, 1 + bus, IOMMU_PGF_ZERO | 104 IOMMU_PGF_WAITOK); 105 re = dmar_map_pgtbl(dmar->ctx_obj, 0, IOMMU_PGF_NOALLOC, &sf); 106 re += bus; 107 dmar_pte_store(&re->r1, DMAR_ROOT_R1_P | (DMAR_ROOT_R1_CTP_MASK & 108 VM_PAGE_TO_PHYS(ctxm))); 109 dmar_flush_root_to_ram(dmar, re); 110 dmar_unmap_pgtbl(sf); 111 TD_PINNED_ASSERT; 112 } 113 114 static dmar_ctx_entry_t * 115 dmar_map_ctx_entry(struct dmar_ctx *ctx, struct sf_buf **sfp) 116 { 117 struct dmar_unit *dmar; 118 dmar_ctx_entry_t *ctxp; 119 120 dmar = (struct dmar_unit *)ctx->context.domain->iommu; 121 122 ctxp = dmar_map_pgtbl(dmar->ctx_obj, 1 + 123 PCI_RID2BUS(ctx->rid), IOMMU_PGF_NOALLOC | IOMMU_PGF_WAITOK, sfp); 124 ctxp += ctx->rid & 0xff; 125 return (ctxp); 126 } 127 128 static void 129 device_tag_init(struct dmar_ctx *ctx, device_t dev) 130 { 131 struct dmar_domain *domain; 132 bus_addr_t maxaddr; 133 134 domain = (struct dmar_domain *)ctx->context.domain; 135 maxaddr = MIN(domain->iodom.end, BUS_SPACE_MAXADDR); 136 ctx->context.tag->common.ref_count = 1; /* Prevent free */ 137 ctx->context.tag->common.impl = &bus_dma_iommu_impl; 138 ctx->context.tag->common.boundary = 0; 139 ctx->context.tag->common.lowaddr = maxaddr; 140 ctx->context.tag->common.highaddr = maxaddr; 141 ctx->context.tag->common.maxsize = maxaddr; 142 ctx->context.tag->common.nsegments = BUS_SPACE_UNRESTRICTED; 143 ctx->context.tag->common.maxsegsz = maxaddr; 144 ctx->context.tag->ctx = (struct iommu_ctx *)ctx; 145 ctx->context.tag->owner = dev; 146 } 147 148 static void 149 ctx_id_entry_init_one(dmar_ctx_entry_t *ctxp, struct dmar_domain *domain, 150 vm_page_t ctx_root) 151 { 152 /* 153 * For update due to move, the store is not atomic. It is 154 * possible that DMAR read upper doubleword, while low 155 * doubleword is not yet updated. The domain id is stored in 156 * the upper doubleword, while the table pointer in the lower. 157 * 158 * There is no good solution, for the same reason it is wrong 159 * to clear P bit in the ctx entry for update. 160 */ 161 dmar_pte_store1(&ctxp->ctx2, DMAR_CTX2_DID(domain->domain) | 162 domain->awlvl); 163 if (ctx_root == NULL) { 164 dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_PASS | DMAR_CTX1_P); 165 } else { 166 dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_UNTR | 167 (DMAR_CTX1_ASR_MASK & VM_PAGE_TO_PHYS(ctx_root)) | 168 DMAR_CTX1_P); 169 } 170 } 171 172 static void 173 ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move, 174 int busno) 175 { 176 struct dmar_unit *unit; 177 struct dmar_domain *domain; 178 vm_page_t ctx_root; 179 int i; 180 181 domain = (struct dmar_domain *)ctx->context.domain; 182 unit = (struct dmar_unit *)domain->iodom.iommu; 183 KASSERT(move || (ctxp->ctx1 == 0 && ctxp->ctx2 == 0), 184 ("dmar%d: initialized ctx entry %d:%d:%d 0x%jx 0x%jx", 185 unit->iommu.unit, busno, pci_get_slot(ctx->context.tag->owner), 186 pci_get_function(ctx->context.tag->owner), 187 ctxp->ctx1, ctxp->ctx2)); 188 189 if ((domain->iodom.flags & IOMMU_DOMAIN_IDMAP) != 0 && 190 (unit->hw_ecap & DMAR_ECAP_PT) != 0) { 191 KASSERT(domain->pgtbl_obj == NULL, 192 ("ctx %p non-null pgtbl_obj", ctx)); 193 ctx_root = NULL; 194 } else { 195 ctx_root = dmar_pgalloc(domain->pgtbl_obj, 0, 196 IOMMU_PGF_NOALLOC); 197 } 198 199 if (iommu_is_buswide_ctx((struct iommu_unit *)unit, busno)) { 200 MPASS(!move); 201 for (i = 0; i <= PCI_BUSMAX; i++) { 202 ctx_id_entry_init_one(&ctxp[i], domain, ctx_root); 203 } 204 } else { 205 ctx_id_entry_init_one(ctxp, domain, ctx_root); 206 } 207 dmar_flush_ctx_to_ram(unit, ctxp); 208 } 209 210 static int 211 dmar_flush_for_ctx_entry(struct dmar_unit *dmar, bool force) 212 { 213 int error; 214 215 /* 216 * If dmar declares Caching Mode as Set, follow 11.5 "Caching 217 * Mode Consideration" and do the (global) invalidation of the 218 * negative TLB entries. 219 */ 220 if ((dmar->hw_cap & DMAR_CAP_CM) == 0 && !force) 221 return (0); 222 if (dmar->qi_enabled) { 223 dmar_qi_invalidate_ctx_glob_locked(dmar); 224 if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force) 225 dmar_qi_invalidate_iotlb_glob_locked(dmar); 226 return (0); 227 } 228 error = dmar_inv_ctx_glob(dmar); 229 if (error == 0 && ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force)) 230 error = dmar_inv_iotlb_glob(dmar); 231 return (error); 232 } 233 234 static int 235 domain_init_rmrr(struct dmar_domain *domain, device_t dev, int bus, 236 int slot, int func, int dev_domain, int dev_busno, 237 const void *dev_path, int dev_path_len) 238 { 239 struct iommu_map_entries_tailq rmrr_entries; 240 struct iommu_map_entry *entry, *entry1; 241 vm_page_t *ma; 242 iommu_gaddr_t start, end; 243 vm_pindex_t size, i; 244 int error, error1; 245 246 error = 0; 247 TAILQ_INIT(&rmrr_entries); 248 dmar_dev_parse_rmrr(domain, dev_domain, dev_busno, dev_path, 249 dev_path_len, &rmrr_entries); 250 TAILQ_FOREACH_SAFE(entry, &rmrr_entries, unroll_link, entry1) { 251 /* 252 * VT-d specification requires that the start of an 253 * RMRR entry is 4k-aligned. Buggy BIOSes put 254 * anything into the start and end fields. Truncate 255 * and round as neccesary. 256 * 257 * We also allow the overlapping RMRR entries, see 258 * iommu_gas_alloc_region(). 259 */ 260 start = entry->start; 261 end = entry->end; 262 if (bootverbose) 263 printf("dmar%d ctx pci%d:%d:%d RMRR [%#jx, %#jx]\n", 264 domain->iodom.iommu->unit, bus, slot, func, 265 (uintmax_t)start, (uintmax_t)end); 266 entry->start = trunc_page(start); 267 entry->end = round_page(end); 268 if (entry->start == entry->end) { 269 /* Workaround for some AMI (?) BIOSes */ 270 if (bootverbose) { 271 if (dev != NULL) 272 device_printf(dev, ""); 273 printf("pci%d:%d:%d ", bus, slot, func); 274 printf("BIOS bug: dmar%d RMRR " 275 "region (%jx, %jx) corrected\n", 276 domain->iodom.iommu->unit, start, end); 277 } 278 entry->end += DMAR_PAGE_SIZE * 0x20; 279 } 280 size = OFF_TO_IDX(entry->end - entry->start); 281 ma = malloc(sizeof(vm_page_t) * size, M_TEMP, M_WAITOK); 282 for (i = 0; i < size; i++) { 283 ma[i] = vm_page_getfake(entry->start + PAGE_SIZE * i, 284 VM_MEMATTR_DEFAULT); 285 } 286 error1 = iommu_gas_map_region((struct iommu_domain *)domain, 287 entry, 288 IOMMU_MAP_ENTRY_READ | IOMMU_MAP_ENTRY_WRITE, 289 IOMMU_MF_CANWAIT | IOMMU_MF_RMRR, ma); 290 /* 291 * Non-failed RMRR entries are owned by context rb 292 * tree. Get rid of the failed entry, but do not stop 293 * the loop. Rest of the parsed RMRR entries are 294 * loaded and removed on the context destruction. 295 */ 296 if (error1 == 0 && entry->end != entry->start) { 297 IOMMU_LOCK(domain->iodom.iommu); 298 domain->refs++; /* XXXKIB prevent free */ 299 domain->iodom.flags |= IOMMU_DOMAIN_RMRR; 300 IOMMU_UNLOCK(domain->iodom.iommu); 301 } else { 302 if (error1 != 0) { 303 if (dev != NULL) 304 device_printf(dev, ""); 305 printf("pci%d:%d:%d ", bus, slot, func); 306 printf( 307 "dmar%d failed to map RMRR region (%jx, %jx) %d\n", 308 domain->iodom.iommu->unit, start, end, 309 error1); 310 error = error1; 311 } 312 TAILQ_REMOVE(&rmrr_entries, entry, unroll_link); 313 iommu_gas_free_entry((struct iommu_domain *)domain, 314 entry); 315 } 316 for (i = 0; i < size; i++) 317 vm_page_putfake(ma[i]); 318 free(ma, M_TEMP); 319 } 320 return (error); 321 } 322 323 static struct dmar_domain * 324 dmar_domain_alloc(struct dmar_unit *dmar, bool id_mapped) 325 { 326 struct iommu_domain *iodom; 327 struct dmar_domain *domain; 328 int error, id, mgaw; 329 330 id = alloc_unr(dmar->domids); 331 if (id == -1) 332 return (NULL); 333 domain = malloc(sizeof(*domain), M_DMAR_DOMAIN, M_WAITOK | M_ZERO); 334 iodom = (struct iommu_domain *)domain; 335 domain->domain = id; 336 LIST_INIT(&domain->contexts); 337 RB_INIT(&domain->iodom.rb_root); 338 TAILQ_INIT(&domain->iodom.unload_entries); 339 TASK_INIT(&domain->iodom.unload_task, 0, dmar_domain_unload_task, 340 domain); 341 mtx_init(&domain->iodom.lock, "dmardom", NULL, MTX_DEF); 342 domain->dmar = dmar; 343 domain->iodom.iommu = &dmar->iommu; 344 345 /* 346 * For now, use the maximal usable physical address of the 347 * installed memory to calculate the mgaw on id_mapped domain. 348 * It is useful for the identity mapping, and less so for the 349 * virtualized bus address space. 350 */ 351 domain->iodom.end = id_mapped ? ptoa(Maxmem) : BUS_SPACE_MAXADDR; 352 mgaw = dmar_maxaddr2mgaw(dmar, domain->iodom.end, !id_mapped); 353 error = domain_set_agaw(domain, mgaw); 354 if (error != 0) 355 goto fail; 356 if (!id_mapped) 357 /* Use all supported address space for remapping. */ 358 domain->iodom.end = 1ULL << (domain->agaw - 1); 359 360 iommu_gas_init_domain((struct iommu_domain *)domain); 361 362 if (id_mapped) { 363 if ((dmar->hw_ecap & DMAR_ECAP_PT) == 0) { 364 domain->pgtbl_obj = domain_get_idmap_pgtbl(domain, 365 domain->iodom.end); 366 } 367 domain->iodom.flags |= IOMMU_DOMAIN_IDMAP; 368 } else { 369 error = domain_alloc_pgtbl(domain); 370 if (error != 0) 371 goto fail; 372 /* Disable local apic region access */ 373 error = iommu_gas_reserve_region(iodom, 0xfee00000, 374 0xfeefffff + 1); 375 if (error != 0) 376 goto fail; 377 } 378 return (domain); 379 380 fail: 381 dmar_domain_destroy(domain); 382 return (NULL); 383 } 384 385 static struct dmar_ctx * 386 dmar_ctx_alloc(struct dmar_domain *domain, uint16_t rid) 387 { 388 struct dmar_ctx *ctx; 389 390 ctx = malloc(sizeof(*ctx), M_DMAR_CTX, M_WAITOK | M_ZERO); 391 ctx->context.domain = (struct iommu_domain *)domain; 392 ctx->context.tag = malloc(sizeof(struct bus_dma_tag_iommu), 393 M_DMAR_CTX, M_WAITOK | M_ZERO); 394 ctx->rid = rid; 395 ctx->refs = 1; 396 return (ctx); 397 } 398 399 static void 400 dmar_ctx_link(struct dmar_ctx *ctx) 401 { 402 struct dmar_domain *domain; 403 404 domain = (struct dmar_domain *)ctx->context.domain; 405 IOMMU_ASSERT_LOCKED(domain->iodom.iommu); 406 KASSERT(domain->refs >= domain->ctx_cnt, 407 ("dom %p ref underflow %d %d", domain, domain->refs, 408 domain->ctx_cnt)); 409 domain->refs++; 410 domain->ctx_cnt++; 411 LIST_INSERT_HEAD(&domain->contexts, ctx, link); 412 } 413 414 static void 415 dmar_ctx_unlink(struct dmar_ctx *ctx) 416 { 417 struct dmar_domain *domain; 418 419 domain = (struct dmar_domain *)ctx->context.domain; 420 IOMMU_ASSERT_LOCKED(domain->iodom.iommu); 421 KASSERT(domain->refs > 0, 422 ("domain %p ctx dtr refs %d", domain, domain->refs)); 423 KASSERT(domain->ctx_cnt >= domain->refs, 424 ("domain %p ctx dtr refs %d ctx_cnt %d", domain, 425 domain->refs, domain->ctx_cnt)); 426 domain->refs--; 427 domain->ctx_cnt--; 428 LIST_REMOVE(ctx, link); 429 } 430 431 static void 432 dmar_domain_destroy(struct dmar_domain *domain) 433 { 434 struct dmar_unit *dmar; 435 436 KASSERT(TAILQ_EMPTY(&domain->iodom.unload_entries), 437 ("unfinished unloads %p", domain)); 438 KASSERT(LIST_EMPTY(&domain->contexts), 439 ("destroying dom %p with contexts", domain)); 440 KASSERT(domain->ctx_cnt == 0, 441 ("destroying dom %p with ctx_cnt %d", domain, domain->ctx_cnt)); 442 KASSERT(domain->refs == 0, 443 ("destroying dom %p with refs %d", domain, domain->refs)); 444 if ((domain->iodom.flags & IOMMU_DOMAIN_GAS_INITED) != 0) { 445 DMAR_DOMAIN_LOCK(domain); 446 iommu_gas_fini_domain((struct iommu_domain *)domain); 447 DMAR_DOMAIN_UNLOCK(domain); 448 } 449 if ((domain->iodom.flags & IOMMU_DOMAIN_PGTBL_INITED) != 0) { 450 if (domain->pgtbl_obj != NULL) 451 DMAR_DOMAIN_PGLOCK(domain); 452 domain_free_pgtbl(domain); 453 } 454 mtx_destroy(&domain->iodom.lock); 455 dmar = (struct dmar_unit *)domain->iodom.iommu; 456 free_unr(dmar->domids, domain->domain); 457 free(domain, M_DMAR_DOMAIN); 458 } 459 460 static struct dmar_ctx * 461 dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid, 462 int dev_domain, int dev_busno, const void *dev_path, int dev_path_len, 463 bool id_mapped, bool rmrr_init) 464 { 465 struct dmar_domain *domain, *domain1; 466 struct dmar_ctx *ctx, *ctx1; 467 struct iommu_unit *unit; 468 dmar_ctx_entry_t *ctxp; 469 struct sf_buf *sf; 470 int bus, slot, func, error; 471 bool enable; 472 473 if (dev != NULL) { 474 bus = pci_get_bus(dev); 475 slot = pci_get_slot(dev); 476 func = pci_get_function(dev); 477 } else { 478 bus = PCI_RID2BUS(rid); 479 slot = PCI_RID2SLOT(rid); 480 func = PCI_RID2FUNC(rid); 481 } 482 enable = false; 483 TD_PREP_PINNED_ASSERT; 484 unit = (struct iommu_unit *)dmar; 485 DMAR_LOCK(dmar); 486 KASSERT(!iommu_is_buswide_ctx(unit, bus) || (slot == 0 && func == 0), 487 ("iommu%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus, 488 slot, func)); 489 ctx = dmar_find_ctx_locked(dmar, rid); 490 error = 0; 491 if (ctx == NULL) { 492 /* 493 * Perform the allocations which require sleep or have 494 * higher chance to succeed if the sleep is allowed. 495 */ 496 DMAR_UNLOCK(dmar); 497 dmar_ensure_ctx_page(dmar, PCI_RID2BUS(rid)); 498 domain1 = dmar_domain_alloc(dmar, id_mapped); 499 if (domain1 == NULL) { 500 TD_PINNED_ASSERT; 501 return (NULL); 502 } 503 if (!id_mapped) { 504 error = domain_init_rmrr(domain1, dev, bus, 505 slot, func, dev_domain, dev_busno, dev_path, 506 dev_path_len); 507 if (error != 0) { 508 dmar_domain_destroy(domain1); 509 TD_PINNED_ASSERT; 510 return (NULL); 511 } 512 } 513 ctx1 = dmar_ctx_alloc(domain1, rid); 514 ctxp = dmar_map_ctx_entry(ctx1, &sf); 515 DMAR_LOCK(dmar); 516 517 /* 518 * Recheck the contexts, other thread might have 519 * already allocated needed one. 520 */ 521 ctx = dmar_find_ctx_locked(dmar, rid); 522 if (ctx == NULL) { 523 domain = domain1; 524 ctx = ctx1; 525 dmar_ctx_link(ctx); 526 ctx->context.tag->owner = dev; 527 device_tag_init(ctx, dev); 528 529 /* 530 * This is the first activated context for the 531 * DMAR unit. Enable the translation after 532 * everything is set up. 533 */ 534 if (LIST_EMPTY(&dmar->domains)) 535 enable = true; 536 LIST_INSERT_HEAD(&dmar->domains, domain, link); 537 ctx_id_entry_init(ctx, ctxp, false, bus); 538 if (dev != NULL) { 539 device_printf(dev, 540 "dmar%d pci%d:%d:%d:%d rid %x domain %d mgaw %d " 541 "agaw %d %s-mapped\n", 542 dmar->iommu.unit, dmar->segment, bus, slot, 543 func, rid, domain->domain, domain->mgaw, 544 domain->agaw, id_mapped ? "id" : "re"); 545 } 546 dmar_unmap_pgtbl(sf); 547 } else { 548 dmar_unmap_pgtbl(sf); 549 dmar_domain_destroy(domain1); 550 /* Nothing needs to be done to destroy ctx1. */ 551 free(ctx1, M_DMAR_CTX); 552 domain = (struct dmar_domain *)ctx->context.domain; 553 ctx->refs++; /* tag referenced us */ 554 } 555 } else { 556 domain = (struct dmar_domain *)ctx->context.domain; 557 if (ctx->context.tag->owner == NULL) 558 ctx->context.tag->owner = dev; 559 ctx->refs++; /* tag referenced us */ 560 } 561 562 error = dmar_flush_for_ctx_entry(dmar, enable); 563 if (error != 0) { 564 dmar_free_ctx_locked(dmar, ctx); 565 TD_PINNED_ASSERT; 566 return (NULL); 567 } 568 569 /* 570 * The dmar lock was potentially dropped between check for the 571 * empty context list and now. Recheck the state of GCMD_TE 572 * to avoid unneeded command. 573 */ 574 if (enable && !rmrr_init && (dmar->hw_gcmd & DMAR_GCMD_TE) == 0) { 575 error = dmar_enable_translation(dmar); 576 if (error == 0) { 577 if (bootverbose) { 578 printf("dmar%d: enabled translation\n", 579 dmar->iommu.unit); 580 } 581 } else { 582 printf("dmar%d: enabling translation failed, " 583 "error %d\n", dmar->iommu.unit, error); 584 dmar_free_ctx_locked(dmar, ctx); 585 TD_PINNED_ASSERT; 586 return (NULL); 587 } 588 } 589 DMAR_UNLOCK(dmar); 590 TD_PINNED_ASSERT; 591 return (ctx); 592 } 593 594 struct dmar_ctx * 595 dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, uint16_t rid, 596 bool id_mapped, bool rmrr_init) 597 { 598 int dev_domain, dev_path_len, dev_busno; 599 600 dev_domain = pci_get_domain(dev); 601 dev_path_len = dmar_dev_depth(dev); 602 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 603 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 604 return (dmar_get_ctx_for_dev1(dmar, dev, rid, dev_domain, dev_busno, 605 dev_path, dev_path_len, id_mapped, rmrr_init)); 606 } 607 608 struct dmar_ctx * 609 dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid, 610 int dev_domain, int dev_busno, 611 const void *dev_path, int dev_path_len, 612 bool id_mapped, bool rmrr_init) 613 { 614 615 return (dmar_get_ctx_for_dev1(dmar, NULL, rid, dev_domain, dev_busno, 616 dev_path, dev_path_len, id_mapped, rmrr_init)); 617 } 618 619 int 620 dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx) 621 { 622 struct dmar_unit *dmar; 623 struct dmar_domain *old_domain; 624 dmar_ctx_entry_t *ctxp; 625 struct sf_buf *sf; 626 int error; 627 628 dmar = domain->dmar; 629 old_domain = (struct dmar_domain *)ctx->context.domain; 630 if (domain == old_domain) 631 return (0); 632 KASSERT(old_domain->iodom.iommu == domain->iodom.iommu, 633 ("domain %p %u moving between dmars %u %u", domain, 634 domain->domain, old_domain->iodom.iommu->unit, 635 domain->iodom.iommu->unit)); 636 TD_PREP_PINNED_ASSERT; 637 638 ctxp = dmar_map_ctx_entry(ctx, &sf); 639 DMAR_LOCK(dmar); 640 dmar_ctx_unlink(ctx); 641 ctx->context.domain = &domain->iodom; 642 dmar_ctx_link(ctx); 643 ctx_id_entry_init(ctx, ctxp, true, PCI_BUSMAX + 100); 644 dmar_unmap_pgtbl(sf); 645 error = dmar_flush_for_ctx_entry(dmar, true); 646 /* If flush failed, rolling back would not work as well. */ 647 printf("dmar%d rid %x domain %d->%d %s-mapped\n", 648 dmar->iommu.unit, ctx->rid, old_domain->domain, domain->domain, 649 (domain->iodom.flags & IOMMU_DOMAIN_IDMAP) != 0 ? "id" : "re"); 650 dmar_unref_domain_locked(dmar, old_domain); 651 TD_PINNED_ASSERT; 652 return (error); 653 } 654 655 static void 656 dmar_unref_domain_locked(struct dmar_unit *dmar, struct dmar_domain *domain) 657 { 658 659 DMAR_ASSERT_LOCKED(dmar); 660 KASSERT(domain->refs >= 1, 661 ("dmar %d domain %p refs %u", dmar->iommu.unit, domain, 662 domain->refs)); 663 KASSERT(domain->refs > domain->ctx_cnt, 664 ("dmar %d domain %p refs %d ctx_cnt %d", dmar->iommu.unit, domain, 665 domain->refs, domain->ctx_cnt)); 666 667 if (domain->refs > 1) { 668 domain->refs--; 669 DMAR_UNLOCK(dmar); 670 return; 671 } 672 673 KASSERT((domain->iodom.flags & IOMMU_DOMAIN_RMRR) == 0, 674 ("lost ref on RMRR domain %p", domain)); 675 676 LIST_REMOVE(domain, link); 677 DMAR_UNLOCK(dmar); 678 679 taskqueue_drain(dmar->iommu.delayed_taskqueue, 680 &domain->iodom.unload_task); 681 dmar_domain_destroy(domain); 682 } 683 684 void 685 dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx) 686 { 687 struct sf_buf *sf; 688 dmar_ctx_entry_t *ctxp; 689 struct dmar_domain *domain; 690 691 DMAR_ASSERT_LOCKED(dmar); 692 KASSERT(ctx->refs >= 1, 693 ("dmar %p ctx %p refs %u", dmar, ctx, ctx->refs)); 694 695 /* 696 * If our reference is not last, only the dereference should 697 * be performed. 698 */ 699 if (ctx->refs > 1) { 700 ctx->refs--; 701 DMAR_UNLOCK(dmar); 702 return; 703 } 704 705 KASSERT((ctx->context.flags & IOMMU_CTX_DISABLED) == 0, 706 ("lost ref on disabled ctx %p", ctx)); 707 708 /* 709 * Otherwise, the context entry must be cleared before the 710 * page table is destroyed. The mapping of the context 711 * entries page could require sleep, unlock the dmar. 712 */ 713 DMAR_UNLOCK(dmar); 714 TD_PREP_PINNED_ASSERT; 715 ctxp = dmar_map_ctx_entry(ctx, &sf); 716 DMAR_LOCK(dmar); 717 KASSERT(ctx->refs >= 1, 718 ("dmar %p ctx %p refs %u", dmar, ctx, ctx->refs)); 719 720 /* 721 * Other thread might have referenced the context, in which 722 * case again only the dereference should be performed. 723 */ 724 if (ctx->refs > 1) { 725 ctx->refs--; 726 DMAR_UNLOCK(dmar); 727 dmar_unmap_pgtbl(sf); 728 TD_PINNED_ASSERT; 729 return; 730 } 731 732 KASSERT((ctx->context.flags & IOMMU_CTX_DISABLED) == 0, 733 ("lost ref on disabled ctx %p", ctx)); 734 735 /* 736 * Clear the context pointer and flush the caches. 737 * XXXKIB: cannot do this if any RMRR entries are still present. 738 */ 739 dmar_pte_clear(&ctxp->ctx1); 740 ctxp->ctx2 = 0; 741 dmar_flush_ctx_to_ram(dmar, ctxp); 742 dmar_inv_ctx_glob(dmar); 743 if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0) { 744 if (dmar->qi_enabled) 745 dmar_qi_invalidate_iotlb_glob_locked(dmar); 746 else 747 dmar_inv_iotlb_glob(dmar); 748 } 749 dmar_unmap_pgtbl(sf); 750 domain = (struct dmar_domain *)ctx->context.domain; 751 dmar_ctx_unlink(ctx); 752 free(ctx->context.tag, M_DMAR_CTX); 753 free(ctx, M_DMAR_CTX); 754 dmar_unref_domain_locked(dmar, domain); 755 TD_PINNED_ASSERT; 756 } 757 758 void 759 dmar_free_ctx(struct dmar_ctx *ctx) 760 { 761 struct dmar_unit *dmar; 762 763 dmar = (struct dmar_unit *)ctx->context.domain->iommu; 764 DMAR_LOCK(dmar); 765 dmar_free_ctx_locked(dmar, ctx); 766 } 767 768 /* 769 * Returns with the domain locked. 770 */ 771 struct dmar_ctx * 772 dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid) 773 { 774 struct dmar_domain *domain; 775 struct dmar_ctx *ctx; 776 777 DMAR_ASSERT_LOCKED(dmar); 778 779 LIST_FOREACH(domain, &dmar->domains, link) { 780 LIST_FOREACH(ctx, &domain->contexts, link) { 781 if (ctx->rid == rid) 782 return (ctx); 783 } 784 } 785 return (NULL); 786 } 787 788 void 789 dmar_domain_free_entry(struct iommu_map_entry *entry, bool free) 790 { 791 struct iommu_domain *domain; 792 793 domain = entry->domain; 794 IOMMU_DOMAIN_LOCK(domain); 795 if ((entry->flags & IOMMU_MAP_ENTRY_RMRR) != 0) 796 iommu_gas_free_region(domain, entry); 797 else 798 iommu_gas_free_space(domain, entry); 799 IOMMU_DOMAIN_UNLOCK(domain); 800 if (free) 801 iommu_gas_free_entry(domain, entry); 802 else 803 entry->flags = 0; 804 } 805 806 void 807 dmar_domain_unload_entry(struct iommu_map_entry *entry, bool free) 808 { 809 struct dmar_domain *domain; 810 struct dmar_unit *unit; 811 812 domain = (struct dmar_domain *)entry->domain; 813 unit = (struct dmar_unit *)domain->iodom.iommu; 814 if (unit->qi_enabled) { 815 DMAR_LOCK(unit); 816 dmar_qi_invalidate_locked((struct dmar_domain *)entry->domain, 817 entry->start, entry->end - entry->start, &entry->gseq, 818 true); 819 if (!free) 820 entry->flags |= IOMMU_MAP_ENTRY_QI_NF; 821 TAILQ_INSERT_TAIL(&unit->tlb_flush_entries, entry, dmamap_link); 822 DMAR_UNLOCK(unit); 823 } else { 824 domain_flush_iotlb_sync((struct dmar_domain *)entry->domain, 825 entry->start, entry->end - entry->start); 826 dmar_domain_free_entry(entry, free); 827 } 828 } 829 830 static bool 831 dmar_domain_unload_emit_wait(struct dmar_domain *domain, 832 struct iommu_map_entry *entry) 833 { 834 835 if (TAILQ_NEXT(entry, dmamap_link) == NULL) 836 return (true); 837 return (domain->batch_no++ % dmar_batch_coalesce == 0); 838 } 839 840 void 841 dmar_domain_unload(struct dmar_domain *domain, 842 struct iommu_map_entries_tailq *entries, bool cansleep) 843 { 844 struct dmar_unit *unit; 845 struct iommu_map_entry *entry, *entry1; 846 int error; 847 848 unit = (struct dmar_unit *)domain->iodom.iommu; 849 850 TAILQ_FOREACH_SAFE(entry, entries, dmamap_link, entry1) { 851 KASSERT((entry->flags & IOMMU_MAP_ENTRY_MAP) != 0, 852 ("not mapped entry %p %p", domain, entry)); 853 error = domain_unmap_buf(domain, entry->start, entry->end - 854 entry->start, cansleep ? IOMMU_PGF_WAITOK : 0); 855 KASSERT(error == 0, ("unmap %p error %d", domain, error)); 856 if (!unit->qi_enabled) { 857 domain_flush_iotlb_sync(domain, entry->start, 858 entry->end - entry->start); 859 TAILQ_REMOVE(entries, entry, dmamap_link); 860 dmar_domain_free_entry(entry, true); 861 } 862 } 863 if (TAILQ_EMPTY(entries)) 864 return; 865 866 KASSERT(unit->qi_enabled, ("loaded entry left")); 867 DMAR_LOCK(unit); 868 TAILQ_FOREACH(entry, entries, dmamap_link) { 869 dmar_qi_invalidate_locked(domain, entry->start, entry->end - 870 entry->start, &entry->gseq, 871 dmar_domain_unload_emit_wait(domain, entry)); 872 } 873 TAILQ_CONCAT(&unit->tlb_flush_entries, entries, dmamap_link); 874 DMAR_UNLOCK(unit); 875 } 876 877 static void 878 dmar_domain_unload_task(void *arg, int pending) 879 { 880 struct dmar_domain *domain; 881 struct iommu_map_entries_tailq entries; 882 883 domain = arg; 884 TAILQ_INIT(&entries); 885 886 for (;;) { 887 DMAR_DOMAIN_LOCK(domain); 888 TAILQ_SWAP(&domain->iodom.unload_entries, &entries, 889 iommu_map_entry, dmamap_link); 890 DMAR_DOMAIN_UNLOCK(domain); 891 if (TAILQ_EMPTY(&entries)) 892 break; 893 dmar_domain_unload(domain, &entries, true); 894 } 895 } 896 897 struct iommu_ctx * 898 iommu_get_ctx(struct iommu_unit *iommu, device_t dev, uint16_t rid, 899 bool id_mapped, bool rmrr_init) 900 { 901 struct dmar_unit *dmar; 902 struct dmar_ctx *ret; 903 904 dmar = (struct dmar_unit *)iommu; 905 906 ret = dmar_get_ctx_for_dev(dmar, dev, rid, id_mapped, rmrr_init); 907 908 return ((struct iommu_ctx *)ret); 909 } 910 911 void 912 iommu_free_ctx_locked(struct iommu_unit *iommu, struct iommu_ctx *context) 913 { 914 struct dmar_unit *dmar; 915 struct dmar_ctx *ctx; 916 917 dmar = (struct dmar_unit *)iommu; 918 ctx = (struct dmar_ctx *)context; 919 920 dmar_free_ctx_locked(dmar, ctx); 921 } 922 923 void 924 iommu_free_ctx(struct iommu_ctx *context) 925 { 926 struct dmar_unit *dmar; 927 struct dmar_ctx *ctx; 928 929 ctx = (struct dmar_ctx *)context; 930 dmar = (struct dmar_unit *)ctx->context.domain->iommu; 931 932 dmar_free_ctx(ctx); 933 } 934 935 void 936 iommu_domain_unload_entry(struct iommu_map_entry *entry, bool free) 937 { 938 939 dmar_domain_unload_entry(entry, free); 940 } 941 942 void 943 iommu_domain_unload(struct iommu_domain *iodom, 944 struct iommu_map_entries_tailq *entries, bool cansleep) 945 { 946 struct dmar_domain *domain; 947 948 domain = (struct dmar_domain *)iodom; 949 950 dmar_domain_unload(domain, entries, cansleep); 951 } 952