1 /*- 2 * Copyright (c) 1995 Bruce D. Evans. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _X86_X86_VAR_H_ 33 #define _X86_X86_VAR_H_ 34 35 /* 36 * Miscellaneous machine-dependent declarations. 37 */ 38 39 extern long Maxmem; 40 extern u_int basemem; 41 extern int busdma_swi_pending; 42 extern u_int cpu_exthigh; 43 extern u_int cpu_feature; 44 extern u_int cpu_feature2; 45 extern u_int amd_feature; 46 extern u_int amd_feature2; 47 extern u_int amd_rascap; 48 extern u_int amd_pminfo; 49 extern u_int amd_extended_feature_extensions; 50 extern u_int via_feature_rng; 51 extern u_int via_feature_xcrypt; 52 extern u_int cpu_clflush_line_size; 53 extern u_int cpu_stdext_feature; 54 extern u_int cpu_stdext_feature2; 55 extern u_int cpu_stdext_feature3; 56 extern uint64_t cpu_ia32_arch_caps; 57 extern u_int cpu_fxsr; 58 extern u_int cpu_high; 59 extern u_int cpu_id; 60 extern u_int cpu_max_ext_state_size; 61 extern u_int cpu_mxcsr_mask; 62 extern u_int cpu_procinfo; 63 extern u_int cpu_procinfo2; 64 extern char cpu_vendor[]; 65 extern u_int cpu_vendor_id; 66 extern u_int cpu_mon_mwait_flags; 67 extern u_int cpu_mon_min_size; 68 extern u_int cpu_mon_max_size; 69 extern u_int cpu_maxphyaddr; 70 extern u_int cpu_power_eax; 71 extern u_int cpu_power_ebx; 72 extern u_int cpu_power_ecx; 73 extern u_int cpu_power_edx; 74 extern u_int hv_base; 75 extern u_int hv_high; 76 extern char hv_vendor[]; 77 extern char kstack[]; 78 extern char sigcode[]; 79 extern int szsigcode; 80 extern int workaround_erratum383; 81 extern int _udatasel; 82 extern int _ucodesel; 83 extern int _ucode32sel; 84 extern int _ufssel; 85 extern int _ugssel; 86 extern int use_xsave; 87 extern uint64_t xsave_mask; 88 extern u_int max_apic_id; 89 extern int i386_read_exec; 90 extern int pti; 91 extern int hw_ibrs_ibpb_active; 92 extern int hw_mds_disable; 93 extern int hw_ssb_active; 94 extern int x86_taa_enable; 95 extern int cpu_flush_rsb_ctxsw; 96 extern int x86_rngds_mitg_enable; 97 extern int cpu_amdc1e_bug; 98 extern char bootmethod[16]; 99 100 struct pcb; 101 struct thread; 102 struct reg; 103 struct fpreg; 104 struct dbreg; 105 struct dumperinfo; 106 struct trapframe; 107 struct minidumpstate; 108 109 /* 110 * The interface type of the interrupt handler entry point cannot be 111 * expressed in C. Use simplest non-variadic function type as an 112 * approximation. 113 */ 114 typedef void alias_for_inthand_t(void); 115 116 bool acpi_get_fadt_bootflags(uint16_t *flagsp); 117 void *alloc_fpusave(int flags); 118 void busdma_swi(void); 119 u_int cpu_auxmsr(void); 120 vm_paddr_t cpu_getmaxphyaddr(void); 121 bool cpu_mwait_usable(void); 122 void cpu_probe_amdc1e(void); 123 void cpu_setregs(void); 124 int dbreg_set_watchpoint(vm_offset_t addr, vm_size_t size, int access); 125 int dbreg_clr_watchpoint(vm_offset_t addr, vm_size_t size); 126 void dbreg_list_watchpoints(void); 127 void x86_clear_dbregs(struct pcb *pcb); 128 bool disable_wp(void); 129 void restore_wp(bool old_wp); 130 void finishidentcpu(void); 131 void identify_cpu1(void); 132 void identify_cpu2(void); 133 void identify_cpu_fixup_bsp(void); 134 void identify_hypervisor(void); 135 void initializecpu(void); 136 void initializecpucache(void); 137 bool fix_cpuid(void); 138 void fillw(int /*u_short*/ pat, void *base, size_t cnt); 139 int is_physical_memory(vm_paddr_t addr); 140 int isa_nmi(int cd); 141 void handle_ibrs_entry(void); 142 void handle_ibrs_exit(void); 143 void hw_ibrs_recalculate(bool all_cpus); 144 void hw_mds_recalculate(void); 145 void hw_ssb_recalculate(bool all_cpus); 146 void x86_taa_recalculate(void); 147 void x86_rngds_mitg_recalculate(bool all_cpus); 148 void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame); 149 void nmi_call_kdb_smp(u_int type, struct trapframe *frame); 150 void nmi_handle_intr(u_int type, struct trapframe *frame); 151 void pagecopy(void *from, void *to); 152 void printcpuinfo(void); 153 int pti_get_default(void); 154 int user_dbreg_trap(register_t dr6); 155 int cpu_minidumpsys(struct dumperinfo *, const struct minidumpstate *); 156 struct pcb *get_pcb_td(struct thread *td); 157 void x86_set_fork_retval(struct thread *td); 158 uint64_t rdtsc_ordered(void); 159 160 /* 161 * MSR ops for x86_msr_op() 162 */ 163 #define MSR_OP_ANDNOT 0x00000001 164 #define MSR_OP_OR 0x00000002 165 #define MSR_OP_WRITE 0x00000003 166 #define MSR_OP_READ 0x00000004 167 168 /* 169 * Where and which execution mode 170 */ 171 #define MSR_OP_LOCAL 0x10000000 172 #define MSR_OP_SCHED_ALL 0x20000000 173 #define MSR_OP_SCHED_ONE 0x30000000 174 #define MSR_OP_RENDEZVOUS_ALL 0x40000000 175 #define MSR_OP_RENDEZVOUS_ONE 0x50000000 176 #define MSR_OP_CPUID(id) ((id) << 8) 177 178 void x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res); 179 180 #endif 181