1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_SPECIALREG_H_ 34 #define _MACHINE_SPECIALREG_H_ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 #define CR3_PCID_SAVE 0x8000000000000000 56 #define CR3_PCID_MASK 0xfff 57 58 /* 59 * Bits in PPro special registers 60 */ 61 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 62 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 63 #define CR4_TSD 0x00000004 /* Time stamp disable */ 64 #define CR4_DE 0x00000008 /* Debugging extensions */ 65 #define CR4_PSE 0x00000010 /* Page size extensions */ 66 #define CR4_PAE 0x00000020 /* Physical address extension */ 67 #define CR4_MCE 0x00000040 /* Machine check enable */ 68 #define CR4_PGE 0x00000080 /* Page global enable */ 69 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 70 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 71 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 72 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 73 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 74 #define CR4_PCIDE 0x00020000 /* Enable Context ID */ 75 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 76 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 77 78 /* 79 * Bits in AMD64 special registers. EFER is 64 bits wide. 80 */ 81 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 82 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 83 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 84 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 85 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ 86 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ 87 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ 88 #define EFER_TCE 0x000008000 /* Translation Cache Extension */ 89 90 /* 91 * Intel Extended Features registers 92 */ 93 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 94 95 #define XFEATURE_ENABLED_X87 0x00000001 96 #define XFEATURE_ENABLED_SSE 0x00000002 97 #define XFEATURE_ENABLED_YMM_HI128 0x00000004 98 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128 99 #define XFEATURE_ENABLED_BNDREGS 0x00000008 100 #define XFEATURE_ENABLED_BNDCSR 0x00000010 101 #define XFEATURE_ENABLED_OPMASK 0x00000020 102 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040 103 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080 104 105 #define XFEATURE_AVX \ 106 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 107 #define XFEATURE_AVX512 \ 108 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \ 109 XFEATURE_ENABLED_HI16_ZMM) 110 #define XFEATURE_MPX \ 111 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR) 112 113 /* 114 * CPUID instruction features register 115 */ 116 #define CPUID_FPU 0x00000001 117 #define CPUID_VME 0x00000002 118 #define CPUID_DE 0x00000004 119 #define CPUID_PSE 0x00000008 120 #define CPUID_TSC 0x00000010 121 #define CPUID_MSR 0x00000020 122 #define CPUID_PAE 0x00000040 123 #define CPUID_MCE 0x00000080 124 #define CPUID_CX8 0x00000100 125 #define CPUID_APIC 0x00000200 126 #define CPUID_B10 0x00000400 127 #define CPUID_SEP 0x00000800 128 #define CPUID_MTRR 0x00001000 129 #define CPUID_PGE 0x00002000 130 #define CPUID_MCA 0x00004000 131 #define CPUID_CMOV 0x00008000 132 #define CPUID_PAT 0x00010000 133 #define CPUID_PSE36 0x00020000 134 #define CPUID_PSN 0x00040000 135 #define CPUID_CLFSH 0x00080000 136 #define CPUID_B20 0x00100000 137 #define CPUID_DS 0x00200000 138 #define CPUID_ACPI 0x00400000 139 #define CPUID_MMX 0x00800000 140 #define CPUID_FXSR 0x01000000 141 #define CPUID_SSE 0x02000000 142 #define CPUID_XMM 0x02000000 143 #define CPUID_SSE2 0x04000000 144 #define CPUID_SS 0x08000000 145 #define CPUID_HTT 0x10000000 146 #define CPUID_TM 0x20000000 147 #define CPUID_IA64 0x40000000 148 #define CPUID_PBE 0x80000000 149 150 #define CPUID2_SSE3 0x00000001 151 #define CPUID2_PCLMULQDQ 0x00000002 152 #define CPUID2_DTES64 0x00000004 153 #define CPUID2_MON 0x00000008 154 #define CPUID2_DS_CPL 0x00000010 155 #define CPUID2_VMX 0x00000020 156 #define CPUID2_SMX 0x00000040 157 #define CPUID2_EST 0x00000080 158 #define CPUID2_TM2 0x00000100 159 #define CPUID2_SSSE3 0x00000200 160 #define CPUID2_CNXTID 0x00000400 161 #define CPUID2_SDBG 0x00000800 162 #define CPUID2_FMA 0x00001000 163 #define CPUID2_CX16 0x00002000 164 #define CPUID2_XTPR 0x00004000 165 #define CPUID2_PDCM 0x00008000 166 #define CPUID2_PCID 0x00020000 167 #define CPUID2_DCA 0x00040000 168 #define CPUID2_SSE41 0x00080000 169 #define CPUID2_SSE42 0x00100000 170 #define CPUID2_X2APIC 0x00200000 171 #define CPUID2_MOVBE 0x00400000 172 #define CPUID2_POPCNT 0x00800000 173 #define CPUID2_TSCDLT 0x01000000 174 #define CPUID2_AESNI 0x02000000 175 #define CPUID2_XSAVE 0x04000000 176 #define CPUID2_OSXSAVE 0x08000000 177 #define CPUID2_AVX 0x10000000 178 #define CPUID2_F16C 0x20000000 179 #define CPUID2_RDRAND 0x40000000 180 #define CPUID2_HV 0x80000000 181 182 /* 183 * Important bits in the Thermal and Power Management flags 184 * CPUID.6 EAX and ECX. 185 */ 186 #define CPUTPM1_SENSOR 0x00000001 187 #define CPUTPM1_TURBO 0x00000002 188 #define CPUTPM1_ARAT 0x00000004 189 #define CPUTPM2_EFFREQ 0x00000001 190 191 /* 192 * Important bits in the AMD extended cpuid flags 193 */ 194 #define AMDID_SYSCALL 0x00000800 195 #define AMDID_MP 0x00080000 196 #define AMDID_NX 0x00100000 197 #define AMDID_EXT_MMX 0x00400000 198 #define AMDID_FFXSR 0x02000000 199 #define AMDID_PAGE1GB 0x04000000 200 #define AMDID_RDTSCP 0x08000000 201 #define AMDID_LM 0x20000000 202 #define AMDID_EXT_3DNOW 0x40000000 203 #define AMDID_3DNOW 0x80000000 204 205 #define AMDID2_LAHF 0x00000001 206 #define AMDID2_CMP 0x00000002 207 #define AMDID2_SVM 0x00000004 208 #define AMDID2_EXT_APIC 0x00000008 209 #define AMDID2_CR8 0x00000010 210 #define AMDID2_ABM 0x00000020 211 #define AMDID2_SSE4A 0x00000040 212 #define AMDID2_MAS 0x00000080 213 #define AMDID2_PREFETCH 0x00000100 214 #define AMDID2_OSVW 0x00000200 215 #define AMDID2_IBS 0x00000400 216 #define AMDID2_XOP 0x00000800 217 #define AMDID2_SKINIT 0x00001000 218 #define AMDID2_WDT 0x00002000 219 #define AMDID2_LWP 0x00008000 220 #define AMDID2_FMA4 0x00010000 221 #define AMDID2_TCE 0x00020000 222 #define AMDID2_NODE_ID 0x00080000 223 #define AMDID2_TBM 0x00200000 224 #define AMDID2_TOPOLOGY 0x00400000 225 #define AMDID2_PCXC 0x00800000 226 #define AMDID2_PNXC 0x01000000 227 #define AMDID2_DBE 0x04000000 228 #define AMDID2_PTSC 0x08000000 229 #define AMDID2_PTSCEL2I 0x10000000 230 #define AMDID2_MWAITX 0x20000000 231 232 /* 233 * CPUID instruction 1 eax info 234 */ 235 #define CPUID_STEPPING 0x0000000f 236 #define CPUID_MODEL 0x000000f0 237 #define CPUID_FAMILY 0x00000f00 238 #define CPUID_EXT_MODEL 0x000f0000 239 #define CPUID_EXT_FAMILY 0x0ff00000 240 #ifdef __i386__ 241 #define CPUID_TO_MODEL(id) \ 242 ((((id) & CPUID_MODEL) >> 4) | \ 243 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 244 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 245 #define CPUID_TO_FAMILY(id) \ 246 ((((id) & CPUID_FAMILY) >> 8) + \ 247 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 248 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 249 #else 250 #define CPUID_TO_MODEL(id) \ 251 ((((id) & CPUID_MODEL) >> 4) | \ 252 (((id) & CPUID_EXT_MODEL) >> 12)) 253 #define CPUID_TO_FAMILY(id) \ 254 ((((id) & CPUID_FAMILY) >> 8) + \ 255 (((id) & CPUID_EXT_FAMILY) >> 20)) 256 #endif 257 258 /* 259 * CPUID instruction 1 ebx info 260 */ 261 #define CPUID_BRAND_INDEX 0x000000ff 262 #define CPUID_CLFUSH_SIZE 0x0000ff00 263 #define CPUID_HTT_CORES 0x00ff0000 264 #define CPUID_LOCAL_APIC_ID 0xff000000 265 266 /* 267 * CPUID instruction 5 info 268 */ 269 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 270 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 271 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 272 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 273 274 /* 275 * MWAIT cpu power states. Lower 4 bits are sub-states. 276 */ 277 #define MWAIT_C0 0xf0 278 #define MWAIT_C1 0x00 279 #define MWAIT_C2 0x10 280 #define MWAIT_C3 0x20 281 #define MWAIT_C4 0x30 282 283 /* 284 * MWAIT extensions. 285 */ 286 /* Interrupt breaks MWAIT even when masked. */ 287 #define MWAIT_INTRBREAK 0x00000001 288 289 /* 290 * CPUID instruction 6 ecx info 291 */ 292 #define CPUID_PERF_STAT 0x00000001 293 #define CPUID_PERF_BIAS 0x00000008 294 295 /* 296 * CPUID instruction 0xb ebx info. 297 */ 298 #define CPUID_TYPE_INVAL 0 299 #define CPUID_TYPE_SMT 1 300 #define CPUID_TYPE_CORE 2 301 302 /* 303 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 304 */ 305 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001 306 #define CPUID_EXTSTATE_XSAVEC 0x00000002 307 #define CPUID_EXTSTATE_XINUSE 0x00000004 308 #define CPUID_EXTSTATE_XSAVES 0x00000008 309 310 /* 311 * AMD extended function 8000_0007h ebx info 312 */ 313 #define AMDRAS_MCA_OF_RECOV 0x00000001 314 #define AMDRAS_SUCCOR 0x00000002 315 #define AMDRAS_HW_ASSERT 0x00000004 316 #define AMDRAS_SCALABLE_MCA 0x00000008 317 #define AMDRAS_PFEH_SUPPORT 0x00000010 318 319 /* 320 * AMD extended function 8000_0007h edx info 321 */ 322 #define AMDPM_TS 0x00000001 323 #define AMDPM_FID 0x00000002 324 #define AMDPM_VID 0x00000004 325 #define AMDPM_TTP 0x00000008 326 #define AMDPM_TM 0x00000010 327 #define AMDPM_STC 0x00000020 328 #define AMDPM_100MHZ_STEPS 0x00000040 329 #define AMDPM_HW_PSTATE 0x00000080 330 #define AMDPM_TSC_INVARIANT 0x00000100 331 #define AMDPM_CPB 0x00000200 332 333 /* 334 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions) 335 */ 336 #define AMDFEID_CLZERO 0x00000001 337 #define AMDFEID_IRPERF 0x00000002 338 #define AMDFEID_XSAVEERPTR 0x00000004 339 340 /* 341 * AMD extended function 8000_0008h ecx info 342 */ 343 #define AMDID_CMP_CORES 0x000000ff 344 #define AMDID_COREID_SIZE 0x0000f000 345 #define AMDID_COREID_SIZE_SHIFT 12 346 347 /* 348 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info 349 */ 350 #define CPUID_STDEXT_FSGSBASE 0x00000001 351 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 352 #define CPUID_STDEXT_SGX 0x00000004 353 #define CPUID_STDEXT_BMI1 0x00000008 354 #define CPUID_STDEXT_HLE 0x00000010 355 #define CPUID_STDEXT_AVX2 0x00000020 356 #define CPUID_STDEXT_FDP_EXC 0x00000040 357 #define CPUID_STDEXT_SMEP 0x00000080 358 #define CPUID_STDEXT_BMI2 0x00000100 359 #define CPUID_STDEXT_ERMS 0x00000200 360 #define CPUID_STDEXT_INVPCID 0x00000400 361 #define CPUID_STDEXT_RTM 0x00000800 362 #define CPUID_STDEXT_PQM 0x00001000 363 #define CPUID_STDEXT_NFPUSG 0x00002000 364 #define CPUID_STDEXT_MPX 0x00004000 365 #define CPUID_STDEXT_PQE 0x00008000 366 #define CPUID_STDEXT_AVX512F 0x00010000 367 #define CPUID_STDEXT_AVX512DQ 0x00020000 368 #define CPUID_STDEXT_RDSEED 0x00040000 369 #define CPUID_STDEXT_ADX 0x00080000 370 #define CPUID_STDEXT_SMAP 0x00100000 371 #define CPUID_STDEXT_AVX512IFMA 0x00200000 372 #define CPUID_STDEXT_PCOMMIT 0x00400000 373 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000 374 #define CPUID_STDEXT_CLWB 0x01000000 375 #define CPUID_STDEXT_PROCTRACE 0x02000000 376 #define CPUID_STDEXT_AVX512PF 0x04000000 377 #define CPUID_STDEXT_AVX512ER 0x08000000 378 #define CPUID_STDEXT_AVX512CD 0x10000000 379 #define CPUID_STDEXT_SHA 0x20000000 380 #define CPUID_STDEXT_AVX512BW 0x40000000 381 382 /* 383 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info 384 */ 385 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001 386 #define CPUID_STDEXT2_UMIP 0x00000004 387 #define CPUID_STDEXT2_PKU 0x00000008 388 #define CPUID_STDEXT2_OSPKE 0x00000010 389 #define CPUID_STDEXT2_RDPID 0x00400000 390 #define CPUID_STDEXT2_SGXLC 0x40000000 391 392 /* 393 * CPUID manufacturers identifiers 394 */ 395 #define AMD_VENDOR_ID "AuthenticAMD" 396 #define CENTAUR_VENDOR_ID "CentaurHauls" 397 #define CYRIX_VENDOR_ID "CyrixInstead" 398 #define INTEL_VENDOR_ID "GenuineIntel" 399 #define NEXGEN_VENDOR_ID "NexGenDriven" 400 #define NSC_VENDOR_ID "Geode by NSC" 401 #define RISE_VENDOR_ID "RiseRiseRise" 402 #define SIS_VENDOR_ID "SiS SiS SiS " 403 #define TRANSMETA_VENDOR_ID "GenuineTMx86" 404 #define UMC_VENDOR_ID "UMC UMC UMC " 405 406 /* 407 * Model-specific registers for the i386 family 408 */ 409 #define MSR_P5_MC_ADDR 0x000 410 #define MSR_P5_MC_TYPE 0x001 411 #define MSR_TSC 0x010 412 #define MSR_P5_CESR 0x011 413 #define MSR_P5_CTR0 0x012 414 #define MSR_P5_CTR1 0x013 415 #define MSR_IA32_PLATFORM_ID 0x017 416 #define MSR_APICBASE 0x01b 417 #define MSR_EBL_CR_POWERON 0x02a 418 #define MSR_TEST_CTL 0x033 419 #define MSR_IA32_FEATURE_CONTROL 0x03a 420 #define MSR_BIOS_UPDT_TRIG 0x079 421 #define MSR_BBL_CR_D0 0x088 422 #define MSR_BBL_CR_D1 0x089 423 #define MSR_BBL_CR_D2 0x08a 424 #define MSR_BIOS_SIGN 0x08b 425 #define MSR_PERFCTR0 0x0c1 426 #define MSR_PERFCTR1 0x0c2 427 #define MSR_PLATFORM_INFO 0x0ce 428 #define MSR_MPERF 0x0e7 429 #define MSR_APERF 0x0e8 430 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 431 #define MSR_MTRRcap 0x0fe 432 #define MSR_BBL_CR_ADDR 0x116 433 #define MSR_BBL_CR_DECC 0x118 434 #define MSR_BBL_CR_CTL 0x119 435 #define MSR_BBL_CR_TRIG 0x11a 436 #define MSR_BBL_CR_BUSY 0x11b 437 #define MSR_BBL_CR_CTL3 0x11e 438 #define MSR_SYSENTER_CS_MSR 0x174 439 #define MSR_SYSENTER_ESP_MSR 0x175 440 #define MSR_SYSENTER_EIP_MSR 0x176 441 #define MSR_MCG_CAP 0x179 442 #define MSR_MCG_STATUS 0x17a 443 #define MSR_MCG_CTL 0x17b 444 #define MSR_EVNTSEL0 0x186 445 #define MSR_EVNTSEL1 0x187 446 #define MSR_THERM_CONTROL 0x19a 447 #define MSR_THERM_INTERRUPT 0x19b 448 #define MSR_THERM_STATUS 0x19c 449 #define MSR_IA32_MISC_ENABLE 0x1a0 450 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 451 #define MSR_TURBO_RATIO_LIMIT 0x1ad 452 #define MSR_TURBO_RATIO_LIMIT1 0x1ae 453 #define MSR_DEBUGCTLMSR 0x1d9 454 #define MSR_LASTBRANCHFROMIP 0x1db 455 #define MSR_LASTBRANCHTOIP 0x1dc 456 #define MSR_LASTINTFROMIP 0x1dd 457 #define MSR_LASTINTTOIP 0x1de 458 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 459 #define MSR_MTRRVarBase 0x200 460 #define MSR_MTRR64kBase 0x250 461 #define MSR_MTRR16kBase 0x258 462 #define MSR_MTRR4kBase 0x268 463 #define MSR_PAT 0x277 464 #define MSR_MC0_CTL2 0x280 465 #define MSR_MTRRdefType 0x2ff 466 #define MSR_MC0_CTL 0x400 467 #define MSR_MC0_STATUS 0x401 468 #define MSR_MC0_ADDR 0x402 469 #define MSR_MC0_MISC 0x403 470 #define MSR_MC1_CTL 0x404 471 #define MSR_MC1_STATUS 0x405 472 #define MSR_MC1_ADDR 0x406 473 #define MSR_MC1_MISC 0x407 474 #define MSR_MC2_CTL 0x408 475 #define MSR_MC2_STATUS 0x409 476 #define MSR_MC2_ADDR 0x40a 477 #define MSR_MC2_MISC 0x40b 478 #define MSR_MC3_CTL 0x40c 479 #define MSR_MC3_STATUS 0x40d 480 #define MSR_MC3_ADDR 0x40e 481 #define MSR_MC3_MISC 0x40f 482 #define MSR_MC4_CTL 0x410 483 #define MSR_MC4_STATUS 0x411 484 #define MSR_MC4_ADDR 0x412 485 #define MSR_MC4_MISC 0x413 486 #define MSR_RAPL_POWER_UNIT 0x606 487 #define MSR_PKG_ENERGY_STATUS 0x611 488 #define MSR_DRAM_ENERGY_STATUS 0x619 489 #define MSR_PP0_ENERGY_STATUS 0x639 490 #define MSR_PP1_ENERGY_STATUS 0x641 491 #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */ 492 493 /* 494 * VMX MSRs 495 */ 496 #define MSR_VMX_BASIC 0x480 497 #define MSR_VMX_PINBASED_CTLS 0x481 498 #define MSR_VMX_PROCBASED_CTLS 0x482 499 #define MSR_VMX_EXIT_CTLS 0x483 500 #define MSR_VMX_ENTRY_CTLS 0x484 501 #define MSR_VMX_CR0_FIXED0 0x486 502 #define MSR_VMX_CR0_FIXED1 0x487 503 #define MSR_VMX_CR4_FIXED0 0x488 504 #define MSR_VMX_CR4_FIXED1 0x489 505 #define MSR_VMX_PROCBASED_CTLS2 0x48b 506 #define MSR_VMX_EPT_VPID_CAP 0x48c 507 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d 508 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e 509 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f 510 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490 511 512 /* 513 * X2APIC MSRs. 514 * Writes are not serializing. 515 */ 516 #define MSR_APIC_000 0x800 517 #define MSR_APIC_ID 0x802 518 #define MSR_APIC_VERSION 0x803 519 #define MSR_APIC_TPR 0x808 520 #define MSR_APIC_EOI 0x80b 521 #define MSR_APIC_LDR 0x80d 522 #define MSR_APIC_SVR 0x80f 523 #define MSR_APIC_ISR0 0x810 524 #define MSR_APIC_ISR1 0x811 525 #define MSR_APIC_ISR2 0x812 526 #define MSR_APIC_ISR3 0x813 527 #define MSR_APIC_ISR4 0x814 528 #define MSR_APIC_ISR5 0x815 529 #define MSR_APIC_ISR6 0x816 530 #define MSR_APIC_ISR7 0x817 531 #define MSR_APIC_TMR0 0x818 532 #define MSR_APIC_IRR0 0x820 533 #define MSR_APIC_ESR 0x828 534 #define MSR_APIC_LVT_CMCI 0x82F 535 #define MSR_APIC_ICR 0x830 536 #define MSR_APIC_LVT_TIMER 0x832 537 #define MSR_APIC_LVT_THERMAL 0x833 538 #define MSR_APIC_LVT_PCINT 0x834 539 #define MSR_APIC_LVT_LINT0 0x835 540 #define MSR_APIC_LVT_LINT1 0x836 541 #define MSR_APIC_LVT_ERROR 0x837 542 #define MSR_APIC_ICR_TIMER 0x838 543 #define MSR_APIC_CCR_TIMER 0x839 544 #define MSR_APIC_DCR_TIMER 0x83e 545 #define MSR_APIC_SELF_IPI 0x83f 546 547 #define MSR_IA32_XSS 0xda0 548 549 /* 550 * Intel Processor Trace (PT) MSRs. 551 */ 552 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */ 553 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */ 554 #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */ 555 #define RTIT_CTL_TRACEEN (1 << 0) 556 #define RTIT_CTL_CYCEN (1 << 1) 557 #define RTIT_CTL_OS (1 << 2) 558 #define RTIT_CTL_USER (1 << 3) 559 #define RTIT_CTL_PWREVTEN (1 << 4) 560 #define RTIT_CTL_FUPONPTW (1 << 5) 561 #define RTIT_CTL_FABRICEN (1 << 6) 562 #define RTIT_CTL_CR3FILTER (1 << 7) 563 #define RTIT_CTL_TOPA (1 << 8) 564 #define RTIT_CTL_MTCEN (1 << 9) 565 #define RTIT_CTL_TSCEN (1 << 10) 566 #define RTIT_CTL_DISRETC (1 << 11) 567 #define RTIT_CTL_PTWEN (1 << 12) 568 #define RTIT_CTL_BRANCHEN (1 << 13) 569 #define RTIT_CTL_MTC_FREQ_S 14 570 #define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S) 571 #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S) 572 #define RTIT_CTL_CYC_THRESH_S 19 573 #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S) 574 #define RTIT_CTL_PSB_FREQ_S 24 575 #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S) 576 #define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4) 577 #define RTIT_CTL_ADDR0_CFG_S 32 578 #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S) 579 #define RTIT_CTL_ADDR1_CFG_S 36 580 #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S) 581 #define RTIT_CTL_ADDR2_CFG_S 40 582 #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S) 583 #define RTIT_CTL_ADDR3_CFG_S 44 584 #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S) 585 #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */ 586 #define RTIT_STATUS_FILTEREN (1 << 0) 587 #define RTIT_STATUS_CONTEXTEN (1 << 1) 588 #define RTIT_STATUS_TRIGGEREN (1 << 2) 589 #define RTIT_STATUS_ERROR (1 << 4) 590 #define RTIT_STATUS_STOPPED (1 << 5) 591 #define RTIT_STATUS_PACKETBYTECNT_S 32 592 #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S) 593 #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */ 594 #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2) 595 #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2) 596 #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */ 597 #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */ 598 #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */ 599 #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */ 600 #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */ 601 #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */ 602 #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */ 603 #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */ 604 605 /* 606 * Constants related to MSR's. 607 */ 608 #define APICBASE_RESERVED 0x000002ff 609 #define APICBASE_BSP 0x00000100 610 #define APICBASE_X2APIC 0x00000400 611 #define APICBASE_ENABLED 0x00000800 612 #define APICBASE_ADDRESS 0xfffff000 613 614 /* MSR_IA32_FEATURE_CONTROL related */ 615 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 616 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 617 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 618 619 /* MSR IA32_MISC_ENABLE */ 620 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL 621 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL 622 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL 623 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL 624 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL 625 #define IA32_MISC_EN_MONE 0x0000000000040000ULL 626 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL 627 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL 628 #define IA32_MISC_EN_XDD 0x0000000400000000ULL 629 630 /* 631 * PAT modes. 632 */ 633 #define PAT_UNCACHEABLE 0x00 634 #define PAT_WRITE_COMBINING 0x01 635 #define PAT_WRITE_THROUGH 0x04 636 #define PAT_WRITE_PROTECTED 0x05 637 #define PAT_WRITE_BACK 0x06 638 #define PAT_UNCACHED 0x07 639 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 640 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 641 642 /* 643 * Constants related to MTRRs 644 */ 645 #define MTRR_UNCACHEABLE 0x00 646 #define MTRR_WRITE_COMBINING 0x01 647 #define MTRR_WRITE_THROUGH 0x04 648 #define MTRR_WRITE_PROTECTED 0x05 649 #define MTRR_WRITE_BACK 0x06 650 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 651 #define MTRR_N16K 16 652 #define MTRR_N4K 64 653 #define MTRR_CAP_WC 0x0000000000000400 654 #define MTRR_CAP_FIXED 0x0000000000000100 655 #define MTRR_CAP_VCNT 0x00000000000000ff 656 #define MTRR_DEF_ENABLE 0x0000000000000800 657 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 658 #define MTRR_DEF_TYPE 0x00000000000000ff 659 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 660 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 661 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 662 #define MTRR_PHYSMASK_VALID 0x0000000000000800 663 664 /* 665 * Cyrix configuration registers, accessible as IO ports. 666 */ 667 #define CCR0 0xc0 /* Configuration control register 0 */ 668 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 669 non-cacheable */ 670 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 671 #define CCR0_A20M 0x04 /* Enables A20M# input pin */ 672 #define CCR0_KEN 0x08 /* Enables KEN# input pin */ 673 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 674 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 675 state */ 676 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 677 assoc */ 678 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 679 680 #define CCR1 0xc1 /* Configuration control register 1 */ 681 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 682 #define CCR1_SMI 0x02 /* Enables SMM pins */ 683 #define CCR1_SMAC 0x04 /* System management memory access */ 684 #define CCR1_MMAC 0x08 /* Main memory access */ 685 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 686 #define CCR1_SM3 0x80 /* SMM address space address region 3 */ 687 688 #define CCR2 0xc2 689 #define CCR2_WB 0x02 /* Enables WB cache interface pins */ 690 #define CCR2_SADS 0x02 /* Slow ADS */ 691 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 692 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 693 #define CCR2_WT1 0x10 /* WT region 1 */ 694 #define CCR2_WPR1 0x10 /* Write-protect region 1 */ 695 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering 696 hold state. */ 697 #define CCR2_BWRT 0x40 /* Enables burst write cycles */ 698 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 699 700 #define CCR3 0xc3 701 #define CCR3_SMILOCK 0x01 /* SMM register lock */ 702 #define CCR3_NMI 0x02 /* Enables NMI during SMM */ 703 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 704 #define CCR3_SMMMODE 0x08 /* SMM Mode */ 705 #define CCR3_MAPEN0 0x10 /* Enables Map0 */ 706 #define CCR3_MAPEN1 0x20 /* Enables Map1 */ 707 #define CCR3_MAPEN2 0x40 /* Enables Map2 */ 708 #define CCR3_MAPEN3 0x80 /* Enables Map3 */ 709 710 #define CCR4 0xe8 711 #define CCR4_IOMASK 0x07 712 #define CCR4_MEM 0x08 /* Enables momory bypassing */ 713 #define CCR4_DTE 0x10 /* Enables directory table entry cache */ 714 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 715 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 716 717 #define CCR5 0xe9 718 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 719 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 720 #define CCR5_LBR1 0x10 /* Local bus region 1 */ 721 #define CCR5_ARREN 0x20 /* Enables ARR region */ 722 723 #define CCR6 0xea 724 725 #define CCR7 0xeb 726 727 /* Performance Control Register (5x86 only). */ 728 #define PCR0 0x20 729 #define PCR0_RSTK 0x01 /* Enables return stack */ 730 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 731 #define PCR0_LOOP 0x04 /* Enables loop */ 732 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 733 serialize pipe. */ 734 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 735 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 736 #define PCR0_LSSER 0x80 /* Disable reorder */ 737 738 /* Device Identification Registers */ 739 #define DIR0 0xfe 740 #define DIR1 0xff 741 742 /* 743 * Machine Check register constants. 744 */ 745 #define MCG_CAP_COUNT 0x000000ff 746 #define MCG_CAP_CTL_P 0x00000100 747 #define MCG_CAP_EXT_P 0x00000200 748 #define MCG_CAP_CMCI_P 0x00000400 749 #define MCG_CAP_TES_P 0x00000800 750 #define MCG_CAP_EXT_CNT 0x00ff0000 751 #define MCG_CAP_SER_P 0x01000000 752 #define MCG_STATUS_RIPV 0x00000001 753 #define MCG_STATUS_EIPV 0x00000002 754 #define MCG_STATUS_MCIP 0x00000004 755 #define MCG_CTL_ENABLE 0xffffffffffffffff 756 #define MCG_CTL_DISABLE 0x0000000000000000 757 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 758 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 759 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 760 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 761 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 762 #define MC_STATUS_MCA_ERROR 0x000000000000ffff 763 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 764 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 765 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 766 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 767 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 768 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 769 #define MC_STATUS_PCC 0x0200000000000000 770 #define MC_STATUS_ADDRV 0x0400000000000000 771 #define MC_STATUS_MISCV 0x0800000000000000 772 #define MC_STATUS_EN 0x1000000000000000 773 #define MC_STATUS_UC 0x2000000000000000 774 #define MC_STATUS_OVER 0x4000000000000000 775 #define MC_STATUS_VAL 0x8000000000000000 776 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 777 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 778 #define MC_CTL2_THRESHOLD 0x0000000000007fff 779 #define MC_CTL2_CMCI_EN 0x0000000040000000 780 #define MC_AMDNB_BANK 4 781 #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */ 782 #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */ 783 #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */ 784 #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */ 785 #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */ 786 #define MC_MISC_AMD_LVT_SHIFT 52 787 #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */ 788 #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */ 789 #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */ 790 #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */ 791 #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */ 792 #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */ 793 #define MC_MISC_AMD_CNT_SHIFT 32 794 #define MC_MISC_AMD_CNT_MAX 0xfff 795 #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */ 796 #define MC_MISC_AMD_PTR_SHIFT 24 797 798 /* 799 * The following four 3-byte registers control the non-cacheable regions. 800 * These registers must be written as three separate bytes. 801 * 802 * NCRx+0: A31-A24 of starting address 803 * NCRx+1: A23-A16 of starting address 804 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 805 * 806 * The non-cacheable region's starting address must be aligned to the 807 * size indicated by the NCR_SIZE_xx field. 808 */ 809 #define NCR1 0xc4 810 #define NCR2 0xc7 811 #define NCR3 0xca 812 #define NCR4 0xcd 813 814 #define NCR_SIZE_0K 0 815 #define NCR_SIZE_4K 1 816 #define NCR_SIZE_8K 2 817 #define NCR_SIZE_16K 3 818 #define NCR_SIZE_32K 4 819 #define NCR_SIZE_64K 5 820 #define NCR_SIZE_128K 6 821 #define NCR_SIZE_256K 7 822 #define NCR_SIZE_512K 8 823 #define NCR_SIZE_1M 9 824 #define NCR_SIZE_2M 10 825 #define NCR_SIZE_4M 11 826 #define NCR_SIZE_8M 12 827 #define NCR_SIZE_16M 13 828 #define NCR_SIZE_32M 14 829 #define NCR_SIZE_4G 15 830 831 /* 832 * The address region registers are used to specify the location and 833 * size for the eight address regions. 834 * 835 * ARRx + 0: A31-A24 of start address 836 * ARRx + 1: A23-A16 of start address 837 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 838 */ 839 #define ARR0 0xc4 840 #define ARR1 0xc7 841 #define ARR2 0xca 842 #define ARR3 0xcd 843 #define ARR4 0xd0 844 #define ARR5 0xd3 845 #define ARR6 0xd6 846 #define ARR7 0xd9 847 848 #define ARR_SIZE_0K 0 849 #define ARR_SIZE_4K 1 850 #define ARR_SIZE_8K 2 851 #define ARR_SIZE_16K 3 852 #define ARR_SIZE_32K 4 853 #define ARR_SIZE_64K 5 854 #define ARR_SIZE_128K 6 855 #define ARR_SIZE_256K 7 856 #define ARR_SIZE_512K 8 857 #define ARR_SIZE_1M 9 858 #define ARR_SIZE_2M 10 859 #define ARR_SIZE_4M 11 860 #define ARR_SIZE_8M 12 861 #define ARR_SIZE_16M 13 862 #define ARR_SIZE_32M 14 863 #define ARR_SIZE_4G 15 864 865 /* 866 * The region control registers specify the attributes associated with 867 * the ARRx addres regions. 868 */ 869 #define RCR0 0xdc 870 #define RCR1 0xdd 871 #define RCR2 0xde 872 #define RCR3 0xdf 873 #define RCR4 0xe0 874 #define RCR5 0xe1 875 #define RCR6 0xe2 876 #define RCR7 0xe3 877 878 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 879 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 880 #define RCR_WWO 0x02 /* Weak write ordering. */ 881 #define RCR_WL 0x04 /* Weak locking. */ 882 #define RCR_WG 0x08 /* Write gathering. */ 883 #define RCR_WT 0x10 /* Write-through. */ 884 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 885 886 /* AMD Write Allocate Top-Of-Memory and Control Register */ 887 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 888 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 889 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 890 891 /* AMD64 MSR's */ 892 #define MSR_EFER 0xc0000080 /* extended features */ 893 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 894 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 895 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 896 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 897 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 898 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 899 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 900 #define MSR_PERFEVSEL0 0xc0010000 901 #define MSR_PERFEVSEL1 0xc0010001 902 #define MSR_PERFEVSEL2 0xc0010002 903 #define MSR_PERFEVSEL3 0xc0010003 904 #define MSR_K7_PERFCTR0 0xc0010004 905 #define MSR_K7_PERFCTR1 0xc0010005 906 #define MSR_K7_PERFCTR2 0xc0010006 907 #define MSR_K7_PERFCTR3 0xc0010007 908 #define MSR_SYSCFG 0xc0010010 909 #define MSR_HWCR 0xc0010015 910 #define MSR_IORRBASE0 0xc0010016 911 #define MSR_IORRMASK0 0xc0010017 912 #define MSR_IORRBASE1 0xc0010018 913 #define MSR_IORRMASK1 0xc0010019 914 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 915 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 916 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ 917 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ 918 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ 919 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ 920 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ 921 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ 922 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ 923 #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ 924 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ 925 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 926 #define MSR_MC0_CTL_MASK 0xc0010044 927 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ 928 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ 929 930 /* MSR_VM_CR related */ 931 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ 932 933 /* VIA ACE crypto featureset: for via_feature_rng */ 934 #define VIA_HAS_RNG 1 /* cpu has RNG */ 935 936 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 937 #define VIA_HAS_AES 1 /* cpu has AES */ 938 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 939 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 940 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 941 942 /* Centaur Extended Feature flags */ 943 #define VIA_CPUID_HAS_RNG 0x000004 944 #define VIA_CPUID_DO_RNG 0x000008 945 #define VIA_CPUID_HAS_ACE 0x000040 946 #define VIA_CPUID_DO_ACE 0x000080 947 #define VIA_CPUID_HAS_ACE2 0x000100 948 #define VIA_CPUID_DO_ACE2 0x000200 949 #define VIA_CPUID_HAS_PHE 0x000400 950 #define VIA_CPUID_DO_PHE 0x000800 951 #define VIA_CPUID_HAS_PMM 0x001000 952 #define VIA_CPUID_DO_PMM 0x002000 953 954 /* VIA ACE xcrypt-* instruction context control options */ 955 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 956 #define VIA_CRYPT_CWLO_ALG_M 0x00000070 957 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 958 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 959 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 960 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 961 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 962 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 963 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 964 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 965 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 966 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 967 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 968 969 #endif /* !_MACHINE_SPECIALREG_H_ */ 970