xref: /freebsd/sys/x86/include/specialreg.h (revision a90b9d0159070121c221b966469c3e36d912bf82)
1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
3  *
4  * Copyright (c) 1991 The Regents of the University of California.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. Neither the name of the University nor the names of its contributors
16  *    may be used to endorse or promote products derived from this software
17  *    without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  */
31 
32 #ifndef _MACHINE_SPECIALREG_H_
33 #define	_MACHINE_SPECIALREG_H_
34 
35 /*
36  * Bits in 386 special registers:
37  */
38 #define	CR0_PE	0x00000001	/* Protected mode Enable */
39 #define	CR0_MP	0x00000002	/* "Math" (fpu) Present */
40 #define	CR0_EM	0x00000004	/* EMulate FPU instructions. (trap ESC only) */
41 #define	CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
42 #define	CR0_PG	0x80000000	/* PaGing enable */
43 
44 /*
45  * Bits in 486 special registers:
46  */
47 #define	CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
48 #define	CR0_WP	0x00010000	/* Write Protect (honor page protect in
49 							   all modes) */
50 #define	CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
51 #define	CR0_NW  0x20000000	/* Not Write-through */
52 #define	CR0_CD  0x40000000	/* Cache Disable */
53 
54 #define	CR3_PCID_SAVE 0x8000000000000000
55 #define	CR3_PCID_MASK 0xfff
56 
57 /*
58  * Bits in PPro special registers
59  */
60 #define	CR4_VME	0x00000001	/* Virtual 8086 mode extensions */
61 #define	CR4_PVI	0x00000002	/* Protected-mode virtual interrupts */
62 #define	CR4_TSD	0x00000004	/* Time stamp disable */
63 #define	CR4_DE	0x00000008	/* Debugging extensions */
64 #define	CR4_PSE	0x00000010	/* Page size extensions */
65 #define	CR4_PAE	0x00000020	/* Physical address extension */
66 #define	CR4_MCE	0x00000040	/* Machine check enable */
67 #define	CR4_PGE	0x00000080	/* Page global enable */
68 #define	CR4_PCE	0x00000100	/* Performance monitoring counter enable */
69 #define	CR4_FXSR 0x00000200	/* Fast FPU save/restore used by OS */
70 #define	CR4_XMM	0x00000400	/* enable SIMD/MMX2 to use except 16 */
71 #define	CR4_UMIP 0x00000800	/* User Mode Instruction Prevention */
72 #define	CR4_LA57 0x00001000	/* Enable 5-level paging */
73 #define	CR4_VMXE 0x00002000	/* enable VMX operation (Intel-specific) */
74 #define	CR4_FSGSBASE 0x00010000	/* Enable FS/GS BASE accessing instructions */
75 #define	CR4_PCIDE 0x00020000	/* Enable Context ID */
76 #define	CR4_XSAVE 0x00040000	/* XSETBV/XGETBV */
77 #define	CR4_SMEP 0x00100000	/* Supervisor-Mode Execution Prevention */
78 #define	CR4_SMAP 0x00200000	/* Supervisor-Mode Access Prevention */
79 #define	CR4_PKE	0x00400000	/* Protection Keys Enable */
80 
81 /*
82  * Bits in AMD64 special registers.  EFER is 64 bits wide.
83  */
84 #define	EFER_SCE 0x000000001	/* System Call Extensions (R/W) */
85 #define	EFER_LME 0x000000100	/* Long mode enable (R/W) */
86 #define	EFER_LMA 0x000000400	/* Long mode active (R) */
87 #define	EFER_NXE 0x000000800	/* PTE No-Execute bit enable (R/W) */
88 #define	EFER_SVM 0x000001000	/* SVM enable bit for AMD, reserved for Intel */
89 #define	EFER_LMSLE 0x000002000	/* Long Mode Segment Limit Enable */
90 #define	EFER_FFXSR 0x000004000	/* Fast FXSAVE/FSRSTOR */
91 #define	EFER_TCE   0x000008000	/* Translation Cache Extension */
92 #define	EFER_MCOMMIT	0x00020000	/* Enable MCOMMIT (AMD) */
93 
94 /*
95  * Intel Extended Features registers
96  */
97 #define	XCR0	0		/* XFEATURE_ENABLED_MASK register */
98 
99 #define	XFEATURE_ENABLED_X87		0x00000001
100 #define	XFEATURE_ENABLED_SSE		0x00000002
101 #define	XFEATURE_ENABLED_YMM_HI128	0x00000004
102 #define	XFEATURE_ENABLED_AVX		XFEATURE_ENABLED_YMM_HI128
103 #define	XFEATURE_ENABLED_BNDREGS	0x00000008
104 #define	XFEATURE_ENABLED_BNDCSR		0x00000010
105 #define	XFEATURE_ENABLED_OPMASK		0x00000020
106 #define	XFEATURE_ENABLED_ZMM_HI256	0x00000040
107 #define	XFEATURE_ENABLED_HI16_ZMM	0x00000080
108 #define	XFEATURE_ENABLED_PKRU		0x00000200
109 #define	XFEATURE_ENABLED_TILECONFIG	0x00020000
110 #define	XFEATURE_ENABLED_TILEDATA	0x00040000
111 
112 #define	XFEATURE_AVX					\
113     (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
114 #define	XFEATURE_AVX512						\
115     (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 |	\
116     XFEATURE_ENABLED_HI16_ZMM)
117 #define	XFEATURE_MPX					\
118     (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
119 
120 /*
121  * CPUID instruction features register
122  */
123 #define	CPUID_FPU	0x00000001
124 #define	CPUID_VME	0x00000002
125 #define	CPUID_DE	0x00000004
126 #define	CPUID_PSE	0x00000008
127 #define	CPUID_TSC	0x00000010
128 #define	CPUID_MSR	0x00000020
129 #define	CPUID_PAE	0x00000040
130 #define	CPUID_MCE	0x00000080
131 #define	CPUID_CX8	0x00000100
132 #define	CPUID_APIC	0x00000200
133 #define	CPUID_B10	0x00000400
134 #define	CPUID_SEP	0x00000800
135 #define	CPUID_MTRR	0x00001000
136 #define	CPUID_PGE	0x00002000
137 #define	CPUID_MCA	0x00004000
138 #define	CPUID_CMOV	0x00008000
139 #define	CPUID_PAT	0x00010000
140 #define	CPUID_PSE36	0x00020000
141 #define	CPUID_PSN	0x00040000
142 #define	CPUID_CLFSH	0x00080000
143 #define	CPUID_B20	0x00100000
144 #define	CPUID_DS	0x00200000
145 #define	CPUID_ACPI	0x00400000
146 #define	CPUID_MMX	0x00800000
147 #define	CPUID_FXSR	0x01000000
148 #define	CPUID_SSE	0x02000000
149 #define	CPUID_XMM	0x02000000
150 #define	CPUID_SSE2	0x04000000
151 #define	CPUID_SS	0x08000000
152 #define	CPUID_HTT	0x10000000
153 #define	CPUID_TM	0x20000000
154 #define	CPUID_IA64	0x40000000
155 #define	CPUID_PBE	0x80000000
156 
157 #define	CPUID2_SSE3	0x00000001
158 #define	CPUID2_PCLMULQDQ 0x00000002
159 #define	CPUID2_DTES64	0x00000004
160 #define	CPUID2_MON	0x00000008
161 #define	CPUID2_DS_CPL	0x00000010
162 #define	CPUID2_VMX	0x00000020
163 #define	CPUID2_SMX	0x00000040
164 #define	CPUID2_EST	0x00000080
165 #define	CPUID2_TM2	0x00000100
166 #define	CPUID2_SSSE3	0x00000200
167 #define	CPUID2_CNXTID	0x00000400
168 #define	CPUID2_SDBG	0x00000800
169 #define	CPUID2_FMA	0x00001000
170 #define	CPUID2_CX16	0x00002000
171 #define	CPUID2_XTPR	0x00004000
172 #define	CPUID2_PDCM	0x00008000
173 #define	CPUID2_PCID	0x00020000
174 #define	CPUID2_DCA	0x00040000
175 #define	CPUID2_SSE41	0x00080000
176 #define	CPUID2_SSE42	0x00100000
177 #define	CPUID2_X2APIC	0x00200000
178 #define	CPUID2_MOVBE	0x00400000
179 #define	CPUID2_POPCNT	0x00800000
180 #define	CPUID2_TSCDLT	0x01000000
181 #define	CPUID2_AESNI	0x02000000
182 #define	CPUID2_XSAVE	0x04000000
183 #define	CPUID2_OSXSAVE	0x08000000
184 #define	CPUID2_AVX	0x10000000
185 #define	CPUID2_F16C	0x20000000
186 #define	CPUID2_RDRAND	0x40000000
187 #define	CPUID2_HV	0x80000000
188 
189 /* Intel Processor Trace CPUID. */
190 
191 /* Leaf 0 ebx. */
192 #define	CPUPT_CR3		(1 << 0)	/* CR3 Filtering Support */
193 #define	CPUPT_PSB		(1 << 1)	/* Configurable PSB and Cycle-Accurate Mode Supported */
194 #define	CPUPT_IPF		(1 << 2)	/* IP Filtering and TraceStop supported */
195 #define	CPUPT_MTC		(1 << 3)	/* MTC Supported */
196 #define	CPUPT_PRW		(1 << 4)	/* PTWRITE Supported */
197 #define	CPUPT_PWR		(1 << 5)	/* Power Event Trace Supported */
198 
199 /* Leaf 0 ecx. */
200 #define	CPUPT_TOPA		(1 << 0)	/* ToPA Output Supported */
201 #define	CPUPT_TOPA_MULTI	(1 << 1)	/* ToPA Tables Allow Multiple Output Entries */
202 #define	CPUPT_SINGLE		(1 << 2)	/* Single-Range Output Supported */
203 #define	CPUPT_TT_OUT		(1 << 3)	/* Output to Trace Transport Subsystem Supported */
204 #define	CPUPT_LINEAR_IP		(1 << 31)	/* IP Payloads are Linear IP, otherwise IP is effective */
205 
206 /* Leaf 1 eax. */
207 #define	CPUPT_NADDR_S		0	/* Number of Address Ranges */
208 #define	CPUPT_NADDR_M		(0x7 << CPUPT_NADDR_S)
209 #define	CPUPT_MTC_BITMAP_S	16	/* Bitmap of supported MTC Period Encodings */
210 #define	CPUPT_MTC_BITMAP_M	(0xffff << CPUPT_MTC_BITMAP_S)
211 
212 /* Leaf 1 ebx. */
213 #define	CPUPT_CT_BITMAP_S	0	/* Bitmap of supported Cycle Threshold values */
214 #define	CPUPT_CT_BITMAP_M	(0xffff << CPUPT_CT_BITMAP_S)
215 #define	CPUPT_PFE_BITMAP_S	16	/* Bitmap of supported Configurable PSB Frequency encoding */
216 #define	CPUPT_PFE_BITMAP_M	(0xffff << CPUPT_PFE_BITMAP_S)
217 
218 /*
219  * Important bits in the AMD extended cpuid flags
220  */
221 #define	AMDID_SYSCALL	0x00000800
222 #define	AMDID_MP	0x00080000
223 #define	AMDID_NX	0x00100000
224 #define	AMDID_EXT_MMX	0x00400000
225 #define	AMDID_FFXSR	0x02000000
226 #define	AMDID_PAGE1GB	0x04000000
227 #define	AMDID_RDTSCP	0x08000000
228 #define	AMDID_LM	0x20000000
229 #define	AMDID_EXT_3DNOW	0x40000000
230 #define	AMDID_3DNOW	0x80000000
231 
232 #define	AMDID2_LAHF	0x00000001
233 #define	AMDID2_CMP	0x00000002
234 #define	AMDID2_SVM	0x00000004
235 #define	AMDID2_EXT_APIC	0x00000008
236 #define	AMDID2_CR8	0x00000010
237 #define	AMDID2_ABM	0x00000020
238 #define	AMDID2_SSE4A	0x00000040
239 #define	AMDID2_MAS	0x00000080
240 #define	AMDID2_PREFETCH	0x00000100
241 #define	AMDID2_OSVW	0x00000200
242 #define	AMDID2_IBS	0x00000400
243 #define	AMDID2_XOP	0x00000800
244 #define	AMDID2_SKINIT	0x00001000
245 #define	AMDID2_WDT	0x00002000
246 #define	AMDID2_LWP	0x00008000
247 #define	AMDID2_FMA4	0x00010000
248 #define	AMDID2_TCE	0x00020000
249 #define	AMDID2_NODE_ID	0x00080000
250 #define	AMDID2_TBM	0x00200000
251 #define	AMDID2_TOPOLOGY	0x00400000
252 #define	AMDID2_PCXC	0x00800000
253 #define	AMDID2_PNXC	0x01000000
254 #define	AMDID2_DBE	0x04000000
255 #define	AMDID2_PTSC	0x08000000
256 #define	AMDID2_PTSCEL2I	0x10000000
257 #define	AMDID2_MWAITX	0x20000000
258 
259 /*
260  * CPUID instruction 1 eax info
261  */
262 #define	CPUID_STEPPING		0x0000000f
263 #define	CPUID_MODEL		0x000000f0
264 #define	CPUID_FAMILY		0x00000f00
265 #define	CPUID_EXT_MODEL		0x000f0000
266 #define	CPUID_EXT_FAMILY	0x0ff00000
267 #ifdef __i386__
268 #define	CPUID_TO_MODEL(id) \
269     ((((id) & CPUID_MODEL) >> 4) | \
270     ((((id) & CPUID_FAMILY) >= 0x600) ? \
271     (((id) & CPUID_EXT_MODEL) >> 12) : 0))
272 #define	CPUID_TO_FAMILY(id) \
273     ((((id) & CPUID_FAMILY) >> 8) + \
274     ((((id) & CPUID_FAMILY) == 0xf00) ? \
275     (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
276 #else
277 #define	CPUID_TO_MODEL(id) \
278     ((((id) & CPUID_MODEL) >> 4) | \
279     (((id) & CPUID_EXT_MODEL) >> 12))
280 #define	CPUID_TO_FAMILY(id) \
281     ((((id) & CPUID_FAMILY) >> 8) + \
282     (((id) & CPUID_EXT_FAMILY) >> 20))
283 #endif
284 #define CPUID_TO_STEPPING(id) ((id) & CPUID_STEPPING)
285 
286 /*
287  * CPUID instruction 1 ebx info
288  */
289 #define	CPUID_BRAND_INDEX	0x000000ff
290 #define	CPUID_CLFUSH_SIZE	0x0000ff00
291 #define	CPUID_HTT_CORES		0x00ff0000
292 #define	CPUID_LOCAL_APIC_ID	0xff000000
293 
294 /*
295  * CPUID instruction 5 info
296  */
297 #define	CPUID5_MON_MIN_SIZE	0x0000ffff	/* eax */
298 #define	CPUID5_MON_MAX_SIZE	0x0000ffff	/* ebx */
299 #define	CPUID5_MON_MWAIT_EXT	0x00000001	/* ecx */
300 #define	CPUID5_MWAIT_INTRBREAK	0x00000002	/* ecx */
301 
302 /*
303  * MWAIT cpu power states.  Lower 4 bits are sub-states.
304  */
305 #define	MWAIT_C0	0xf0
306 #define	MWAIT_C1	0x00
307 #define	MWAIT_C2	0x10
308 #define	MWAIT_C3	0x20
309 #define	MWAIT_C4	0x30
310 
311 /*
312  * MWAIT extensions.
313  */
314 /* Interrupt breaks MWAIT even when masked. */
315 #define	MWAIT_INTRBREAK		0x00000001
316 
317 /*
318  * CPUID leaf 6: Thermal and Power management.
319  */
320 /* Eax. */
321 #define	CPUTPM1_SENSOR			0x00000001
322 #define	CPUTPM1_TURBO			0x00000002
323 #define	CPUTPM1_ARAT			0x00000004
324 #define	CPUTPM1_PLN			0x00000010
325 #define	CPUTPM1_ECMD			0x00000020
326 #define	CPUTPM1_PTM			0x00000040
327 #define	CPUTPM1_HWP			0x00000080
328 #define	CPUTPM1_HWP_NOTIFICATION	0x00000100
329 #define	CPUTPM1_HWP_ACTIVITY_WINDOW	0x00000200
330 #define	CPUTPM1_HWP_PERF_PREF		0x00000400
331 #define	CPUTPM1_HWP_PKG			0x00000800
332 #define	CPUTPM1_HDC			0x00002000
333 #define	CPUTPM1_TURBO30			0x00004000
334 #define	CPUTPM1_HWP_CAPABILITIES	0x00008000
335 #define	CPUTPM1_HWP_PECI_OVR		0x00010000
336 #define	CPUTPM1_HWP_FLEXIBLE		0x00020000
337 #define	CPUTPM1_HWP_FAST_MSR		0x00040000
338 #define	CPUTPM1_HW_FEEDBACK		0x00080000
339 #define	CPUTPM1_HWP_IGN_IDLE		0x00100000
340 #define	CPUTPM1_THREAD_DIRECTOR		0x00800000
341 
342 /* Ebx. */
343 #define	CPUTPM_B_NSENSINTTHRESH		0x0000000f
344 
345 /* Ecx. */
346 #define	CPUID_PERF_STAT			0x00000001
347 #define	CPUID_PERF_BIAS			0x00000008
348 #define	CPUID_PERF_TD_CLASSES		0x0000ff00
349 
350 /* Edx. */
351 #define	CPUID_HF_PERFORMANCE		0x00000001
352 #define	CPUID_HF_EFFICIENCY		0x00000002
353 #define	CPUID_TD_CAPABLITIES		0x0000000f
354 #define	CPUID_TD_TBLPAGES		0x00000f00
355 
356 /*
357  * CPUID instruction 0xb ebx info.
358  */
359 #define	CPUID_TYPE_INVAL	0
360 #define	CPUID_TYPE_SMT		1
361 #define	CPUID_TYPE_CORE		2
362 
363 /*
364  * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
365  */
366 #define	CPUID_EXTSTATE_XSAVEOPT	0x00000001
367 #define	CPUID_EXTSTATE_XSAVEC	0x00000002
368 #define	CPUID_EXTSTATE_XINUSE	0x00000004
369 #define	CPUID_EXTSTATE_XSAVES	0x00000008
370 
371 /*
372  * AMD extended function 8000_0007h ebx info
373  */
374 #define	AMDRAS_MCA_OF_RECOV	0x00000001
375 #define	AMDRAS_SUCCOR		0x00000002
376 #define	AMDRAS_HW_ASSERT	0x00000004
377 #define	AMDRAS_SCALABLE_MCA	0x00000008
378 #define	AMDRAS_PFEH_SUPPORT	0x00000010
379 
380 /*
381  * AMD extended function 8000_0007h edx info
382  */
383 #define	AMDPM_TS		0x00000001
384 #define	AMDPM_FID		0x00000002
385 #define	AMDPM_VID		0x00000004
386 #define	AMDPM_TTP		0x00000008
387 #define	AMDPM_TM		0x00000010
388 #define	AMDPM_STC		0x00000020
389 #define	AMDPM_100MHZ_STEPS	0x00000040
390 #define	AMDPM_HW_PSTATE		0x00000080
391 #define	AMDPM_TSC_INVARIANT	0x00000100
392 #define	AMDPM_CPB		0x00000200
393 
394 /*
395  * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions)
396  */
397 #define	AMDFEID_CLZERO		0x00000001
398 #define	AMDFEID_IRPERF		0x00000002
399 #define	AMDFEID_XSAVEERPTR	0x00000004
400 #define	AMDFEID_INVLPGB		0x00000008
401 #define	AMDFEID_RDPRU		0x00000010
402 #define	AMDFEID_BE		0x00000040
403 #define	AMDFEID_MCOMMIT		0x00000100
404 #define	AMDFEID_WBNOINVD	0x00000200
405 #define	AMDFEID_IBPB		0x00001000
406 #define	AMDFEID_INT_WBINVD	0x00002000
407 #define	AMDFEID_IBRS		0x00004000
408 #define	AMDFEID_STIBP		0x00008000
409 /* The below are only defined if the corresponding base feature above exists. */
410 #define	AMDFEID_IBRS_ALWAYSON	0x00010000
411 #define	AMDFEID_STIBP_ALWAYSON	0x00020000
412 #define	AMDFEID_PREFER_IBRS	0x00040000
413 #define	AMDFEID_SAMEMODE_IBRS	0x00080000
414 #define	AMDFEID_NO_LMSLE	0x00100000
415 #define	AMDFEID_INVLPGB_NEST	0x00200000
416 #define	AMDFEID_PPIN		0x00800000
417 #define	AMDFEID_SSBD		0x01000000
418 /* SSBD via MSRC001_011F instead of MSR 0x48: */
419 #define	AMDFEID_VIRT_SSBD	0x02000000
420 #define	AMDFEID_SSB_NO		0x04000000
421 #define	AMDFEID_CPPC		0x08000000
422 #define	AMDFEID_PSFD		0x10000000
423 #define	AMDFEID_BTC_NO		0x20000000
424 #define	AMDFEID_IBPB_RET	0x40000000
425 
426 /*
427  * AMD extended function 8000_0008h ecx info
428  */
429 #define	AMDID_CMP_CORES		0x000000ff
430 #define	AMDID_COREID_SIZE	0x0000f000
431 #define	AMDID_COREID_SIZE_SHIFT	12
432 
433 /*
434  * AMD extended function 8000_0008h edx info
435  */
436 #define	AMDID_INVLPGB_MAXCNT	0x0000ffff
437 #define	AMDID_RDPRU_SHIFT	16
438 #define	AMDID_RDPRU_ID		0xffff0000
439 
440 /*
441  * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
442  */
443 #define	CPUID_STDEXT_FSGSBASE	0x00000001
444 #define	CPUID_STDEXT_TSC_ADJUST	0x00000002
445 #define	CPUID_STDEXT_SGX	0x00000004
446 #define	CPUID_STDEXT_BMI1	0x00000008
447 #define	CPUID_STDEXT_HLE	0x00000010
448 #define	CPUID_STDEXT_AVX2	0x00000020
449 #define	CPUID_STDEXT_FDP_EXC	0x00000040
450 #define	CPUID_STDEXT_SMEP	0x00000080
451 #define	CPUID_STDEXT_BMI2	0x00000100
452 #define	CPUID_STDEXT_ERMS	0x00000200
453 #define	CPUID_STDEXT_INVPCID	0x00000400
454 #define	CPUID_STDEXT_RTM	0x00000800
455 #define	CPUID_STDEXT_PQM	0x00001000
456 #define	CPUID_STDEXT_NFPUSG	0x00002000
457 #define	CPUID_STDEXT_MPX	0x00004000
458 #define	CPUID_STDEXT_PQE	0x00008000
459 #define	CPUID_STDEXT_AVX512F	0x00010000
460 #define	CPUID_STDEXT_AVX512DQ	0x00020000
461 #define	CPUID_STDEXT_RDSEED	0x00040000
462 #define	CPUID_STDEXT_ADX	0x00080000
463 #define	CPUID_STDEXT_SMAP	0x00100000
464 #define	CPUID_STDEXT_AVX512IFMA	0x00200000
465 /* Formerly PCOMMIT */
466 #define	CPUID_STDEXT_CLFLUSHOPT	0x00800000
467 #define	CPUID_STDEXT_CLWB	0x01000000
468 #define	CPUID_STDEXT_PROCTRACE	0x02000000
469 #define	CPUID_STDEXT_AVX512PF	0x04000000
470 #define	CPUID_STDEXT_AVX512ER	0x08000000
471 #define	CPUID_STDEXT_AVX512CD	0x10000000
472 #define	CPUID_STDEXT_SHA	0x20000000
473 #define	CPUID_STDEXT_AVX512BW	0x40000000
474 #define	CPUID_STDEXT_AVX512VL	0x80000000
475 
476 /*
477  * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
478  */
479 #define	CPUID_STDEXT2_PREFETCHWT1 	0x00000001
480 #define	CPUID_STDEXT2_AVX512VBMI	0x00000002
481 #define	CPUID_STDEXT2_UMIP		0x00000004
482 #define	CPUID_STDEXT2_PKU		0x00000008
483 #define	CPUID_STDEXT2_OSPKE		0x00000010
484 #define	CPUID_STDEXT2_WAITPKG		0x00000020
485 #define	CPUID_STDEXT2_AVX512VBMI2	0x00000040
486 #define	CPUID_STDEXT2_GFNI		0x00000100
487 #define	CPUID_STDEXT2_VAES		0x00000200
488 #define	CPUID_STDEXT2_VPCLMULQDQ	0x00000400
489 #define	CPUID_STDEXT2_AVX512VNNI	0x00000800
490 #define	CPUID_STDEXT2_AVX512BITALG	0x00001000
491 #define	CPUID_STDEXT2_TME		0x00002000
492 #define	CPUID_STDEXT2_AVX512VPOPCNTDQ	0x00004000
493 #define	CPUID_STDEXT2_LA57		0x00010000
494 #define	CPUID_STDEXT2_RDPID		0x00400000
495 #define	CPUID_STDEXT2_CLDEMOTE		0x02000000
496 #define	CPUID_STDEXT2_MOVDIRI		0x08000000
497 #define	CPUID_STDEXT2_MOVDIR64B		0x10000000
498 #define	CPUID_STDEXT2_ENQCMD		0x20000000
499 #define	CPUID_STDEXT2_SGXLC		0x40000000
500 
501 /*
502  * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
503  */
504 #define	CPUID_STDEXT3_AVX5124VNNIW	0x00000004
505 #define	CPUID_STDEXT3_AVX5124FMAPS	0x00000008
506 #define	CPUID_STDEXT3_FSRM		0x00000010
507 #define	CPUID_STDEXT3_AVX512VP2INTERSECT	0x00000100
508 #define	CPUID_STDEXT3_MCUOPT		0x00000200
509 #define	CPUID_STDEXT3_MD_CLEAR		0x00000400
510 #define	CPUID_STDEXT3_TSXFA		0x00002000
511 #define	CPUID_STDEXT3_PCONFIG		0x00040000
512 #define	CPUID_STDEXT3_IBPB		0x04000000
513 #define	CPUID_STDEXT3_STIBP		0x08000000
514 #define	CPUID_STDEXT3_L1D_FLUSH		0x10000000
515 #define	CPUID_STDEXT3_ARCH_CAP		0x20000000
516 #define	CPUID_STDEXT3_CORE_CAP		0x40000000
517 #define	CPUID_STDEXT3_SSBD		0x80000000
518 
519 /* CPUID_HYBRID_ID leaf 0x1a */
520 #define	CPUID_HYBRID_CORE_MASK	0xff000000
521 #define	CPUID_HYBRID_SMALL_CORE	0x20000000
522 #define	CPUID_HYBRID_LARGE_CORE	0x40000000
523 
524 /* MSR IA32_ARCH_CAP(ABILITIES) bits */
525 #define	IA32_ARCH_CAP_RDCL_NO	0x00000001
526 #define	IA32_ARCH_CAP_IBRS_ALL	0x00000002
527 #define	IA32_ARCH_CAP_RSBA	0x00000004
528 #define	IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY	0x00000008
529 #define	IA32_ARCH_CAP_SSB_NO	0x00000010
530 #define	IA32_ARCH_CAP_MDS_NO	0x00000020
531 #define	IA32_ARCH_CAP_IF_PSCHANGE_MC_NO	0x00000040
532 #define	IA32_ARCH_CAP_TSX_CTRL	0x00000080
533 #define	IA32_ARCH_CAP_TAA_NO	0x00000100
534 
535 /* MSR IA32_TSX_CTRL bits */
536 #define	IA32_TSX_CTRL_RTM_DISABLE	0x00000001
537 #define	IA32_TSX_CTRL_TSX_CPUID_CLEAR	0x00000002
538 
539 /*
540  * CPUID manufacturers identifiers
541  */
542 #define	AMD_VENDOR_ID		"AuthenticAMD"
543 #define	CENTAUR_VENDOR_ID	"CentaurHauls"
544 #define	CYRIX_VENDOR_ID		"CyrixInstead"
545 #define	INTEL_VENDOR_ID		"GenuineIntel"
546 #define	NEXGEN_VENDOR_ID	"NexGenDriven"
547 #define	NSC_VENDOR_ID		"Geode by NSC"
548 #define	RISE_VENDOR_ID		"RiseRiseRise"
549 #define	SIS_VENDOR_ID		"SiS SiS SiS "
550 #define	TRANSMETA_VENDOR_ID	"GenuineTMx86"
551 #define	UMC_VENDOR_ID		"UMC UMC UMC "
552 #define	HYGON_VENDOR_ID		"HygonGenuine"
553 
554 /*
555  * Model-specific registers for the i386 family
556  */
557 #define	MSR_P5_MC_ADDR		0x000
558 #define	MSR_P5_MC_TYPE		0x001
559 #define	MSR_TSC			0x010
560 #define	MSR_P5_CESR		0x011
561 #define	MSR_P5_CTR0		0x012
562 #define	MSR_P5_CTR1		0x013
563 #define	MSR_IA32_PLATFORM_ID	0x017
564 #define	MSR_APICBASE		0x01b
565 #define	MSR_EBL_CR_POWERON	0x02a
566 #define	MSR_TEST_CTL		0x033
567 #define	MSR_IA32_FEATURE_CONTROL 0x03a
568 #define	MSR_IA32_SPEC_CTRL	0x048
569 #define	MSR_IA32_PRED_CMD	0x049
570 #define	MSR_BIOS_UPDT_TRIG	0x079
571 #define	MSR_BBL_CR_D0		0x088
572 #define	MSR_BBL_CR_D1		0x089
573 #define	MSR_BBL_CR_D2		0x08a
574 #define	MSR_BIOS_SIGN		0x08b
575 #define	MSR_PERFCTR0		0x0c1
576 #define	MSR_PERFCTR1		0x0c2
577 #define	MSR_PLATFORM_INFO	0x0ce
578 #define	MSR_MPERF		0x0e7
579 #define	MSR_APERF		0x0e8
580 #define	MSR_IA32_EXT_CONFIG	0x0ee	/* Undocumented. Core Solo/Duo only */
581 #define	MSR_MTRRcap		0x0fe
582 #define	MSR_IA32_ARCH_CAP	0x10a
583 #define	MSR_IA32_FLUSH_CMD	0x10b
584 #define	MSR_TSX_FORCE_ABORT	0x10f
585 #define	MSR_BBL_CR_ADDR		0x116
586 #define	MSR_BBL_CR_DECC		0x118
587 #define	MSR_BBL_CR_CTL		0x119
588 #define	MSR_BBL_CR_TRIG		0x11a
589 #define	MSR_BBL_CR_BUSY		0x11b
590 #define	MSR_BBL_CR_CTL3		0x11e
591 #define	MSR_IA32_TSX_CTRL	0x122
592 #define	MSR_IA32_MCU_OPT_CTRL	0x123
593 #define	MSR_MISC_FEATURE_ENABLES	0x140
594 #define	MSR_SYSENTER_CS_MSR	0x174
595 #define	MSR_SYSENTER_ESP_MSR	0x175
596 #define	MSR_SYSENTER_EIP_MSR	0x176
597 #define	MSR_MCG_CAP		0x179
598 #define	MSR_MCG_STATUS		0x17a
599 #define	MSR_MCG_CTL		0x17b
600 #define	MSR_EVNTSEL0		0x186
601 #define	MSR_EVNTSEL1		0x187
602 #define	MSR_THERM_CONTROL	0x19a
603 #define	MSR_THERM_INTERRUPT	0x19b
604 #define	MSR_THERM_STATUS	0x19c
605 #define	MSR_IA32_MISC_ENABLE	0x1a0
606 #define	MSR_IA32_TEMPERATURE_TARGET	0x1a2
607 #define	MSR_TURBO_RATIO_LIMIT	0x1ad
608 #define	MSR_TURBO_RATIO_LIMIT1	0x1ae
609 #define	MSR_IA32_ENERGY_PERF_BIAS	0x1b0
610 #define	MSR_IA32_PKG_THERM_STATUS	0x1b1
611 #define	MSR_IA32_PKG_THERM_INTERRUPT	0x1b2
612 #define	MSR_DEBUGCTLMSR		0x1d9
613 #define	MSR_LASTBRANCHFROMIP	0x1db
614 #define	MSR_LASTBRANCHTOIP	0x1dc
615 #define	MSR_LASTINTFROMIP	0x1dd
616 #define	MSR_LASTINTTOIP		0x1de
617 #define	MSR_ROB_CR_BKUPTMPDR6	0x1e0
618 #define	MSR_MTRRVarBase		0x200
619 #define	MSR_MTRR64kBase		0x250
620 #define	MSR_MTRR16kBase		0x258
621 #define	MSR_MTRR4kBase		0x268
622 #define	MSR_PAT			0x277
623 #define	MSR_MC0_CTL2		0x280
624 #define	MSR_MTRRdefType		0x2ff
625 #define	MSR_MC0_CTL		0x400
626 #define	MSR_MC0_STATUS		0x401
627 #define	MSR_MC0_ADDR		0x402
628 #define	MSR_MC0_MISC		0x403
629 #define	MSR_MC1_CTL		0x404
630 #define	MSR_MC1_STATUS		0x405
631 #define	MSR_MC1_ADDR		0x406
632 #define	MSR_MC1_MISC		0x407
633 #define	MSR_MC2_CTL		0x408
634 #define	MSR_MC2_STATUS		0x409
635 #define	MSR_MC2_ADDR		0x40a
636 #define	MSR_MC2_MISC		0x40b
637 #define	MSR_MC3_CTL		0x40c
638 #define	MSR_MC3_STATUS		0x40d
639 #define	MSR_MC3_ADDR		0x40e
640 #define	MSR_MC3_MISC		0x40f
641 #define	MSR_MC4_CTL		0x410
642 #define	MSR_MC4_STATUS		0x411
643 #define	MSR_MC4_ADDR		0x412
644 #define	MSR_MC4_MISC		0x413
645 #define	MSR_MCG_EXT_CTL		0x4d0
646 #define	MSR_RAPL_POWER_UNIT	0x606
647 #define	MSR_PKG_ENERGY_STATUS	0x611
648 #define	MSR_DRAM_ENERGY_STATUS	0x619
649 #define	MSR_PP0_ENERGY_STATUS	0x639
650 #define	MSR_PP1_ENERGY_STATUS	0x641
651 #define	MSR_PPERF		0x64e
652 #define	MSR_TSC_DEADLINE	0x6e0	/* Writes are not serializing */
653 #define	MSR_IA32_PM_ENABLE	0x770
654 #define	MSR_IA32_HWP_CAPABILITIES	0x771
655 #define	MSR_IA32_HWP_REQUEST_PKG	0x772
656 #define	MSR_IA32_HWP_INTERRUPT		0x773
657 #define	MSR_IA32_HWP_REQUEST	0x774
658 #define	MSR_IA32_HWP_STATUS	0x777
659 
660 /*
661  * VMX MSRs
662  */
663 #define	MSR_VMX_BASIC		0x480
664 #define	MSR_VMX_PINBASED_CTLS	0x481
665 #define	MSR_VMX_PROCBASED_CTLS	0x482
666 #define	MSR_VMX_EXIT_CTLS	0x483
667 #define	MSR_VMX_ENTRY_CTLS	0x484
668 #define	MSR_VMX_CR0_FIXED0	0x486
669 #define	MSR_VMX_CR0_FIXED1	0x487
670 #define	MSR_VMX_CR4_FIXED0	0x488
671 #define	MSR_VMX_CR4_FIXED1	0x489
672 #define	MSR_VMX_PROCBASED_CTLS2	0x48b
673 #define	MSR_VMX_EPT_VPID_CAP	0x48c
674 #define	MSR_VMX_TRUE_PINBASED_CTLS	0x48d
675 #define	MSR_VMX_TRUE_PROCBASED_CTLS	0x48e
676 #define	MSR_VMX_TRUE_EXIT_CTLS	0x48f
677 #define	MSR_VMX_TRUE_ENTRY_CTLS	0x490
678 
679 /*
680  * X2APIC MSRs.
681  * Writes are not serializing.
682  */
683 #define	MSR_APIC_000		0x800
684 #define	MSR_APIC_ID		0x802
685 #define	MSR_APIC_VERSION	0x803
686 #define	MSR_APIC_TPR		0x808
687 #define	MSR_APIC_EOI		0x80b
688 #define	MSR_APIC_LDR		0x80d
689 #define	MSR_APIC_SVR		0x80f
690 #define	MSR_APIC_ISR0		0x810
691 #define	MSR_APIC_ISR1		0x811
692 #define	MSR_APIC_ISR2		0x812
693 #define	MSR_APIC_ISR3		0x813
694 #define	MSR_APIC_ISR4		0x814
695 #define	MSR_APIC_ISR5		0x815
696 #define	MSR_APIC_ISR6		0x816
697 #define	MSR_APIC_ISR7		0x817
698 #define	MSR_APIC_TMR0		0x818
699 #define	MSR_APIC_IRR0		0x820
700 #define	MSR_APIC_ESR		0x828
701 #define	MSR_APIC_LVT_CMCI	0x82F
702 #define	MSR_APIC_ICR		0x830
703 #define	MSR_APIC_LVT_TIMER	0x832
704 #define	MSR_APIC_LVT_THERMAL	0x833
705 #define	MSR_APIC_LVT_PCINT	0x834
706 #define	MSR_APIC_LVT_LINT0	0x835
707 #define	MSR_APIC_LVT_LINT1	0x836
708 #define	MSR_APIC_LVT_ERROR	0x837
709 #define	MSR_APIC_ICR_TIMER	0x838
710 #define	MSR_APIC_CCR_TIMER	0x839
711 #define	MSR_APIC_DCR_TIMER	0x83e
712 #define	MSR_APIC_SELF_IPI	0x83f
713 
714 #define	MSR_IA32_XSS		0xda0
715 
716 /*
717  * Intel Processor Trace (PT) MSRs.
718  */
719 #define	MSR_IA32_RTIT_OUTPUT_BASE	0x560	/* Trace Output Base Register (R/W) */
720 #define	MSR_IA32_RTIT_OUTPUT_MASK_PTRS	0x561	/* Trace Output Mask Pointers Register (R/W) */
721 #define	MSR_IA32_RTIT_CTL		0x570	/* Trace Control Register (R/W) */
722 #define	 RTIT_CTL_TRACEEN	(1 << 0)
723 #define	 RTIT_CTL_CYCEN		(1 << 1)
724 #define	 RTIT_CTL_OS		(1 << 2)
725 #define	 RTIT_CTL_USER		(1 << 3)
726 #define	 RTIT_CTL_PWREVTEN	(1 << 4)
727 #define	 RTIT_CTL_FUPONPTW	(1 << 5)
728 #define	 RTIT_CTL_FABRICEN	(1 << 6)
729 #define	 RTIT_CTL_CR3FILTER	(1 << 7)
730 #define	 RTIT_CTL_TOPA		(1 << 8)
731 #define	 RTIT_CTL_MTCEN		(1 << 9)
732 #define	 RTIT_CTL_TSCEN		(1 << 10)
733 #define	 RTIT_CTL_DISRETC	(1 << 11)
734 #define	 RTIT_CTL_PTWEN		(1 << 12)
735 #define	 RTIT_CTL_BRANCHEN	(1 << 13)
736 #define	 RTIT_CTL_MTC_FREQ_S	14
737 #define	 RTIT_CTL_MTC_FREQ(n)	((n) << RTIT_CTL_MTC_FREQ_S)
738 #define	 RTIT_CTL_MTC_FREQ_M	(0xf << RTIT_CTL_MTC_FREQ_S)
739 #define	 RTIT_CTL_CYC_THRESH_S	19
740 #define	 RTIT_CTL_CYC_THRESH_M	(0xf << RTIT_CTL_CYC_THRESH_S)
741 #define	 RTIT_CTL_PSB_FREQ_S	24
742 #define	 RTIT_CTL_PSB_FREQ_M	(0xf << RTIT_CTL_PSB_FREQ_S)
743 #define	 RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4)
744 #define	 RTIT_CTL_ADDR0_CFG_S	32
745 #define	 RTIT_CTL_ADDR0_CFG_M	(0xfULL << RTIT_CTL_ADDR0_CFG_S)
746 #define	 RTIT_CTL_ADDR1_CFG_S	36
747 #define	 RTIT_CTL_ADDR1_CFG_M	(0xfULL << RTIT_CTL_ADDR1_CFG_S)
748 #define	 RTIT_CTL_ADDR2_CFG_S	40
749 #define	 RTIT_CTL_ADDR2_CFG_M	(0xfULL << RTIT_CTL_ADDR2_CFG_S)
750 #define	 RTIT_CTL_ADDR3_CFG_S	44
751 #define	 RTIT_CTL_ADDR3_CFG_M	(0xfULL << RTIT_CTL_ADDR3_CFG_S)
752 #define	MSR_IA32_RTIT_STATUS		0x571	/* Tracing Status Register (R/W) */
753 #define	 RTIT_STATUS_FILTEREN	(1 << 0)
754 #define	 RTIT_STATUS_CONTEXTEN	(1 << 1)
755 #define	 RTIT_STATUS_TRIGGEREN	(1 << 2)
756 #define	 RTIT_STATUS_ERROR	(1 << 4)
757 #define	 RTIT_STATUS_STOPPED	(1 << 5)
758 #define	 RTIT_STATUS_PACKETBYTECNT_S	32
759 #define	 RTIT_STATUS_PACKETBYTECNT_M	(0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S)
760 #define	MSR_IA32_RTIT_CR3_MATCH		0x572	/* Trace Filter CR3 Match Register (R/W) */
761 #define	MSR_IA32_RTIT_ADDR_A(n)		(0x580 + (n) * 2)
762 #define	MSR_IA32_RTIT_ADDR_B(n)		(0x581 + (n) * 2)
763 #define	MSR_IA32_RTIT_ADDR0_A		0x580	/* Region 0 Start Address (R/W) */
764 #define	MSR_IA32_RTIT_ADDR0_B		0x581	/* Region 0 End Address (R/W) */
765 #define	MSR_IA32_RTIT_ADDR1_A		0x582	/* Region 1 Start Address (R/W) */
766 #define	MSR_IA32_RTIT_ADDR1_B		0x583	/* Region 1 End Address (R/W) */
767 #define	MSR_IA32_RTIT_ADDR2_A		0x584	/* Region 2 Start Address (R/W) */
768 #define	MSR_IA32_RTIT_ADDR2_B		0x585	/* Region 2 End Address (R/W) */
769 #define	MSR_IA32_RTIT_ADDR3_A		0x586	/* Region 3 Start Address (R/W) */
770 #define	MSR_IA32_RTIT_ADDR3_B		0x587	/* Region 3 End Address (R/W) */
771 
772 /* Intel Processor Trace Table of Physical Addresses (ToPA). */
773 #define	TOPA_SIZE_S	6
774 #define	TOPA_SIZE_M	(0xf << TOPA_SIZE_S)
775 #define	TOPA_SIZE_4K	(0 << TOPA_SIZE_S)
776 #define	TOPA_SIZE_8K	(1 << TOPA_SIZE_S)
777 #define	TOPA_SIZE_16K	(2 << TOPA_SIZE_S)
778 #define	TOPA_SIZE_32K	(3 << TOPA_SIZE_S)
779 #define	TOPA_SIZE_64K	(4 << TOPA_SIZE_S)
780 #define	TOPA_SIZE_128K	(5 << TOPA_SIZE_S)
781 #define	TOPA_SIZE_256K	(6 << TOPA_SIZE_S)
782 #define	TOPA_SIZE_512K	(7 << TOPA_SIZE_S)
783 #define	TOPA_SIZE_1M	(8 << TOPA_SIZE_S)
784 #define	TOPA_SIZE_2M	(9 << TOPA_SIZE_S)
785 #define	TOPA_SIZE_4M	(10 << TOPA_SIZE_S)
786 #define	TOPA_SIZE_8M	(11 << TOPA_SIZE_S)
787 #define	TOPA_SIZE_16M	(12 << TOPA_SIZE_S)
788 #define	TOPA_SIZE_32M	(13 << TOPA_SIZE_S)
789 #define	TOPA_SIZE_64M	(14 << TOPA_SIZE_S)
790 #define	TOPA_SIZE_128M	(15 << TOPA_SIZE_S)
791 #define	TOPA_STOP	(1 << 4)
792 #define	TOPA_INT	(1 << 2)
793 #define	TOPA_END	(1 << 0)
794 
795 /*
796  *  Intel Hardware Feedback Interface / Thread Director MSRs
797  */
798 #define	MSR_IA32_HW_FEEDBACK_PTR		0x17d0
799 #define	MSR_IA32_HW_FEEDBACK_CONFIG		0x17d1
800 #define	MSR_IA32_THREAD_FEEDBACK_CHAR		0x17d2
801 #define	MSR_IA32_HW_FEEDBACK_THREAD_CONFIG	0x17d4
802 
803 /*
804  * Constants related to MSR's.
805  */
806 #define	APICBASE_RESERVED	0x000002ff
807 #define	APICBASE_BSP		0x00000100
808 #define	APICBASE_X2APIC		0x00000400
809 #define	APICBASE_ENABLED	0x00000800
810 #define	APICBASE_ADDRESS	0xfffff000
811 
812 /* MSR_IA32_FEATURE_CONTROL related */
813 #define	IA32_FEATURE_CONTROL_LOCK	0x01	/* lock bit */
814 #define	IA32_FEATURE_CONTROL_SMX_EN	0x02	/* enable VMX inside SMX */
815 #define	IA32_FEATURE_CONTROL_VMX_EN	0x04	/* enable VMX outside SMX */
816 #define	IA32_FEATURE_CONTROL_LMCE_EN	0x100000 /* enable local MCE */
817 
818 /* MSR IA32_MISC_ENABLE */
819 #define	IA32_MISC_EN_FASTSTR	0x0000000000000001ULL
820 #define	IA32_MISC_EN_ATCCE	0x0000000000000008ULL
821 #define	IA32_MISC_EN_PERFMON	0x0000000000000080ULL
822 #define	IA32_MISC_EN_PEBSU	0x0000000000001000ULL
823 #define	IA32_MISC_EN_ESSTE	0x0000000000010000ULL
824 #define	IA32_MISC_EN_MONE	0x0000000000040000ULL
825 #define	IA32_MISC_EN_LIMCPUID	0x0000000000400000ULL
826 #define	IA32_MISC_EN_xTPRD	0x0000000000800000ULL
827 #define	IA32_MISC_EN_XDD	0x0000000400000000ULL
828 
829 /*
830  * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
831  * document 336996-001 Speculative Execution Side Channel Mitigations.
832  *
833  * AMD uses the same MSRs and bit definitions, as described in 111006-B
834  * "Indirect Branch Control Extension" and 124441 "Speculative Store Bypass
835  * Disable."
836  */
837 /* MSR IA32_SPEC_CTRL */
838 #define	IA32_SPEC_CTRL_IBRS	0x00000001
839 #define	IA32_SPEC_CTRL_STIBP	0x00000002
840 #define	IA32_SPEC_CTRL_SSBD	0x00000004
841 
842 /* MSR IA32_PRED_CMD */
843 #define	IA32_PRED_CMD_IBPB_BARRIER	0x0000000000000001ULL
844 
845 /* MSR IA32_FLUSH_CMD */
846 #define	IA32_FLUSH_CMD_L1D	0x00000001
847 
848 /* MSR IA32_MCU_OPT_CTRL */
849 #define	IA32_RNGDS_MITG_DIS	0x00000001
850 
851 /* MSR IA32_HWP_CAPABILITIES */
852 #define	IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x)	(((x) >> 0) & 0xff)
853 #define	IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x)	(((x) >> 8) & 0xff)
854 #define	IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x)	(((x) >> 16) & 0xff)
855 #define	IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x)	(((x) >> 24) & 0xff)
856 
857 /* MSR IA32_HWP_REQUEST */
858 #define	IA32_HWP_REQUEST_MINIMUM_VALID			(1ULL << 63)
859 #define	IA32_HWP_REQUEST_MAXIMUM_VALID			(1ULL << 62)
860 #define	IA32_HWP_REQUEST_DESIRED_VALID			(1ULL << 61)
861 #define	IA32_HWP_REQUEST_EPP_VALID 			(1ULL << 60)
862 #define	IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID		(1ULL << 59)
863 #define	IA32_HWP_REQUEST_PACKAGE_CONTROL		(1ULL << 42)
864 #define	IA32_HWP_ACTIVITY_WINDOW			(0x3ffULL << 32)
865 #define	IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE	(0xffULL << 24)
866 #define	IA32_HWP_DESIRED_PERFORMANCE			(0xffULL << 16)
867 #define	IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE		(0xffULL << 8)
868 #define	IA32_HWP_MINIMUM_PERFORMANCE			(0xffULL << 0)
869 
870 /* MSR IA32_ENERGY_PERF_BIAS */
871 #define	IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK		(0xfULL << 0)
872 
873 /* MSR IA32_HW_FEEDBACK_PTR */
874 #define	IA32_HW_FEEDBACK_PTR_ENABLE			(0x1ULL << 0)
875 
876 /* MSR IA32_HW_FEEDBACK_CONFIG */
877 #define	IA32_HW_FEEDBACK_CONFIG_EN_HFI			(0x1ULL << 0)
878 #define	IA32_HW_FEEDBACK_CONFIG_EN_THDIR		(0x1ULL << 1)
879 
880 /* MSR IA32_PKG_THERM_STATUS */
881 #define	IA32_PKG_THERM_STATUS_HFI_UPDATED		(0x1ULL << 26)
882 
883 /* MSR IA32_PKG_THERM_INTERRUPT */
884 #define	IA32_PKG_THERM_INTERRUPT_HFI_ENABLE		(0x1ULL << 25)
885 
886 /*
887  * PAT modes.
888  */
889 #define	PAT_UNCACHEABLE		0x00
890 #define	PAT_WRITE_COMBINING	0x01
891 #define	PAT_WRITE_THROUGH	0x04
892 #define	PAT_WRITE_PROTECTED	0x05
893 #define	PAT_WRITE_BACK		0x06
894 #define	PAT_UNCACHED		0x07
895 #define	PAT_VALUE(i, m)		((long long)(m) << (8 * (i)))
896 #define	PAT_MASK(i)		PAT_VALUE(i, 0xff)
897 
898 /*
899  * Constants related to MTRRs
900  */
901 #define	MTRR_UNCACHEABLE	0x00
902 #define	MTRR_WRITE_COMBINING	0x01
903 #define	MTRR_WRITE_THROUGH	0x04
904 #define	MTRR_WRITE_PROTECTED	0x05
905 #define	MTRR_WRITE_BACK		0x06
906 #define	MTRR_N64K		8	/* numbers of fixed-size entries */
907 #define	MTRR_N16K		16
908 #define	MTRR_N4K		64
909 #define	MTRR_CAP_WC		0x0000000000000400
910 #define	MTRR_CAP_FIXED		0x0000000000000100
911 #define	MTRR_CAP_VCNT		0x00000000000000ff
912 #define	MTRR_DEF_ENABLE		0x0000000000000800
913 #define	MTRR_DEF_FIXED_ENABLE	0x0000000000000400
914 #define	MTRR_DEF_TYPE		0x00000000000000ff
915 #define	MTRR_PHYSBASE_PHYSBASE	0x000ffffffffff000
916 #define	MTRR_PHYSBASE_TYPE	0x00000000000000ff
917 #define	MTRR_PHYSMASK_PHYSMASK	0x000ffffffffff000
918 #define	MTRR_PHYSMASK_VALID	0x0000000000000800
919 
920 /*
921  * Cyrix configuration registers, accessible as IO ports.
922  */
923 #define	CCR0			0xc0	/* Configuration control register 0 */
924 #define	CCR0_NC0		0x01	/* First 64K of each 1M memory region is
925 								   non-cacheable */
926 #define	CCR0_NC1		0x02	/* 640K-1M region is non-cacheable */
927 #define	CCR0_A20M		0x04	/* Enables A20M# input pin */
928 #define	CCR0_KEN		0x08	/* Enables KEN# input pin */
929 #define	CCR0_FLUSH		0x10	/* Enables FLUSH# input pin */
930 #define	CCR0_BARB		0x20	/* Flushes internal cache when entering hold
931 								   state */
932 #define	CCR0_CO			0x40	/* Cache org: 1=direct mapped, 0=2x set
933 								   assoc */
934 #define	CCR0_SUSPEND	0x80	/* Enables SUSP# and SUSPA# pins */
935 
936 #define	CCR1			0xc1	/* Configuration control register 1 */
937 #define	CCR1_RPL		0x01	/* Enables RPLSET and RPLVAL# pins */
938 #define	CCR1_SMI		0x02	/* Enables SMM pins */
939 #define	CCR1_SMAC		0x04	/* System management memory access */
940 #define	CCR1_MMAC		0x08	/* Main memory access */
941 #define	CCR1_NO_LOCK	0x10	/* Negate LOCK# */
942 #define	CCR1_SM3		0x80	/* SMM address space address region 3 */
943 
944 #define	CCR2			0xc2
945 #define	CCR2_WB			0x02	/* Enables WB cache interface pins */
946 #define	CCR2_SADS		0x02	/* Slow ADS */
947 #define	CCR2_LOCK_NW	0x04	/* LOCK NW Bit */
948 #define	CCR2_SUSP_HLT	0x08	/* Suspend on HALT */
949 #define	CCR2_WT1		0x10	/* WT region 1 */
950 #define	CCR2_WPR1		0x10	/* Write-protect region 1 */
951 #define	CCR2_BARB		0x20	/* Flushes write-back cache when entering
952 								   hold state. */
953 #define	CCR2_BWRT		0x40	/* Enables burst write cycles */
954 #define	CCR2_USE_SUSP	0x80	/* Enables suspend pins */
955 
956 #define	CCR3			0xc3
957 #define	CCR3_SMILOCK	0x01	/* SMM register lock */
958 #define	CCR3_NMI		0x02	/* Enables NMI during SMM */
959 #define	CCR3_LINBRST	0x04	/* Linear address burst cycles */
960 #define	CCR3_SMMMODE	0x08	/* SMM Mode */
961 #define	CCR3_MAPEN0		0x10	/* Enables Map0 */
962 #define	CCR3_MAPEN1		0x20	/* Enables Map1 */
963 #define	CCR3_MAPEN2		0x40	/* Enables Map2 */
964 #define	CCR3_MAPEN3		0x80	/* Enables Map3 */
965 
966 #define	CCR4			0xe8
967 #define	CCR4_IOMASK		0x07
968 #define	CCR4_MEM		0x08	/* Enables memory bypassing */
969 #define	CCR4_DTE		0x10	/* Enables directory table entry cache */
970 #define	CCR4_FASTFPE	0x20	/* Fast FPU exception */
971 #define	CCR4_CPUID		0x80	/* Enables CPUID instruction */
972 
973 #define	CCR5			0xe9
974 #define	CCR5_WT_ALLOC	0x01	/* Write-through allocate */
975 #define	CCR5_SLOP		0x02	/* LOOP instruction slowed down */
976 #define	CCR5_LBR1		0x10	/* Local bus region 1 */
977 #define	CCR5_ARREN		0x20	/* Enables ARR region */
978 
979 #define	CCR6			0xea
980 
981 #define	CCR7			0xeb
982 
983 /* Performance Control Register (5x86 only). */
984 #define	PCR0			0x20
985 #define	PCR0_RSTK		0x01	/* Enables return stack */
986 #define	PCR0_BTB		0x02	/* Enables branch target buffer */
987 #define	PCR0_LOOP		0x04	/* Enables loop */
988 #define	PCR0_AIS		0x08	/* Enables all instructions stalled to
989 								   serialize pipe. */
990 #define	PCR0_MLR		0x10	/* Enables reordering of misaligned loads */
991 #define	PCR0_BTBRT		0x40	/* Enables BTB test register. */
992 #define	PCR0_LSSER		0x80	/* Disable reorder */
993 
994 /* Device Identification Registers */
995 #define	DIR0			0xfe
996 #define	DIR1			0xff
997 
998 /*
999  * Machine Check register constants.
1000  */
1001 #define	MCG_CAP_COUNT		0x000000ff
1002 #define	MCG_CAP_CTL_P		0x00000100
1003 #define	MCG_CAP_EXT_P		0x00000200
1004 #define	MCG_CAP_CMCI_P		0x00000400
1005 #define	MCG_CAP_TES_P		0x00000800
1006 #define	MCG_CAP_EXT_CNT		0x00ff0000
1007 #define	MCG_CAP_SER_P		0x01000000
1008 #define	MCG_CAP_EMC_P		0x02000000
1009 #define	MCG_CAP_ELOG_P		0x04000000
1010 #define	MCG_CAP_LMCE_P		0x08000000
1011 #define	MCG_STATUS_RIPV		0x00000001
1012 #define	MCG_STATUS_EIPV		0x00000002
1013 #define	MCG_STATUS_MCIP		0x00000004
1014 #define	MCG_STATUS_LMCS		0x00000008		/* if MCG_CAP_LMCE_P */
1015 #define	MCG_CTL_ENABLE		0xffffffffffffffff
1016 #define	MCG_CTL_DISABLE		0x0000000000000000
1017 #define	MSR_MC_CTL(x)		(MSR_MC0_CTL + (x) * 4)
1018 #define	MSR_MC_STATUS(x)	(MSR_MC0_STATUS + (x) * 4)
1019 #define	MSR_MC_ADDR(x)		(MSR_MC0_ADDR + (x) * 4)
1020 #define	MSR_MC_MISC(x)		(MSR_MC0_MISC + (x) * 4)
1021 #define	MSR_MC_CTL2(x)		(MSR_MC0_CTL2 + (x))	/* If MCG_CAP_CMCI_P */
1022 #define	MC_STATUS_MCA_ERROR	0x000000000000ffff
1023 #define	MC_STATUS_MODEL_ERROR	0x00000000ffff0000
1024 #define	MC_STATUS_OTHER_INFO	0x01ffffff00000000
1025 #define	MC_STATUS_COR_COUNT	0x001fffc000000000	/* If MCG_CAP_CMCI_P */
1026 #define	MC_STATUS_TES_STATUS	0x0060000000000000	/* If MCG_CAP_TES_P */
1027 #define	MC_STATUS_AR		0x0080000000000000	/* If MCG_CAP_TES_P */
1028 #define	MC_STATUS_S		0x0100000000000000	/* If MCG_CAP_TES_P */
1029 #define	MC_STATUS_PCC		0x0200000000000000
1030 #define	MC_STATUS_ADDRV		0x0400000000000000
1031 #define	MC_STATUS_MISCV		0x0800000000000000
1032 #define	MC_STATUS_EN		0x1000000000000000
1033 #define	MC_STATUS_UC		0x2000000000000000
1034 #define	MC_STATUS_OVER		0x4000000000000000
1035 #define	MC_STATUS_VAL		0x8000000000000000
1036 #define	MC_MISC_RA_LSB		0x000000000000003f	/* If MCG_CAP_SER_P */
1037 #define	MC_MISC_ADDRESS_MODE	0x00000000000001c0	/* If MCG_CAP_SER_P */
1038 #define	MC_MISC_PCIE_RID	0x00000000ffff0000
1039 #define	MC_MISC_PCIE_FUNC	0x0000000000070000
1040 #define	MC_MISC_PCIE_SLOT	0x0000000000f80000
1041 #define	MC_MISC_PCIE_BUS	0x00000000ff000000
1042 #define	MC_MISC_PCIE_SEG	0x000000ff00000000
1043 #define	MC_CTL2_THRESHOLD	0x0000000000007fff
1044 #define	MC_CTL2_CMCI_EN		0x0000000040000000
1045 #define	MC_AMDNB_BANK		4
1046 #define	MC_MISC_AMD_VAL		0x8000000000000000	/* Counter presence valid */
1047 #define	MC_MISC_AMD_CNTP	0x4000000000000000	/* Counter present */
1048 #define	MC_MISC_AMD_LOCK	0x2000000000000000	/* Register locked */
1049 #define	MC_MISC_AMD_INTP	0x1000000000000000	/* Int. type can generate interrupts */
1050 #define	MC_MISC_AMD_LVT_MASK	0x00f0000000000000	/* Extended LVT offset */
1051 #define	MC_MISC_AMD_LVT_SHIFT	52
1052 #define	MC_MISC_AMD_CNTEN	0x0008000000000000	/* Counter enabled */
1053 #define	MC_MISC_AMD_INT_MASK	0x0006000000000000	/* Interrupt type */
1054 #define	MC_MISC_AMD_INT_LVT	0x0002000000000000	/* Interrupt via Extended LVT */
1055 #define	MC_MISC_AMD_INT_SMI	0x0004000000000000	/* SMI */
1056 #define	MC_MISC_AMD_OVERFLOW	0x0001000000000000	/* Counter overflow */
1057 #define	MC_MISC_AMD_CNT_MASK	0x00000fff00000000	/* Counter value */
1058 #define	MC_MISC_AMD_CNT_SHIFT	32
1059 #define	MC_MISC_AMD_CNT_MAX	0xfff
1060 #define	MC_MISC_AMD_PTR_MASK	0x00000000ff000000	/* Pointer to additional registers */
1061 #define	MC_MISC_AMD_PTR_SHIFT	24
1062 
1063 /* AMD Scalable MCA */
1064 #define MSR_SMCA_MC0_CTL          0xc0002000
1065 #define MSR_SMCA_MC0_STATUS       0xc0002001
1066 #define MSR_SMCA_MC0_ADDR         0xc0002002
1067 #define MSR_SMCA_MC0_MISC0        0xc0002003
1068 #define MSR_SMCA_MC_CTL(x)       (MSR_SMCA_MC0_CTL + 0x10 * (x))
1069 #define MSR_SMCA_MC_STATUS(x)    (MSR_SMCA_MC0_STATUS + 0x10 * (x))
1070 #define MSR_SMCA_MC_ADDR(x)      (MSR_SMCA_MC0_ADDR + 0x10 * (x))
1071 #define MSR_SMCA_MC_MISC(x)      (MSR_SMCA_MC0_MISC0 + 0x10 * (x))
1072 
1073 /*
1074  * The following four 3-byte registers control the non-cacheable regions.
1075  * These registers must be written as three separate bytes.
1076  *
1077  * NCRx+0: A31-A24 of starting address
1078  * NCRx+1: A23-A16 of starting address
1079  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
1080  *
1081  * The non-cacheable region's starting address must be aligned to the
1082  * size indicated by the NCR_SIZE_xx field.
1083  */
1084 #define	NCR1	0xc4
1085 #define	NCR2	0xc7
1086 #define	NCR3	0xca
1087 #define	NCR4	0xcd
1088 
1089 #define	NCR_SIZE_0K	0
1090 #define	NCR_SIZE_4K	1
1091 #define	NCR_SIZE_8K	2
1092 #define	NCR_SIZE_16K	3
1093 #define	NCR_SIZE_32K	4
1094 #define	NCR_SIZE_64K	5
1095 #define	NCR_SIZE_128K	6
1096 #define	NCR_SIZE_256K	7
1097 #define	NCR_SIZE_512K	8
1098 #define	NCR_SIZE_1M	9
1099 #define	NCR_SIZE_2M	10
1100 #define	NCR_SIZE_4M	11
1101 #define	NCR_SIZE_8M	12
1102 #define	NCR_SIZE_16M	13
1103 #define	NCR_SIZE_32M	14
1104 #define	NCR_SIZE_4G	15
1105 
1106 /*
1107  * The address region registers are used to specify the location and
1108  * size for the eight address regions.
1109  *
1110  * ARRx + 0: A31-A24 of start address
1111  * ARRx + 1: A23-A16 of start address
1112  * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
1113  */
1114 #define	ARR0	0xc4
1115 #define	ARR1	0xc7
1116 #define	ARR2	0xca
1117 #define	ARR3	0xcd
1118 #define	ARR4	0xd0
1119 #define	ARR5	0xd3
1120 #define	ARR6	0xd6
1121 #define	ARR7	0xd9
1122 
1123 #define	ARR_SIZE_0K		0
1124 #define	ARR_SIZE_4K		1
1125 #define	ARR_SIZE_8K		2
1126 #define	ARR_SIZE_16K	3
1127 #define	ARR_SIZE_32K	4
1128 #define	ARR_SIZE_64K	5
1129 #define	ARR_SIZE_128K	6
1130 #define	ARR_SIZE_256K	7
1131 #define	ARR_SIZE_512K	8
1132 #define	ARR_SIZE_1M		9
1133 #define	ARR_SIZE_2M		10
1134 #define	ARR_SIZE_4M		11
1135 #define	ARR_SIZE_8M		12
1136 #define	ARR_SIZE_16M	13
1137 #define	ARR_SIZE_32M	14
1138 #define	ARR_SIZE_4G		15
1139 
1140 /*
1141  * The region control registers specify the attributes associated with
1142  * the ARRx address regions.
1143  */
1144 #define	RCR0	0xdc
1145 #define	RCR1	0xdd
1146 #define	RCR2	0xde
1147 #define	RCR3	0xdf
1148 #define	RCR4	0xe0
1149 #define	RCR5	0xe1
1150 #define	RCR6	0xe2
1151 #define	RCR7	0xe3
1152 
1153 #define	RCR_RCD	0x01	/* Disables caching for ARRx (x = 0-6). */
1154 #define	RCR_RCE	0x01	/* Enables caching for ARR7. */
1155 #define	RCR_WWO	0x02	/* Weak write ordering. */
1156 #define	RCR_WL	0x04	/* Weak locking. */
1157 #define	RCR_WG	0x08	/* Write gathering. */
1158 #define	RCR_WT	0x10	/* Write-through. */
1159 #define	RCR_NLB	0x20	/* LBA# pin is not asserted. */
1160 
1161 /* AMD Write Allocate Top-Of-Memory and Control Register */
1162 #define	AMD_WT_ALLOC_TME	0x40000	/* top-of-memory enable */
1163 #define	AMD_WT_ALLOC_PRE	0x20000	/* programmable range enable */
1164 #define	AMD_WT_ALLOC_FRE	0x10000	/* fixed (A0000-FFFFF) range enable */
1165 
1166 /* AMD64 MSR's */
1167 #define	MSR_EFER	0xc0000080	/* extended features */
1168 #define	MSR_STAR	0xc0000081	/* legacy mode SYSCALL target/cs/ss */
1169 #define	MSR_LSTAR	0xc0000082	/* long mode SYSCALL target rip */
1170 #define	MSR_CSTAR	0xc0000083	/* compat mode SYSCALL target rip */
1171 #define	MSR_SF_MASK	0xc0000084	/* syscall flags mask */
1172 #define	MSR_FSBASE	0xc0000100	/* base address of the %fs "segment" */
1173 #define	MSR_GSBASE	0xc0000101	/* base address of the %gs "segment" */
1174 #define	MSR_KGSBASE	0xc0000102	/* base address of the kernel %gs */
1175 #define	MSR_TSC_AUX	0xc0000103
1176 #define	MSR_PERFEVSEL0	0xc0010000
1177 #define	MSR_PERFEVSEL1	0xc0010001
1178 #define	MSR_PERFEVSEL2	0xc0010002
1179 #define	MSR_PERFEVSEL3	0xc0010003
1180 #define	MSR_K7_PERFCTR0	0xc0010004
1181 #define	MSR_K7_PERFCTR1	0xc0010005
1182 #define	MSR_K7_PERFCTR2	0xc0010006
1183 #define	MSR_K7_PERFCTR3	0xc0010007
1184 #define	MSR_SYSCFG	0xc0010010
1185 #define	MSR_HWCR	0xc0010015
1186 #define	MSR_IORRBASE0	0xc0010016
1187 #define	MSR_IORRMASK0	0xc0010017
1188 #define	MSR_IORRBASE1	0xc0010018
1189 #define	MSR_IORRMASK1	0xc0010019
1190 #define	MSR_TOP_MEM	0xc001001a	/* boundary for ram below 4G */
1191 #define	MSR_TOP_MEM2	0xc001001d	/* boundary for ram above 4G */
1192 #define	MSR_NB_CFG1	0xc001001f	/* NB configuration 1 */
1193 #define	MSR_K8_UCODE_UPDATE 0xc0010020	/* update microcode */
1194 #define	MSR_MC0_CTL_MASK 0xc0010044
1195 #define	MSR_AMDK8_IPM	0xc0010055
1196 #define	MSR_P_STATE_LIMIT 0xc0010061	/* P-state Current Limit Register */
1197 #define	MSR_P_STATE_CONTROL 0xc0010062	/* P-state Control Register */
1198 #define	MSR_P_STATE_STATUS 0xc0010063	/* P-state Status Register */
1199 #define	MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
1200 #define	MSR_SMM_ADDR	0xc0010112	/* SMM TSEG base address */
1201 #define	MSR_SMM_MASK	0xc0010113	/* SMM TSEG address mask */
1202 #define	MSR_VM_CR	0xc0010114	/* SVM: feature control */
1203 #define	MSR_VM_HSAVE_PA 0xc0010117	/* SVM: host save area address */
1204 #define	MSR_AMD_CPUID07	0xc0011002	/* CPUID 07 %ebx override */
1205 #define	MSR_EXTFEATURES	0xc0011005	/* Extended CPUID Features override */
1206 #define	MSR_LS_CFG	0xc0011020
1207 #define	MSR_IC_CFG	0xc0011021	/* Instruction Cache Configuration */
1208 #define	MSR_DE_CFG	0xc0011029	/* Decode Configuration */
1209 
1210 /* MSR_AMDK8_IPM */
1211 #define	AMDK8_SMIONCMPHALT	(1ULL << 27)
1212 #define	AMDK8_C1EONCMPHALT	(1ULL << 28)
1213 
1214 /* MSR_VM_CR related */
1215 #define	VM_CR_SVMDIS		0x10	/* SVM: disabled by BIOS */
1216 
1217 /* MSR_DE_CFG */
1218 #define DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT	0x1
1219 #define DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT		0x2000
1220 #define DE_CFG_ZEN2_FP_BACKUP_FIX_BIT			0x200
1221 
1222 /* VIA ACE crypto featureset: for via_feature_rng */
1223 #define	VIA_HAS_RNG		1	/* cpu has RNG */
1224 
1225 /* VIA ACE crypto featureset: for via_feature_xcrypt */
1226 #define	VIA_HAS_AES		1	/* cpu has AES */
1227 #define	VIA_HAS_SHA		2	/* cpu has SHA1 & SHA256 */
1228 #define	VIA_HAS_MM		4	/* cpu has RSA instructions */
1229 #define	VIA_HAS_AESCTR		8	/* cpu has AES-CTR instructions */
1230 
1231 /* Centaur Extended Feature flags */
1232 #define	VIA_CPUID_HAS_RNG	0x000004
1233 #define	VIA_CPUID_DO_RNG	0x000008
1234 #define	VIA_CPUID_HAS_ACE	0x000040
1235 #define	VIA_CPUID_DO_ACE	0x000080
1236 #define	VIA_CPUID_HAS_ACE2	0x000100
1237 #define	VIA_CPUID_DO_ACE2	0x000200
1238 #define	VIA_CPUID_HAS_PHE	0x000400
1239 #define	VIA_CPUID_DO_PHE	0x000800
1240 #define	VIA_CPUID_HAS_PMM	0x001000
1241 #define	VIA_CPUID_DO_PMM	0x002000
1242 
1243 /* VIA ACE xcrypt-* instruction context control options */
1244 #define	VIA_CRYPT_CWLO_ROUND_M		0x0000000f
1245 #define	VIA_CRYPT_CWLO_ALG_M		0x00000070
1246 #define	VIA_CRYPT_CWLO_ALG_AES		0x00000000
1247 #define	VIA_CRYPT_CWLO_KEYGEN_M		0x00000080
1248 #define	VIA_CRYPT_CWLO_KEYGEN_HW	0x00000000
1249 #define	VIA_CRYPT_CWLO_KEYGEN_SW	0x00000080
1250 #define	VIA_CRYPT_CWLO_NORMAL		0x00000000
1251 #define	VIA_CRYPT_CWLO_INTERMEDIATE	0x00000100
1252 #define	VIA_CRYPT_CWLO_ENCRYPT		0x00000000
1253 #define	VIA_CRYPT_CWLO_DECRYPT		0x00000200
1254 #define	VIA_CRYPT_CWLO_KEY128		0x0000000a	/* 128bit, 10 rds */
1255 #define	VIA_CRYPT_CWLO_KEY192		0x0000040c	/* 192bit, 12 rds */
1256 #define	VIA_CRYPT_CWLO_KEY256		0x0000080e	/* 256bit, 15 rds */
1257 
1258 #endif /* !_MACHINE_SPECIALREG_H_ */
1259