1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_SPECIALREG_H_ 34 #define _MACHINE_SPECIALREG_H_ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 #define CR3_PCID_SAVE 0x8000000000000000 56 57 /* 58 * Bits in PPro special registers 59 */ 60 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 61 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 62 #define CR4_TSD 0x00000004 /* Time stamp disable */ 63 #define CR4_DE 0x00000008 /* Debugging extensions */ 64 #define CR4_PSE 0x00000010 /* Page size extensions */ 65 #define CR4_PAE 0x00000020 /* Physical address extension */ 66 #define CR4_MCE 0x00000040 /* Machine check enable */ 67 #define CR4_PGE 0x00000080 /* Page global enable */ 68 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 69 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 70 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 71 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 72 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 73 #define CR4_PCIDE 0x00020000 /* Enable Context ID */ 74 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 75 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 76 77 /* 78 * Bits in AMD64 special registers. EFER is 64 bits wide. 79 */ 80 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 81 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 82 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 83 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 84 85 /* 86 * Intel Extended Features registers 87 */ 88 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 89 90 #define XFEATURE_ENABLED_X87 0x00000001 91 #define XFEATURE_ENABLED_SSE 0x00000002 92 #define XFEATURE_ENABLED_AVX 0x00000004 93 94 #define XFEATURE_AVX \ 95 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 96 97 /* 98 * CPUID instruction features register 99 */ 100 #define CPUID_FPU 0x00000001 101 #define CPUID_VME 0x00000002 102 #define CPUID_DE 0x00000004 103 #define CPUID_PSE 0x00000008 104 #define CPUID_TSC 0x00000010 105 #define CPUID_MSR 0x00000020 106 #define CPUID_PAE 0x00000040 107 #define CPUID_MCE 0x00000080 108 #define CPUID_CX8 0x00000100 109 #define CPUID_APIC 0x00000200 110 #define CPUID_B10 0x00000400 111 #define CPUID_SEP 0x00000800 112 #define CPUID_MTRR 0x00001000 113 #define CPUID_PGE 0x00002000 114 #define CPUID_MCA 0x00004000 115 #define CPUID_CMOV 0x00008000 116 #define CPUID_PAT 0x00010000 117 #define CPUID_PSE36 0x00020000 118 #define CPUID_PSN 0x00040000 119 #define CPUID_CLFSH 0x00080000 120 #define CPUID_B20 0x00100000 121 #define CPUID_DS 0x00200000 122 #define CPUID_ACPI 0x00400000 123 #define CPUID_MMX 0x00800000 124 #define CPUID_FXSR 0x01000000 125 #define CPUID_SSE 0x02000000 126 #define CPUID_XMM 0x02000000 127 #define CPUID_SSE2 0x04000000 128 #define CPUID_SS 0x08000000 129 #define CPUID_HTT 0x10000000 130 #define CPUID_TM 0x20000000 131 #define CPUID_IA64 0x40000000 132 #define CPUID_PBE 0x80000000 133 134 #define CPUID2_SSE3 0x00000001 135 #define CPUID2_PCLMULQDQ 0x00000002 136 #define CPUID2_DTES64 0x00000004 137 #define CPUID2_MON 0x00000008 138 #define CPUID2_DS_CPL 0x00000010 139 #define CPUID2_VMX 0x00000020 140 #define CPUID2_SMX 0x00000040 141 #define CPUID2_EST 0x00000080 142 #define CPUID2_TM2 0x00000100 143 #define CPUID2_SSSE3 0x00000200 144 #define CPUID2_CNXTID 0x00000400 145 #define CPUID2_FMA 0x00001000 146 #define CPUID2_CX16 0x00002000 147 #define CPUID2_XTPR 0x00004000 148 #define CPUID2_PDCM 0x00008000 149 #define CPUID2_PCID 0x00020000 150 #define CPUID2_DCA 0x00040000 151 #define CPUID2_SSE41 0x00080000 152 #define CPUID2_SSE42 0x00100000 153 #define CPUID2_X2APIC 0x00200000 154 #define CPUID2_MOVBE 0x00400000 155 #define CPUID2_POPCNT 0x00800000 156 #define CPUID2_TSCDLT 0x01000000 157 #define CPUID2_AESNI 0x02000000 158 #define CPUID2_XSAVE 0x04000000 159 #define CPUID2_OSXSAVE 0x08000000 160 #define CPUID2_AVX 0x10000000 161 #define CPUID2_F16C 0x20000000 162 #define CPUID2_RDRAND 0x40000000 163 #define CPUID2_HV 0x80000000 164 165 /* 166 * Important bits in the Thermal and Power Management flags 167 * CPUID.6 EAX and ECX. 168 */ 169 #define CPUTPM1_SENSOR 0x00000001 170 #define CPUTPM1_TURBO 0x00000002 171 #define CPUTPM1_ARAT 0x00000004 172 #define CPUTPM2_EFFREQ 0x00000001 173 174 /* 175 * Important bits in the AMD extended cpuid flags 176 */ 177 #define AMDID_SYSCALL 0x00000800 178 #define AMDID_MP 0x00080000 179 #define AMDID_NX 0x00100000 180 #define AMDID_EXT_MMX 0x00400000 181 #define AMDID_FFXSR 0x01000000 182 #define AMDID_PAGE1GB 0x04000000 183 #define AMDID_RDTSCP 0x08000000 184 #define AMDID_LM 0x20000000 185 #define AMDID_EXT_3DNOW 0x40000000 186 #define AMDID_3DNOW 0x80000000 187 188 #define AMDID2_LAHF 0x00000001 189 #define AMDID2_CMP 0x00000002 190 #define AMDID2_SVM 0x00000004 191 #define AMDID2_EXT_APIC 0x00000008 192 #define AMDID2_CR8 0x00000010 193 #define AMDID2_ABM 0x00000020 194 #define AMDID2_SSE4A 0x00000040 195 #define AMDID2_MAS 0x00000080 196 #define AMDID2_PREFETCH 0x00000100 197 #define AMDID2_OSVW 0x00000200 198 #define AMDID2_IBS 0x00000400 199 #define AMDID2_XOP 0x00000800 200 #define AMDID2_SKINIT 0x00001000 201 #define AMDID2_WDT 0x00002000 202 #define AMDID2_LWP 0x00008000 203 #define AMDID2_FMA4 0x00010000 204 #define AMDID2_NODE_ID 0x00080000 205 #define AMDID2_TBM 0x00200000 206 #define AMDID2_TOPOLOGY 0x00400000 207 208 /* 209 * CPUID instruction 1 eax info 210 */ 211 #define CPUID_STEPPING 0x0000000f 212 #define CPUID_MODEL 0x000000f0 213 #define CPUID_FAMILY 0x00000f00 214 #define CPUID_EXT_MODEL 0x000f0000 215 #define CPUID_EXT_FAMILY 0x0ff00000 216 #ifdef __i386__ 217 #define CPUID_TO_MODEL(id) \ 218 ((((id) & CPUID_MODEL) >> 4) | \ 219 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 220 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 221 #define CPUID_TO_FAMILY(id) \ 222 ((((id) & CPUID_FAMILY) >> 8) + \ 223 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 224 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 225 #else 226 #define CPUID_TO_MODEL(id) \ 227 ((((id) & CPUID_MODEL) >> 4) | \ 228 (((id) & CPUID_EXT_MODEL) >> 12)) 229 #define CPUID_TO_FAMILY(id) \ 230 ((((id) & CPUID_FAMILY) >> 8) + \ 231 (((id) & CPUID_EXT_FAMILY) >> 20)) 232 #endif 233 234 /* 235 * CPUID instruction 1 ebx info 236 */ 237 #define CPUID_BRAND_INDEX 0x000000ff 238 #define CPUID_CLFUSH_SIZE 0x0000ff00 239 #define CPUID_HTT_CORES 0x00ff0000 240 #define CPUID_LOCAL_APIC_ID 0xff000000 241 242 /* 243 * CPUID instruction 6 ecx info 244 */ 245 #define CPUID_PERF_STAT 0x00000001 246 #define CPUID_PERF_BIAS 0x00000008 247 248 /* 249 * CPUID instruction 0xb ebx info. 250 */ 251 #define CPUID_TYPE_INVAL 0 252 #define CPUID_TYPE_SMT 1 253 #define CPUID_TYPE_CORE 2 254 255 /* 256 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 257 */ 258 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001 259 260 /* 261 * AMD extended function 8000_0007h edx info 262 */ 263 #define AMDPM_TS 0x00000001 264 #define AMDPM_FID 0x00000002 265 #define AMDPM_VID 0x00000004 266 #define AMDPM_TTP 0x00000008 267 #define AMDPM_TM 0x00000010 268 #define AMDPM_STC 0x00000020 269 #define AMDPM_100MHZ_STEPS 0x00000040 270 #define AMDPM_HW_PSTATE 0x00000080 271 #define AMDPM_TSC_INVARIANT 0x00000100 272 #define AMDPM_CPB 0x00000200 273 274 /* 275 * AMD extended function 8000_0008h ecx info 276 */ 277 #define AMDID_CMP_CORES 0x000000ff 278 #define AMDID_COREID_SIZE 0x0000f000 279 #define AMDID_COREID_SIZE_SHIFT 12 280 281 /* 282 * Structured Extended Features 283 */ 284 #define CPUID_STDEXT_FSGSBASE 0x00000001 285 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 286 #define CPUID_STDEXT_BMI1 0x00000008 287 #define CPUID_STDEXT_HLE 0x00000010 288 #define CPUID_STDEXT_AVX2 0x00000020 289 #define CPUID_STDEXT_SMEP 0x00000080 290 #define CPUID_STDEXT_BMI2 0x00000100 291 #define CPUID_STDEXT_ENH_MOVSB 0x00000200 292 #define CPUID_STDEXT_RTM 0x00000800 293 #define CPUID_STDEXT_INVPCID 0x00000400 294 #define CPUID_STDEXT_RDSEED 0x00040000 295 #define CPUID_STDEXT_ADX 0x00080000 296 #define CPUID_STDEXT_SMAP 0x00100000 297 298 /* 299 * CPUID manufacturers identifiers 300 */ 301 #define AMD_VENDOR_ID "AuthenticAMD" 302 #define CENTAUR_VENDOR_ID "CentaurHauls" 303 #define CYRIX_VENDOR_ID "CyrixInstead" 304 #define INTEL_VENDOR_ID "GenuineIntel" 305 #define NEXGEN_VENDOR_ID "NexGenDriven" 306 #define NSC_VENDOR_ID "Geode by NSC" 307 #define RISE_VENDOR_ID "RiseRiseRise" 308 #define SIS_VENDOR_ID "SiS SiS SiS " 309 #define TRANSMETA_VENDOR_ID "GenuineTMx86" 310 #define UMC_VENDOR_ID "UMC UMC UMC " 311 312 /* 313 * Model-specific registers for the i386 family 314 */ 315 #define MSR_P5_MC_ADDR 0x000 316 #define MSR_P5_MC_TYPE 0x001 317 #define MSR_TSC 0x010 318 #define MSR_P5_CESR 0x011 319 #define MSR_P5_CTR0 0x012 320 #define MSR_P5_CTR1 0x013 321 #define MSR_IA32_PLATFORM_ID 0x017 322 #define MSR_APICBASE 0x01b 323 #define MSR_EBL_CR_POWERON 0x02a 324 #define MSR_TEST_CTL 0x033 325 #define MSR_IA32_FEATURE_CONTROL 0x03a 326 #define MSR_BIOS_UPDT_TRIG 0x079 327 #define MSR_BBL_CR_D0 0x088 328 #define MSR_BBL_CR_D1 0x089 329 #define MSR_BBL_CR_D2 0x08a 330 #define MSR_BIOS_SIGN 0x08b 331 #define MSR_PERFCTR0 0x0c1 332 #define MSR_PERFCTR1 0x0c2 333 #define MSR_MPERF 0x0e7 334 #define MSR_APERF 0x0e8 335 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 336 #define MSR_MTRRcap 0x0fe 337 #define MSR_BBL_CR_ADDR 0x116 338 #define MSR_BBL_CR_DECC 0x118 339 #define MSR_BBL_CR_CTL 0x119 340 #define MSR_BBL_CR_TRIG 0x11a 341 #define MSR_BBL_CR_BUSY 0x11b 342 #define MSR_BBL_CR_CTL3 0x11e 343 #define MSR_SYSENTER_CS_MSR 0x174 344 #define MSR_SYSENTER_ESP_MSR 0x175 345 #define MSR_SYSENTER_EIP_MSR 0x176 346 #define MSR_MCG_CAP 0x179 347 #define MSR_MCG_STATUS 0x17a 348 #define MSR_MCG_CTL 0x17b 349 #define MSR_EVNTSEL0 0x186 350 #define MSR_EVNTSEL1 0x187 351 #define MSR_THERM_CONTROL 0x19a 352 #define MSR_THERM_INTERRUPT 0x19b 353 #define MSR_THERM_STATUS 0x19c 354 #define MSR_IA32_MISC_ENABLE 0x1a0 355 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 356 #define MSR_DEBUGCTLMSR 0x1d9 357 #define MSR_LASTBRANCHFROMIP 0x1db 358 #define MSR_LASTBRANCHTOIP 0x1dc 359 #define MSR_LASTINTFROMIP 0x1dd 360 #define MSR_LASTINTTOIP 0x1de 361 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 362 #define MSR_MTRRVarBase 0x200 363 #define MSR_MTRR64kBase 0x250 364 #define MSR_MTRR16kBase 0x258 365 #define MSR_MTRR4kBase 0x268 366 #define MSR_PAT 0x277 367 #define MSR_MC0_CTL2 0x280 368 #define MSR_MTRRdefType 0x2ff 369 #define MSR_MC0_CTL 0x400 370 #define MSR_MC0_STATUS 0x401 371 #define MSR_MC0_ADDR 0x402 372 #define MSR_MC0_MISC 0x403 373 #define MSR_MC1_CTL 0x404 374 #define MSR_MC1_STATUS 0x405 375 #define MSR_MC1_ADDR 0x406 376 #define MSR_MC1_MISC 0x407 377 #define MSR_MC2_CTL 0x408 378 #define MSR_MC2_STATUS 0x409 379 #define MSR_MC2_ADDR 0x40a 380 #define MSR_MC2_MISC 0x40b 381 #define MSR_MC3_CTL 0x40c 382 #define MSR_MC3_STATUS 0x40d 383 #define MSR_MC3_ADDR 0x40e 384 #define MSR_MC3_MISC 0x40f 385 #define MSR_MC4_CTL 0x410 386 #define MSR_MC4_STATUS 0x411 387 #define MSR_MC4_ADDR 0x412 388 #define MSR_MC4_MISC 0x413 389 390 /* 391 * X2APIC MSRs 392 */ 393 #define MSR_APIC_ID 0x802 394 #define MSR_APIC_VERSION 0x803 395 #define MSR_APIC_TPR 0x808 396 #define MSR_APIC_EOI 0x80b 397 #define MSR_APIC_LDR 0x80d 398 #define MSR_APIC_SVR 0x80f 399 #define MSR_APIC_ISR0 0x810 400 #define MSR_APIC_ISR1 0x811 401 #define MSR_APIC_ISR2 0x812 402 #define MSR_APIC_ISR3 0x813 403 #define MSR_APIC_ISR4 0x814 404 #define MSR_APIC_ISR5 0x815 405 #define MSR_APIC_ISR6 0x816 406 #define MSR_APIC_ISR7 0x817 407 #define MSR_APIC_TMR0 0x818 408 #define MSR_APIC_IRR0 0x820 409 #define MSR_APIC_ESR 0x828 410 #define MSR_APIC_LVT_CMCI 0x82F 411 #define MSR_APIC_ICR 0x830 412 #define MSR_APIC_LVT_TIMER 0x832 413 #define MSR_APIC_LVT_THERMAL 0x833 414 #define MSR_APIC_LVT_PCINT 0x834 415 #define MSR_APIC_LVT_LINT0 0x835 416 #define MSR_APIC_LVT_LINT1 0x836 417 #define MSR_APIC_LVT_ERROR 0x837 418 #define MSR_APIC_ICR_TIMER 0x838 419 #define MSR_APIC_CCR_TIMER 0x839 420 #define MSR_APIC_DCR_TIMER 0x83e 421 #define MSR_APIC_SELF_IPI 0x83f 422 423 /* 424 * Constants related to MSR's. 425 */ 426 #define APICBASE_RESERVED 0x000002ff 427 #define APICBASE_BSP 0x00000100 428 #define APICBASE_X2APIC 0x00000400 429 #define APICBASE_ENABLED 0x00000800 430 #define APICBASE_ADDRESS 0xfffff000 431 432 /* MSR_IA32_FEATURE_CONTROL related */ 433 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 434 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 435 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 436 437 /* 438 * PAT modes. 439 */ 440 #define PAT_UNCACHEABLE 0x00 441 #define PAT_WRITE_COMBINING 0x01 442 #define PAT_WRITE_THROUGH 0x04 443 #define PAT_WRITE_PROTECTED 0x05 444 #define PAT_WRITE_BACK 0x06 445 #define PAT_UNCACHED 0x07 446 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 447 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 448 449 /* 450 * Constants related to MTRRs 451 */ 452 #define MTRR_UNCACHEABLE 0x00 453 #define MTRR_WRITE_COMBINING 0x01 454 #define MTRR_WRITE_THROUGH 0x04 455 #define MTRR_WRITE_PROTECTED 0x05 456 #define MTRR_WRITE_BACK 0x06 457 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 458 #define MTRR_N16K 16 459 #define MTRR_N4K 64 460 #define MTRR_CAP_WC 0x0000000000000400 461 #define MTRR_CAP_FIXED 0x0000000000000100 462 #define MTRR_CAP_VCNT 0x00000000000000ff 463 #define MTRR_DEF_ENABLE 0x0000000000000800 464 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 465 #define MTRR_DEF_TYPE 0x00000000000000ff 466 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 467 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 468 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 469 #define MTRR_PHYSMASK_VALID 0x0000000000000800 470 471 /* 472 * Cyrix configuration registers, accessible as IO ports. 473 */ 474 #define CCR0 0xc0 /* Configuration control register 0 */ 475 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 476 non-cacheable */ 477 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 478 #define CCR0_A20M 0x04 /* Enables A20M# input pin */ 479 #define CCR0_KEN 0x08 /* Enables KEN# input pin */ 480 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 481 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 482 state */ 483 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 484 assoc */ 485 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 486 487 #define CCR1 0xc1 /* Configuration control register 1 */ 488 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 489 #define CCR1_SMI 0x02 /* Enables SMM pins */ 490 #define CCR1_SMAC 0x04 /* System management memory access */ 491 #define CCR1_MMAC 0x08 /* Main memory access */ 492 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 493 #define CCR1_SM3 0x80 /* SMM address space address region 3 */ 494 495 #define CCR2 0xc2 496 #define CCR2_WB 0x02 /* Enables WB cache interface pins */ 497 #define CCR2_SADS 0x02 /* Slow ADS */ 498 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 499 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 500 #define CCR2_WT1 0x10 /* WT region 1 */ 501 #define CCR2_WPR1 0x10 /* Write-protect region 1 */ 502 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering 503 hold state. */ 504 #define CCR2_BWRT 0x40 /* Enables burst write cycles */ 505 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 506 507 #define CCR3 0xc3 508 #define CCR3_SMILOCK 0x01 /* SMM register lock */ 509 #define CCR3_NMI 0x02 /* Enables NMI during SMM */ 510 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 511 #define CCR3_SMMMODE 0x08 /* SMM Mode */ 512 #define CCR3_MAPEN0 0x10 /* Enables Map0 */ 513 #define CCR3_MAPEN1 0x20 /* Enables Map1 */ 514 #define CCR3_MAPEN2 0x40 /* Enables Map2 */ 515 #define CCR3_MAPEN3 0x80 /* Enables Map3 */ 516 517 #define CCR4 0xe8 518 #define CCR4_IOMASK 0x07 519 #define CCR4_MEM 0x08 /* Enables momory bypassing */ 520 #define CCR4_DTE 0x10 /* Enables directory table entry cache */ 521 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 522 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 523 524 #define CCR5 0xe9 525 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 526 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 527 #define CCR5_LBR1 0x10 /* Local bus region 1 */ 528 #define CCR5_ARREN 0x20 /* Enables ARR region */ 529 530 #define CCR6 0xea 531 532 #define CCR7 0xeb 533 534 /* Performance Control Register (5x86 only). */ 535 #define PCR0 0x20 536 #define PCR0_RSTK 0x01 /* Enables return stack */ 537 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 538 #define PCR0_LOOP 0x04 /* Enables loop */ 539 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 540 serialize pipe. */ 541 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 542 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 543 #define PCR0_LSSER 0x80 /* Disable reorder */ 544 545 /* Device Identification Registers */ 546 #define DIR0 0xfe 547 #define DIR1 0xff 548 549 /* 550 * Machine Check register constants. 551 */ 552 #define MCG_CAP_COUNT 0x000000ff 553 #define MCG_CAP_CTL_P 0x00000100 554 #define MCG_CAP_EXT_P 0x00000200 555 #define MCG_CAP_CMCI_P 0x00000400 556 #define MCG_CAP_TES_P 0x00000800 557 #define MCG_CAP_EXT_CNT 0x00ff0000 558 #define MCG_CAP_SER_P 0x01000000 559 #define MCG_STATUS_RIPV 0x00000001 560 #define MCG_STATUS_EIPV 0x00000002 561 #define MCG_STATUS_MCIP 0x00000004 562 #define MCG_CTL_ENABLE 0xffffffffffffffff 563 #define MCG_CTL_DISABLE 0x0000000000000000 564 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 565 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 566 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 567 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 568 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 569 #define MC_STATUS_MCA_ERROR 0x000000000000ffff 570 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 571 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 572 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 573 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 574 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 575 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 576 #define MC_STATUS_PCC 0x0200000000000000 577 #define MC_STATUS_ADDRV 0x0400000000000000 578 #define MC_STATUS_MISCV 0x0800000000000000 579 #define MC_STATUS_EN 0x1000000000000000 580 #define MC_STATUS_UC 0x2000000000000000 581 #define MC_STATUS_OVER 0x4000000000000000 582 #define MC_STATUS_VAL 0x8000000000000000 583 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 584 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 585 #define MC_CTL2_THRESHOLD 0x0000000000007fff 586 #define MC_CTL2_CMCI_EN 0x0000000040000000 587 588 /* 589 * The following four 3-byte registers control the non-cacheable regions. 590 * These registers must be written as three separate bytes. 591 * 592 * NCRx+0: A31-A24 of starting address 593 * NCRx+1: A23-A16 of starting address 594 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 595 * 596 * The non-cacheable region's starting address must be aligned to the 597 * size indicated by the NCR_SIZE_xx field. 598 */ 599 #define NCR1 0xc4 600 #define NCR2 0xc7 601 #define NCR3 0xca 602 #define NCR4 0xcd 603 604 #define NCR_SIZE_0K 0 605 #define NCR_SIZE_4K 1 606 #define NCR_SIZE_8K 2 607 #define NCR_SIZE_16K 3 608 #define NCR_SIZE_32K 4 609 #define NCR_SIZE_64K 5 610 #define NCR_SIZE_128K 6 611 #define NCR_SIZE_256K 7 612 #define NCR_SIZE_512K 8 613 #define NCR_SIZE_1M 9 614 #define NCR_SIZE_2M 10 615 #define NCR_SIZE_4M 11 616 #define NCR_SIZE_8M 12 617 #define NCR_SIZE_16M 13 618 #define NCR_SIZE_32M 14 619 #define NCR_SIZE_4G 15 620 621 /* 622 * The address region registers are used to specify the location and 623 * size for the eight address regions. 624 * 625 * ARRx + 0: A31-A24 of start address 626 * ARRx + 1: A23-A16 of start address 627 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 628 */ 629 #define ARR0 0xc4 630 #define ARR1 0xc7 631 #define ARR2 0xca 632 #define ARR3 0xcd 633 #define ARR4 0xd0 634 #define ARR5 0xd3 635 #define ARR6 0xd6 636 #define ARR7 0xd9 637 638 #define ARR_SIZE_0K 0 639 #define ARR_SIZE_4K 1 640 #define ARR_SIZE_8K 2 641 #define ARR_SIZE_16K 3 642 #define ARR_SIZE_32K 4 643 #define ARR_SIZE_64K 5 644 #define ARR_SIZE_128K 6 645 #define ARR_SIZE_256K 7 646 #define ARR_SIZE_512K 8 647 #define ARR_SIZE_1M 9 648 #define ARR_SIZE_2M 10 649 #define ARR_SIZE_4M 11 650 #define ARR_SIZE_8M 12 651 #define ARR_SIZE_16M 13 652 #define ARR_SIZE_32M 14 653 #define ARR_SIZE_4G 15 654 655 /* 656 * The region control registers specify the attributes associated with 657 * the ARRx addres regions. 658 */ 659 #define RCR0 0xdc 660 #define RCR1 0xdd 661 #define RCR2 0xde 662 #define RCR3 0xdf 663 #define RCR4 0xe0 664 #define RCR5 0xe1 665 #define RCR6 0xe2 666 #define RCR7 0xe3 667 668 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 669 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 670 #define RCR_WWO 0x02 /* Weak write ordering. */ 671 #define RCR_WL 0x04 /* Weak locking. */ 672 #define RCR_WG 0x08 /* Write gathering. */ 673 #define RCR_WT 0x10 /* Write-through. */ 674 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 675 676 /* AMD Write Allocate Top-Of-Memory and Control Register */ 677 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 678 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 679 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 680 681 /* AMD64 MSR's */ 682 #define MSR_EFER 0xc0000080 /* extended features */ 683 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 684 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 685 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 686 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 687 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 688 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 689 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 690 #define MSR_PERFEVSEL0 0xc0010000 691 #define MSR_PERFEVSEL1 0xc0010001 692 #define MSR_PERFEVSEL2 0xc0010002 693 #define MSR_PERFEVSEL3 0xc0010003 694 #undef MSR_PERFCTR0 695 #undef MSR_PERFCTR1 696 #define MSR_PERFCTR0 0xc0010004 697 #define MSR_PERFCTR1 0xc0010005 698 #define MSR_PERFCTR2 0xc0010006 699 #define MSR_PERFCTR3 0xc0010007 700 #define MSR_SYSCFG 0xc0010010 701 #define MSR_HWCR 0xc0010015 702 #define MSR_IORRBASE0 0xc0010016 703 #define MSR_IORRMASK0 0xc0010017 704 #define MSR_IORRBASE1 0xc0010018 705 #define MSR_IORRMASK1 0xc0010019 706 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 707 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 708 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 709 #define MSR_MC0_CTL_MASK 0xc0010044 710 711 /* VIA ACE crypto featureset: for via_feature_rng */ 712 #define VIA_HAS_RNG 1 /* cpu has RNG */ 713 714 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 715 #define VIA_HAS_AES 1 /* cpu has AES */ 716 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 717 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 718 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 719 720 /* Centaur Extended Feature flags */ 721 #define VIA_CPUID_HAS_RNG 0x000004 722 #define VIA_CPUID_DO_RNG 0x000008 723 #define VIA_CPUID_HAS_ACE 0x000040 724 #define VIA_CPUID_DO_ACE 0x000080 725 #define VIA_CPUID_HAS_ACE2 0x000100 726 #define VIA_CPUID_DO_ACE2 0x000200 727 #define VIA_CPUID_HAS_PHE 0x000400 728 #define VIA_CPUID_DO_PHE 0x000800 729 #define VIA_CPUID_HAS_PMM 0x001000 730 #define VIA_CPUID_DO_PMM 0x002000 731 732 /* VIA ACE xcrypt-* instruction context control options */ 733 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 734 #define VIA_CRYPT_CWLO_ALG_M 0x00000070 735 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 736 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 737 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 738 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 739 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 740 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 741 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 742 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 743 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 744 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 745 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 746 747 #endif /* !_MACHINE_SPECIALREG_H_ */ 748