12c7879eaSTijl Coosemans /*- 251369649SPedro F. Giffuni * SPDX-License-Identifier: BSD-3-Clause 351369649SPedro F. Giffuni * 42c7879eaSTijl Coosemans * Copyright (c) 1991 The Regents of the University of California. 52c7879eaSTijl Coosemans * All rights reserved. 62c7879eaSTijl Coosemans * 72c7879eaSTijl Coosemans * Redistribution and use in source and binary forms, with or without 82c7879eaSTijl Coosemans * modification, are permitted provided that the following conditions 92c7879eaSTijl Coosemans * are met: 102c7879eaSTijl Coosemans * 1. Redistributions of source code must retain the above copyright 112c7879eaSTijl Coosemans * notice, this list of conditions and the following disclaimer. 122c7879eaSTijl Coosemans * 2. Redistributions in binary form must reproduce the above copyright 132c7879eaSTijl Coosemans * notice, this list of conditions and the following disclaimer in the 142c7879eaSTijl Coosemans * documentation and/or other materials provided with the distribution. 15fbbd9655SWarner Losh * 3. Neither the name of the University nor the names of its contributors 162c7879eaSTijl Coosemans * may be used to endorse or promote products derived from this software 172c7879eaSTijl Coosemans * without specific prior written permission. 182c7879eaSTijl Coosemans * 192c7879eaSTijl Coosemans * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 202c7879eaSTijl Coosemans * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 212c7879eaSTijl Coosemans * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 222c7879eaSTijl Coosemans * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 232c7879eaSTijl Coosemans * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 242c7879eaSTijl Coosemans * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 252c7879eaSTijl Coosemans * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 262c7879eaSTijl Coosemans * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 272c7879eaSTijl Coosemans * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 282c7879eaSTijl Coosemans * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 292c7879eaSTijl Coosemans * SUCH DAMAGE. 302c7879eaSTijl Coosemans */ 312c7879eaSTijl Coosemans 322c7879eaSTijl Coosemans #ifndef _MACHINE_SPECIALREG_H_ 332c7879eaSTijl Coosemans #define _MACHINE_SPECIALREG_H_ 342c7879eaSTijl Coosemans 352c7879eaSTijl Coosemans /* 362c7879eaSTijl Coosemans * Bits in 386 special registers: 372c7879eaSTijl Coosemans */ 382c7879eaSTijl Coosemans #define CR0_PE 0x00000001 /* Protected mode Enable */ 392c7879eaSTijl Coosemans #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 402c7879eaSTijl Coosemans #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 412c7879eaSTijl Coosemans #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 422c7879eaSTijl Coosemans #define CR0_PG 0x80000000 /* PaGing enable */ 432c7879eaSTijl Coosemans 442c7879eaSTijl Coosemans /* 452c7879eaSTijl Coosemans * Bits in 486 special registers: 462c7879eaSTijl Coosemans */ 472c7879eaSTijl Coosemans #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 482c7879eaSTijl Coosemans #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 492c7879eaSTijl Coosemans all modes) */ 502c7879eaSTijl Coosemans #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 512c7879eaSTijl Coosemans #define CR0_NW 0x20000000 /* Not Write-through */ 522c7879eaSTijl Coosemans #define CR0_CD 0x40000000 /* Cache Disable */ 532c7879eaSTijl Coosemans 542773649dSKonstantin Belousov #define CR3_PCID_SAVE 0x8000000000000000 55a546448bSKonstantin Belousov #define CR3_PCID_MASK 0xfff 562773649dSKonstantin Belousov 572c7879eaSTijl Coosemans /* 582c7879eaSTijl Coosemans * Bits in PPro special registers 592c7879eaSTijl Coosemans */ 602c7879eaSTijl Coosemans #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 612c7879eaSTijl Coosemans #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 622c7879eaSTijl Coosemans #define CR4_TSD 0x00000004 /* Time stamp disable */ 632c7879eaSTijl Coosemans #define CR4_DE 0x00000008 /* Debugging extensions */ 642c7879eaSTijl Coosemans #define CR4_PSE 0x00000010 /* Page size extensions */ 652c7879eaSTijl Coosemans #define CR4_PAE 0x00000020 /* Physical address extension */ 662c7879eaSTijl Coosemans #define CR4_MCE 0x00000040 /* Machine check enable */ 672c7879eaSTijl Coosemans #define CR4_PGE 0x00000080 /* Page global enable */ 682c7879eaSTijl Coosemans #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 692c7879eaSTijl Coosemans #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 702c7879eaSTijl Coosemans #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 71706bc29bSConrad Meyer #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */ 724ba405dcSKonstantin Belousov #define CR4_LA57 0x00001000 /* Enable 5-level paging */ 73bf70b875SNeel Natu #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 742773649dSKonstantin Belousov #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 752773649dSKonstantin Belousov #define CR4_PCIDE 0x00020000 /* Enable Context ID */ 762c7879eaSTijl Coosemans #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 772773649dSKonstantin Belousov #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 78da457ed9SKonstantin Belousov #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */ 795671e0d6SKonstantin Belousov #define CR4_PKE 0x00400000 /* Protection Keys Enable */ 802c7879eaSTijl Coosemans 812c7879eaSTijl Coosemans /* 822c7879eaSTijl Coosemans * Bits in AMD64 special registers. EFER is 64 bits wide. 832c7879eaSTijl Coosemans */ 842c7879eaSTijl Coosemans #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 852c7879eaSTijl Coosemans #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 862c7879eaSTijl Coosemans #define EFER_LMA 0x000000400 /* Long mode active (R) */ 872c7879eaSTijl Coosemans #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 88e011dc96SNeel Natu #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ 89712bd51aSNeel Natu #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ 90712bd51aSNeel Natu #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ 91712bd51aSNeel Natu #define EFER_TCE 0x000008000 /* Translation Cache Extension */ 92706bc29bSConrad Meyer #define EFER_MCOMMIT 0x00020000 /* Enable MCOMMIT (AMD) */ 932c7879eaSTijl Coosemans 942c7879eaSTijl Coosemans /* 952c7879eaSTijl Coosemans * Intel Extended Features registers 962c7879eaSTijl Coosemans */ 972c7879eaSTijl Coosemans #define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 982c7879eaSTijl Coosemans 992c7879eaSTijl Coosemans #define XFEATURE_ENABLED_X87 0x00000001 1002c7879eaSTijl Coosemans #define XFEATURE_ENABLED_SSE 0x00000002 101355d8a2fSJohn Baldwin #define XFEATURE_ENABLED_YMM_HI128 0x00000004 102355d8a2fSJohn Baldwin #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128 103355d8a2fSJohn Baldwin #define XFEATURE_ENABLED_BNDREGS 0x00000008 104355d8a2fSJohn Baldwin #define XFEATURE_ENABLED_BNDCSR 0x00000010 105355d8a2fSJohn Baldwin #define XFEATURE_ENABLED_OPMASK 0x00000020 106355d8a2fSJohn Baldwin #define XFEATURE_ENABLED_ZMM_HI256 0x00000040 107355d8a2fSJohn Baldwin #define XFEATURE_ENABLED_HI16_ZMM 0x00000080 10811989314SKonstantin Belousov #define XFEATURE_ENABLED_PKRU 0x00000200 10911989314SKonstantin Belousov #define XFEATURE_ENABLED_TILECONFIG 0x00020000 11011989314SKonstantin Belousov #define XFEATURE_ENABLED_TILEDATA 0x00040000 1112c7879eaSTijl Coosemans 1122c7879eaSTijl Coosemans #define XFEATURE_AVX \ 1132c7879eaSTijl Coosemans (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 114355d8a2fSJohn Baldwin #define XFEATURE_AVX512 \ 115355d8a2fSJohn Baldwin (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \ 116355d8a2fSJohn Baldwin XFEATURE_ENABLED_HI16_ZMM) 117355d8a2fSJohn Baldwin #define XFEATURE_MPX \ 118355d8a2fSJohn Baldwin (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR) 1192c7879eaSTijl Coosemans 1202c7879eaSTijl Coosemans /* 1212c7879eaSTijl Coosemans * CPUID instruction features register 1222c7879eaSTijl Coosemans */ 1232c7879eaSTijl Coosemans #define CPUID_FPU 0x00000001 1242c7879eaSTijl Coosemans #define CPUID_VME 0x00000002 1252c7879eaSTijl Coosemans #define CPUID_DE 0x00000004 1262c7879eaSTijl Coosemans #define CPUID_PSE 0x00000008 1272c7879eaSTijl Coosemans #define CPUID_TSC 0x00000010 1282c7879eaSTijl Coosemans #define CPUID_MSR 0x00000020 1292c7879eaSTijl Coosemans #define CPUID_PAE 0x00000040 1302c7879eaSTijl Coosemans #define CPUID_MCE 0x00000080 1312c7879eaSTijl Coosemans #define CPUID_CX8 0x00000100 1322c7879eaSTijl Coosemans #define CPUID_APIC 0x00000200 1332c7879eaSTijl Coosemans #define CPUID_B10 0x00000400 1342c7879eaSTijl Coosemans #define CPUID_SEP 0x00000800 1352c7879eaSTijl Coosemans #define CPUID_MTRR 0x00001000 1362c7879eaSTijl Coosemans #define CPUID_PGE 0x00002000 1372c7879eaSTijl Coosemans #define CPUID_MCA 0x00004000 1382c7879eaSTijl Coosemans #define CPUID_CMOV 0x00008000 1392c7879eaSTijl Coosemans #define CPUID_PAT 0x00010000 1402c7879eaSTijl Coosemans #define CPUID_PSE36 0x00020000 1412c7879eaSTijl Coosemans #define CPUID_PSN 0x00040000 1422c7879eaSTijl Coosemans #define CPUID_CLFSH 0x00080000 1432c7879eaSTijl Coosemans #define CPUID_B20 0x00100000 1442c7879eaSTijl Coosemans #define CPUID_DS 0x00200000 1452c7879eaSTijl Coosemans #define CPUID_ACPI 0x00400000 1462c7879eaSTijl Coosemans #define CPUID_MMX 0x00800000 1472c7879eaSTijl Coosemans #define CPUID_FXSR 0x01000000 1482c7879eaSTijl Coosemans #define CPUID_SSE 0x02000000 1492c7879eaSTijl Coosemans #define CPUID_XMM 0x02000000 1502c7879eaSTijl Coosemans #define CPUID_SSE2 0x04000000 1512c7879eaSTijl Coosemans #define CPUID_SS 0x08000000 1522c7879eaSTijl Coosemans #define CPUID_HTT 0x10000000 1532c7879eaSTijl Coosemans #define CPUID_TM 0x20000000 1542c7879eaSTijl Coosemans #define CPUID_IA64 0x40000000 1552c7879eaSTijl Coosemans #define CPUID_PBE 0x80000000 1562c7879eaSTijl Coosemans 1572c7879eaSTijl Coosemans #define CPUID2_SSE3 0x00000001 1582c7879eaSTijl Coosemans #define CPUID2_PCLMULQDQ 0x00000002 1592c7879eaSTijl Coosemans #define CPUID2_DTES64 0x00000004 1602c7879eaSTijl Coosemans #define CPUID2_MON 0x00000008 1612c7879eaSTijl Coosemans #define CPUID2_DS_CPL 0x00000010 1622c7879eaSTijl Coosemans #define CPUID2_VMX 0x00000020 1632c7879eaSTijl Coosemans #define CPUID2_SMX 0x00000040 1642c7879eaSTijl Coosemans #define CPUID2_EST 0x00000080 1652c7879eaSTijl Coosemans #define CPUID2_TM2 0x00000100 1662c7879eaSTijl Coosemans #define CPUID2_SSSE3 0x00000200 1672c7879eaSTijl Coosemans #define CPUID2_CNXTID 0x00000400 168e31b1dc8SSean Bruno #define CPUID2_SDBG 0x00000800 1692c7879eaSTijl Coosemans #define CPUID2_FMA 0x00001000 1702c7879eaSTijl Coosemans #define CPUID2_CX16 0x00002000 1712c7879eaSTijl Coosemans #define CPUID2_XTPR 0x00004000 1722c7879eaSTijl Coosemans #define CPUID2_PDCM 0x00008000 1732c7879eaSTijl Coosemans #define CPUID2_PCID 0x00020000 1742c7879eaSTijl Coosemans #define CPUID2_DCA 0x00040000 1752c7879eaSTijl Coosemans #define CPUID2_SSE41 0x00080000 1762c7879eaSTijl Coosemans #define CPUID2_SSE42 0x00100000 1772c7879eaSTijl Coosemans #define CPUID2_X2APIC 0x00200000 1782c7879eaSTijl Coosemans #define CPUID2_MOVBE 0x00400000 1792c7879eaSTijl Coosemans #define CPUID2_POPCNT 0x00800000 1802c7879eaSTijl Coosemans #define CPUID2_TSCDLT 0x01000000 1812c7879eaSTijl Coosemans #define CPUID2_AESNI 0x02000000 1822c7879eaSTijl Coosemans #define CPUID2_XSAVE 0x04000000 1832c7879eaSTijl Coosemans #define CPUID2_OSXSAVE 0x08000000 1842c7879eaSTijl Coosemans #define CPUID2_AVX 0x10000000 1852c7879eaSTijl Coosemans #define CPUID2_F16C 0x20000000 186bcd60681SJohn Baldwin #define CPUID2_RDRAND 0x40000000 1872c7879eaSTijl Coosemans #define CPUID2_HV 0x80000000 1882c7879eaSTijl Coosemans 1893b418d1bSRuslan Bukin /* Intel Processor Trace CPUID. */ 1903b418d1bSRuslan Bukin 1913b418d1bSRuslan Bukin /* Leaf 0 ebx. */ 1923b418d1bSRuslan Bukin #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */ 1933b418d1bSRuslan Bukin #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */ 1943b418d1bSRuslan Bukin #define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */ 1953b418d1bSRuslan Bukin #define CPUPT_MTC (1 << 3) /* MTC Supported */ 1963b418d1bSRuslan Bukin #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */ 1973b418d1bSRuslan Bukin #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */ 1983b418d1bSRuslan Bukin 1993b418d1bSRuslan Bukin /* Leaf 0 ecx. */ 2003b418d1bSRuslan Bukin #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */ 2013b418d1bSRuslan Bukin #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */ 2023b418d1bSRuslan Bukin #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */ 2033b418d1bSRuslan Bukin #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */ 2043b418d1bSRuslan Bukin #define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */ 2053b418d1bSRuslan Bukin 2063b418d1bSRuslan Bukin /* Leaf 1 eax. */ 2073b418d1bSRuslan Bukin #define CPUPT_NADDR_S 0 /* Number of Address Ranges */ 2083b418d1bSRuslan Bukin #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S) 2093b418d1bSRuslan Bukin #define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */ 2103b418d1bSRuslan Bukin #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S) 2113b418d1bSRuslan Bukin 2123b418d1bSRuslan Bukin /* Leaf 1 ebx. */ 2133b418d1bSRuslan Bukin #define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */ 2143b418d1bSRuslan Bukin #define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S) 2153b418d1bSRuslan Bukin #define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */ 2163b418d1bSRuslan Bukin #define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S) 2173b418d1bSRuslan Bukin 2182c7879eaSTijl Coosemans /* 2192c7879eaSTijl Coosemans * Important bits in the AMD extended cpuid flags 2202c7879eaSTijl Coosemans */ 2212c7879eaSTijl Coosemans #define AMDID_SYSCALL 0x00000800 2222c7879eaSTijl Coosemans #define AMDID_MP 0x00080000 2232c7879eaSTijl Coosemans #define AMDID_NX 0x00100000 2242c7879eaSTijl Coosemans #define AMDID_EXT_MMX 0x00400000 225712bd51aSNeel Natu #define AMDID_FFXSR 0x02000000 2262c7879eaSTijl Coosemans #define AMDID_PAGE1GB 0x04000000 2272c7879eaSTijl Coosemans #define AMDID_RDTSCP 0x08000000 2282c7879eaSTijl Coosemans #define AMDID_LM 0x20000000 2292c7879eaSTijl Coosemans #define AMDID_EXT_3DNOW 0x40000000 2302c7879eaSTijl Coosemans #define AMDID_3DNOW 0x80000000 2312c7879eaSTijl Coosemans 2322c7879eaSTijl Coosemans #define AMDID2_LAHF 0x00000001 2332c7879eaSTijl Coosemans #define AMDID2_CMP 0x00000002 2342c7879eaSTijl Coosemans #define AMDID2_SVM 0x00000004 2352c7879eaSTijl Coosemans #define AMDID2_EXT_APIC 0x00000008 2362c7879eaSTijl Coosemans #define AMDID2_CR8 0x00000010 2372c7879eaSTijl Coosemans #define AMDID2_ABM 0x00000020 2382c7879eaSTijl Coosemans #define AMDID2_SSE4A 0x00000040 2392c7879eaSTijl Coosemans #define AMDID2_MAS 0x00000080 2402c7879eaSTijl Coosemans #define AMDID2_PREFETCH 0x00000100 2412c7879eaSTijl Coosemans #define AMDID2_OSVW 0x00000200 2422c7879eaSTijl Coosemans #define AMDID2_IBS 0x00000400 2432c7879eaSTijl Coosemans #define AMDID2_XOP 0x00000800 2442c7879eaSTijl Coosemans #define AMDID2_SKINIT 0x00001000 2452c7879eaSTijl Coosemans #define AMDID2_WDT 0x00002000 2462c7879eaSTijl Coosemans #define AMDID2_LWP 0x00008000 2472c7879eaSTijl Coosemans #define AMDID2_FMA4 0x00010000 2486f8a44a5SKonstantin Belousov #define AMDID2_TCE 0x00020000 2492c7879eaSTijl Coosemans #define AMDID2_NODE_ID 0x00080000 2502c7879eaSTijl Coosemans #define AMDID2_TBM 0x00200000 2512c7879eaSTijl Coosemans #define AMDID2_TOPOLOGY 0x00400000 2526f8a44a5SKonstantin Belousov #define AMDID2_PCXC 0x00800000 2536f8a44a5SKonstantin Belousov #define AMDID2_PNXC 0x01000000 2546f8a44a5SKonstantin Belousov #define AMDID2_DBE 0x04000000 2556f8a44a5SKonstantin Belousov #define AMDID2_PTSC 0x08000000 2566f8a44a5SKonstantin Belousov #define AMDID2_PTSCEL2I 0x10000000 257264fae07SPeter Grehan #define AMDID2_MWAITX 0x20000000 2582c7879eaSTijl Coosemans 2592c7879eaSTijl Coosemans /* 2602c7879eaSTijl Coosemans * CPUID instruction 1 eax info 2612c7879eaSTijl Coosemans */ 2622c7879eaSTijl Coosemans #define CPUID_STEPPING 0x0000000f 2632c7879eaSTijl Coosemans #define CPUID_MODEL 0x000000f0 2642c7879eaSTijl Coosemans #define CPUID_FAMILY 0x00000f00 2652c7879eaSTijl Coosemans #define CPUID_EXT_MODEL 0x000f0000 2662c7879eaSTijl Coosemans #define CPUID_EXT_FAMILY 0x0ff00000 2672c7879eaSTijl Coosemans #ifdef __i386__ 2682c7879eaSTijl Coosemans #define CPUID_TO_MODEL(id) \ 2692c7879eaSTijl Coosemans ((((id) & CPUID_MODEL) >> 4) | \ 2702c7879eaSTijl Coosemans ((((id) & CPUID_FAMILY) >= 0x600) ? \ 2712c7879eaSTijl Coosemans (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 2722c7879eaSTijl Coosemans #define CPUID_TO_FAMILY(id) \ 2732c7879eaSTijl Coosemans ((((id) & CPUID_FAMILY) >> 8) + \ 2742c7879eaSTijl Coosemans ((((id) & CPUID_FAMILY) == 0xf00) ? \ 2752c7879eaSTijl Coosemans (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 2762c7879eaSTijl Coosemans #else 2772c7879eaSTijl Coosemans #define CPUID_TO_MODEL(id) \ 2782c7879eaSTijl Coosemans ((((id) & CPUID_MODEL) >> 4) | \ 2792c7879eaSTijl Coosemans (((id) & CPUID_EXT_MODEL) >> 12)) 2802c7879eaSTijl Coosemans #define CPUID_TO_FAMILY(id) \ 2812c7879eaSTijl Coosemans ((((id) & CPUID_FAMILY) >> 8) + \ 2822c7879eaSTijl Coosemans (((id) & CPUID_EXT_FAMILY) >> 20)) 2832c7879eaSTijl Coosemans #endif 284ef013ceeSRyan Moeller #define CPUID_TO_STEPPING(id) ((id) & CPUID_STEPPING) 2852c7879eaSTijl Coosemans 2862c7879eaSTijl Coosemans /* 2872c7879eaSTijl Coosemans * CPUID instruction 1 ebx info 2882c7879eaSTijl Coosemans */ 2892c7879eaSTijl Coosemans #define CPUID_BRAND_INDEX 0x000000ff 2902c7879eaSTijl Coosemans #define CPUID_CLFUSH_SIZE 0x0000ff00 2912c7879eaSTijl Coosemans #define CPUID_HTT_CORES 0x00ff0000 2922c7879eaSTijl Coosemans #define CPUID_LOCAL_APIC_ID 0xff000000 2932c7879eaSTijl Coosemans 2942c7879eaSTijl Coosemans /* 295a69e8d60SAndriy Gapon * CPUID instruction 5 info 296a69e8d60SAndriy Gapon */ 297a69e8d60SAndriy Gapon #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 298a69e8d60SAndriy Gapon #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 299a69e8d60SAndriy Gapon #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 300a69e8d60SAndriy Gapon #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 301a69e8d60SAndriy Gapon 302a69e8d60SAndriy Gapon /* 303a69e8d60SAndriy Gapon * MWAIT cpu power states. Lower 4 bits are sub-states. 304a69e8d60SAndriy Gapon */ 305a69e8d60SAndriy Gapon #define MWAIT_C0 0xf0 306a69e8d60SAndriy Gapon #define MWAIT_C1 0x00 307a69e8d60SAndriy Gapon #define MWAIT_C2 0x10 308a69e8d60SAndriy Gapon #define MWAIT_C3 0x20 309a69e8d60SAndriy Gapon #define MWAIT_C4 0x30 310a69e8d60SAndriy Gapon 311a69e8d60SAndriy Gapon /* 312a69e8d60SAndriy Gapon * MWAIT extensions. 313a69e8d60SAndriy Gapon */ 314a69e8d60SAndriy Gapon /* Interrupt breaks MWAIT even when masked. */ 315a69e8d60SAndriy Gapon #define MWAIT_INTRBREAK 0x00000001 316a69e8d60SAndriy Gapon 317a69e8d60SAndriy Gapon /* 318bb044eafSConrad Meyer * CPUID leaf 6: Thermal and Power management. 3192c7879eaSTijl Coosemans */ 320bb044eafSConrad Meyer /* Eax. */ 321bb044eafSConrad Meyer #define CPUTPM1_SENSOR 0x00000001 322bb044eafSConrad Meyer #define CPUTPM1_TURBO 0x00000002 323bb044eafSConrad Meyer #define CPUTPM1_ARAT 0x00000004 324bb044eafSConrad Meyer #define CPUTPM1_PLN 0x00000010 325bb044eafSConrad Meyer #define CPUTPM1_ECMD 0x00000020 326bb044eafSConrad Meyer #define CPUTPM1_PTM 0x00000040 327bb044eafSConrad Meyer #define CPUTPM1_HWP 0x00000080 328bb044eafSConrad Meyer #define CPUTPM1_HWP_NOTIFICATION 0x00000100 329bb044eafSConrad Meyer #define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200 330bb044eafSConrad Meyer #define CPUTPM1_HWP_PERF_PREF 0x00000400 331bb044eafSConrad Meyer #define CPUTPM1_HWP_PKG 0x00000800 332bb044eafSConrad Meyer #define CPUTPM1_HDC 0x00002000 333bb044eafSConrad Meyer #define CPUTPM1_TURBO30 0x00004000 334bb044eafSConrad Meyer #define CPUTPM1_HWP_CAPABILITIES 0x00008000 335bb044eafSConrad Meyer #define CPUTPM1_HWP_PECI_OVR 0x00010000 336bb044eafSConrad Meyer #define CPUTPM1_HWP_FLEXIBLE 0x00020000 337bb044eafSConrad Meyer #define CPUTPM1_HWP_FAST_MSR 0x00040000 338e60316d1SMark Johnston #define CPUTPM1_HW_FEEDBACK 0x00080000 339bb044eafSConrad Meyer #define CPUTPM1_HWP_IGN_IDLE 0x00100000 340e60316d1SMark Johnston #define CPUTPM1_THREAD_DIRECTOR 0x00800000 341bb044eafSConrad Meyer 342bb044eafSConrad Meyer /* Ebx. */ 343bb044eafSConrad Meyer #define CPUTPM_B_NSENSINTTHRESH 0x0000000f 344bb044eafSConrad Meyer 345bb044eafSConrad Meyer /* Ecx. */ 3462c7879eaSTijl Coosemans #define CPUID_PERF_STAT 0x00000001 3472c7879eaSTijl Coosemans #define CPUID_PERF_BIAS 0x00000008 348338d5396SKoine Yuusuke #define CPUID_PERF_TD_CLASSES 0x0000ff00 349338d5396SKoine Yuusuke 350338d5396SKoine Yuusuke /* Edx. */ 351338d5396SKoine Yuusuke #define CPUID_HF_PERFORMANCE 0x00000001 352338d5396SKoine Yuusuke #define CPUID_HF_EFFICIENCY 0x00000002 353338d5396SKoine Yuusuke #define CPUID_TD_CAPABLITIES 0x0000000f 354338d5396SKoine Yuusuke #define CPUID_TD_TBLPAGES 0x00000f00 3552c7879eaSTijl Coosemans 3562c7879eaSTijl Coosemans /* 3572c7879eaSTijl Coosemans * CPUID instruction 0xb ebx info. 3582c7879eaSTijl Coosemans */ 3592c7879eaSTijl Coosemans #define CPUID_TYPE_INVAL 0 3602c7879eaSTijl Coosemans #define CPUID_TYPE_SMT 1 3612c7879eaSTijl Coosemans #define CPUID_TYPE_CORE 2 3622c7879eaSTijl Coosemans 3632c7879eaSTijl Coosemans /* 364333d0c60SKonstantin Belousov * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 365333d0c60SKonstantin Belousov */ 366333d0c60SKonstantin Belousov #define CPUID_EXTSTATE_XSAVEOPT 0x00000001 367dc7c2b07SKonstantin Belousov #define CPUID_EXTSTATE_XSAVEC 0x00000002 368dc7c2b07SKonstantin Belousov #define CPUID_EXTSTATE_XINUSE 0x00000004 369dc7c2b07SKonstantin Belousov #define CPUID_EXTSTATE_XSAVES 0x00000008 370333d0c60SKonstantin Belousov 371333d0c60SKonstantin Belousov /* 372cd8c2581SConrad Meyer * AMD extended function 8000_0007h ebx info 373cd8c2581SConrad Meyer */ 374cd8c2581SConrad Meyer #define AMDRAS_MCA_OF_RECOV 0x00000001 375cd8c2581SConrad Meyer #define AMDRAS_SUCCOR 0x00000002 376cd8c2581SConrad Meyer #define AMDRAS_HW_ASSERT 0x00000004 377cd8c2581SConrad Meyer #define AMDRAS_SCALABLE_MCA 0x00000008 378cd8c2581SConrad Meyer #define AMDRAS_PFEH_SUPPORT 0x00000010 379cd8c2581SConrad Meyer 380cd8c2581SConrad Meyer /* 3812c7879eaSTijl Coosemans * AMD extended function 8000_0007h edx info 3822c7879eaSTijl Coosemans */ 3832c7879eaSTijl Coosemans #define AMDPM_TS 0x00000001 3842c7879eaSTijl Coosemans #define AMDPM_FID 0x00000002 3852c7879eaSTijl Coosemans #define AMDPM_VID 0x00000004 3862c7879eaSTijl Coosemans #define AMDPM_TTP 0x00000008 3872c7879eaSTijl Coosemans #define AMDPM_TM 0x00000010 3882c7879eaSTijl Coosemans #define AMDPM_STC 0x00000020 3892c7879eaSTijl Coosemans #define AMDPM_100MHZ_STEPS 0x00000040 3902c7879eaSTijl Coosemans #define AMDPM_HW_PSTATE 0x00000080 3912c7879eaSTijl Coosemans #define AMDPM_TSC_INVARIANT 0x00000100 3922c7879eaSTijl Coosemans #define AMDPM_CPB 0x00000200 3932c7879eaSTijl Coosemans 3942c7879eaSTijl Coosemans /* 395194446f9SConrad Meyer * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions) 396194446f9SConrad Meyer */ 397194446f9SConrad Meyer #define AMDFEID_CLZERO 0x00000001 398194446f9SConrad Meyer #define AMDFEID_IRPERF 0x00000002 399194446f9SConrad Meyer #define AMDFEID_XSAVEERPTR 0x00000004 400*c6113ac5SKonstantin Belousov #define AMDFEID_INVLPGB 0x00000008 401ebcfcba8SConrad Meyer #define AMDFEID_RDPRU 0x00000010 402*c6113ac5SKonstantin Belousov #define AMDFEID_BE 0x00000040 403706bc29bSConrad Meyer #define AMDFEID_MCOMMIT 0x00000100 404706bc29bSConrad Meyer #define AMDFEID_WBNOINVD 0x00000200 40516068ae4SConrad Meyer #define AMDFEID_IBPB 0x00001000 406*c6113ac5SKonstantin Belousov #define AMDFEID_INT_WBINVD 0x00002000 40716068ae4SConrad Meyer #define AMDFEID_IBRS 0x00004000 40816068ae4SConrad Meyer #define AMDFEID_STIBP 0x00008000 40916068ae4SConrad Meyer /* The below are only defined if the corresponding base feature above exists. */ 41016068ae4SConrad Meyer #define AMDFEID_IBRS_ALWAYSON 0x00010000 41116068ae4SConrad Meyer #define AMDFEID_STIBP_ALWAYSON 0x00020000 41216068ae4SConrad Meyer #define AMDFEID_PREFER_IBRS 0x00040000 413*c6113ac5SKonstantin Belousov #define AMDFEID_SAMEMODE_IBRS 0x00080000 414*c6113ac5SKonstantin Belousov #define AMDFEID_NO_LMSLE 0x00100000 415*c6113ac5SKonstantin Belousov #define AMDFEID_INVLPGB_NEST 0x00200000 4169d3b7f62SConrad Meyer #define AMDFEID_PPIN 0x00800000 41716068ae4SConrad Meyer #define AMDFEID_SSBD 0x01000000 41816068ae4SConrad Meyer /* SSBD via MSRC001_011F instead of MSR 0x48: */ 41916068ae4SConrad Meyer #define AMDFEID_VIRT_SSBD 0x02000000 42016068ae4SConrad Meyer #define AMDFEID_SSB_NO 0x04000000 421*c6113ac5SKonstantin Belousov #define AMDFEID_CPPC 0x08000000 422*c6113ac5SKonstantin Belousov #define AMDFEID_PSFD 0x10000000 423*c6113ac5SKonstantin Belousov #define AMDFEID_BTC_NO 0x20000000 424*c6113ac5SKonstantin Belousov #define AMDFEID_IBPB_RET 0x40000000 425194446f9SConrad Meyer 426194446f9SConrad Meyer /* 4272c7879eaSTijl Coosemans * AMD extended function 8000_0008h ecx info 4282c7879eaSTijl Coosemans */ 4292c7879eaSTijl Coosemans #define AMDID_CMP_CORES 0x000000ff 4302c7879eaSTijl Coosemans #define AMDID_COREID_SIZE 0x0000f000 4312c7879eaSTijl Coosemans #define AMDID_COREID_SIZE_SHIFT 12 4322c7879eaSTijl Coosemans 4335dfae122SRui Paulo /* 434*c6113ac5SKonstantin Belousov * AMD extended function 8000_0008h edx info 435*c6113ac5SKonstantin Belousov */ 436*c6113ac5SKonstantin Belousov #define AMDID_INVLPGB_MAXCNT 0x0000ffff 437*c6113ac5SKonstantin Belousov #define AMDID_RDPRU_SHIFT 16 438*c6113ac5SKonstantin Belousov #define AMDID_RDPRU_ID 0xffff0000 439*c6113ac5SKonstantin Belousov 440*c6113ac5SKonstantin Belousov /* 441355d8a2fSJohn Baldwin * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info 4425dfae122SRui Paulo */ 4432773649dSKonstantin Belousov #define CPUID_STDEXT_FSGSBASE 0x00000001 4442773649dSKonstantin Belousov #define CPUID_STDEXT_TSC_ADJUST 0x00000002 445c5c20928SKonstantin Belousov #define CPUID_STDEXT_SGX 0x00000004 4465dfae122SRui Paulo #define CPUID_STDEXT_BMI1 0x00000008 4475dfae122SRui Paulo #define CPUID_STDEXT_HLE 0x00000010 4485dfae122SRui Paulo #define CPUID_STDEXT_AVX2 0x00000020 4496b247f85SKonstantin Belousov #define CPUID_STDEXT_FDP_EXC 0x00000040 4502773649dSKonstantin Belousov #define CPUID_STDEXT_SMEP 0x00000080 4515dfae122SRui Paulo #define CPUID_STDEXT_BMI2 0x00000100 452355d8a2fSJohn Baldwin #define CPUID_STDEXT_ERMS 0x00000200 4532773649dSKonstantin Belousov #define CPUID_STDEXT_INVPCID 0x00000400 454355d8a2fSJohn Baldwin #define CPUID_STDEXT_RTM 0x00000800 455c5c20928SKonstantin Belousov #define CPUID_STDEXT_PQM 0x00001000 456c5c20928SKonstantin Belousov #define CPUID_STDEXT_NFPUSG 0x00002000 457355d8a2fSJohn Baldwin #define CPUID_STDEXT_MPX 0x00004000 458c5c20928SKonstantin Belousov #define CPUID_STDEXT_PQE 0x00008000 459355d8a2fSJohn Baldwin #define CPUID_STDEXT_AVX512F 0x00010000 460986fd63bSConrad Meyer #define CPUID_STDEXT_AVX512DQ 0x00020000 4615dfae122SRui Paulo #define CPUID_STDEXT_RDSEED 0x00040000 4625dfae122SRui Paulo #define CPUID_STDEXT_ADX 0x00080000 4635dfae122SRui Paulo #define CPUID_STDEXT_SMAP 0x00100000 464986fd63bSConrad Meyer #define CPUID_STDEXT_AVX512IFMA 0x00200000 465bb044eafSConrad Meyer /* Formerly PCOMMIT */ 466355d8a2fSJohn Baldwin #define CPUID_STDEXT_CLFLUSHOPT 0x00800000 467986fd63bSConrad Meyer #define CPUID_STDEXT_CLWB 0x01000000 468355d8a2fSJohn Baldwin #define CPUID_STDEXT_PROCTRACE 0x02000000 469355d8a2fSJohn Baldwin #define CPUID_STDEXT_AVX512PF 0x04000000 470355d8a2fSJohn Baldwin #define CPUID_STDEXT_AVX512ER 0x08000000 471355d8a2fSJohn Baldwin #define CPUID_STDEXT_AVX512CD 0x10000000 472355d8a2fSJohn Baldwin #define CPUID_STDEXT_SHA 0x20000000 473986fd63bSConrad Meyer #define CPUID_STDEXT_AVX512BW 0x40000000 4746332b148SKonstantin Belousov #define CPUID_STDEXT_AVX512VL 0x80000000 4752773649dSKonstantin Belousov 4762c7879eaSTijl Coosemans /* 477c5c20928SKonstantin Belousov * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info 478c5c20928SKonstantin Belousov */ 479c5c20928SKonstantin Belousov #define CPUID_STDEXT2_PREFETCHWT1 0x00000001 480c63f1e21SConrad Meyer #define CPUID_STDEXT2_AVX512VBMI 0x00000002 481c5c20928SKonstantin Belousov #define CPUID_STDEXT2_UMIP 0x00000004 482c5c20928SKonstantin Belousov #define CPUID_STDEXT2_PKU 0x00000008 483c5c20928SKonstantin Belousov #define CPUID_STDEXT2_OSPKE 0x00000010 484ccc2d07eSKonstantin Belousov #define CPUID_STDEXT2_WAITPKG 0x00000020 485c63f1e21SConrad Meyer #define CPUID_STDEXT2_AVX512VBMI2 0x00000040 486ccc2d07eSKonstantin Belousov #define CPUID_STDEXT2_GFNI 0x00000100 487c63f1e21SConrad Meyer #define CPUID_STDEXT2_VAES 0x00000200 488c63f1e21SConrad Meyer #define CPUID_STDEXT2_VPCLMULQDQ 0x00000400 489c63f1e21SConrad Meyer #define CPUID_STDEXT2_AVX512VNNI 0x00000800 490c63f1e21SConrad Meyer #define CPUID_STDEXT2_AVX512BITALG 0x00001000 4919d3b7f62SConrad Meyer #define CPUID_STDEXT2_TME 0x00002000 492c63f1e21SConrad Meyer #define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000 4939d3b7f62SConrad Meyer #define CPUID_STDEXT2_LA57 0x00010000 494c5c20928SKonstantin Belousov #define CPUID_STDEXT2_RDPID 0x00400000 495ccc2d07eSKonstantin Belousov #define CPUID_STDEXT2_CLDEMOTE 0x02000000 496ccc2d07eSKonstantin Belousov #define CPUID_STDEXT2_MOVDIRI 0x08000000 497d23e252dSConrad Meyer #define CPUID_STDEXT2_MOVDIR64B 0x10000000 498c63f1e21SConrad Meyer #define CPUID_STDEXT2_ENQCMD 0x20000000 499c5c20928SKonstantin Belousov #define CPUID_STDEXT2_SGXLC 0x40000000 500c5c20928SKonstantin Belousov 501c5c20928SKonstantin Belousov /* 502e8c770a6SKonstantin Belousov * CPUID instruction 7 Structured Extended Features, leaf 0 edx info 503e8c770a6SKonstantin Belousov */ 504c63f1e21SConrad Meyer #define CPUID_STDEXT3_AVX5124VNNIW 0x00000004 505c63f1e21SConrad Meyer #define CPUID_STDEXT3_AVX5124FMAPS 0x00000008 5069d3b7f62SConrad Meyer #define CPUID_STDEXT3_FSRM 0x00000010 507c63f1e21SConrad Meyer #define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100 508958d257eSKonstantin Belousov #define CPUID_STDEXT3_MCUOPT 0x00000200 5097355a02bSKonstantin Belousov #define CPUID_STDEXT3_MD_CLEAR 0x00000400 5103dcf329eSKonstantin Belousov #define CPUID_STDEXT3_TSXFA 0x00002000 511c63f1e21SConrad Meyer #define CPUID_STDEXT3_PCONFIG 0x00040000 512e8c770a6SKonstantin Belousov #define CPUID_STDEXT3_IBPB 0x04000000 513e8c770a6SKonstantin Belousov #define CPUID_STDEXT3_STIBP 0x08000000 5148d32b463SKonstantin Belousov #define CPUID_STDEXT3_L1D_FLUSH 0x10000000 515e8c770a6SKonstantin Belousov #define CPUID_STDEXT3_ARCH_CAP 0x20000000 516ccc2d07eSKonstantin Belousov #define CPUID_STDEXT3_CORE_CAP 0x40000000 5179be4bbbbSKonstantin Belousov #define CPUID_STDEXT3_SSBD 0x80000000 518e8c770a6SKonstantin Belousov 51945ac7755SKonstantin Belousov /* CPUID_HYBRID_ID leaf 0x1a */ 52045ac7755SKonstantin Belousov #define CPUID_HYBRID_CORE_MASK 0xff000000 52145ac7755SKonstantin Belousov #define CPUID_HYBRID_SMALL_CORE 0x20000000 52245ac7755SKonstantin Belousov #define CPUID_HYBRID_LARGE_CORE 0x40000000 52345ac7755SKonstantin Belousov 524e8c770a6SKonstantin Belousov /* MSR IA32_ARCH_CAP(ABILITIES) bits */ 525e8c770a6SKonstantin Belousov #define IA32_ARCH_CAP_RDCL_NO 0x00000001 526e8c770a6SKonstantin Belousov #define IA32_ARCH_CAP_IBRS_ALL 0x00000002 52723437573SKonstantin Belousov #define IA32_ARCH_CAP_RSBA 0x00000004 52823437573SKonstantin Belousov #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008 52923437573SKonstantin Belousov #define IA32_ARCH_CAP_SSB_NO 0x00000010 5307355a02bSKonstantin Belousov #define IA32_ARCH_CAP_MDS_NO 0x00000020 531c08973d0SKonstantin Belousov #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040 532837d7332SScott Long #define IA32_ARCH_CAP_TSX_CTRL 0x00000080 533837d7332SScott Long #define IA32_ARCH_CAP_TAA_NO 0x00000100 534837d7332SScott Long 535837d7332SScott Long /* MSR IA32_TSX_CTRL bits */ 536837d7332SScott Long #define IA32_TSX_CTRL_RTM_DISABLE 0x00000001 537837d7332SScott Long #define IA32_TSX_CTRL_TSX_CPUID_CLEAR 0x00000002 538e8c770a6SKonstantin Belousov 539e8c770a6SKonstantin Belousov /* 5402c7879eaSTijl Coosemans * CPUID manufacturers identifiers 5412c7879eaSTijl Coosemans */ 5422c7879eaSTijl Coosemans #define AMD_VENDOR_ID "AuthenticAMD" 5432c7879eaSTijl Coosemans #define CENTAUR_VENDOR_ID "CentaurHauls" 5442c7879eaSTijl Coosemans #define CYRIX_VENDOR_ID "CyrixInstead" 5452c7879eaSTijl Coosemans #define INTEL_VENDOR_ID "GenuineIntel" 5462c7879eaSTijl Coosemans #define NEXGEN_VENDOR_ID "NexGenDriven" 5472c7879eaSTijl Coosemans #define NSC_VENDOR_ID "Geode by NSC" 5482c7879eaSTijl Coosemans #define RISE_VENDOR_ID "RiseRiseRise" 5492c7879eaSTijl Coosemans #define SIS_VENDOR_ID "SiS SiS SiS " 5502c7879eaSTijl Coosemans #define TRANSMETA_VENDOR_ID "GenuineTMx86" 5512c7879eaSTijl Coosemans #define UMC_VENDOR_ID "UMC UMC UMC " 5522ee49facSKonstantin Belousov #define HYGON_VENDOR_ID "HygonGenuine" 5532c7879eaSTijl Coosemans 5542c7879eaSTijl Coosemans /* 5552c7879eaSTijl Coosemans * Model-specific registers for the i386 family 5562c7879eaSTijl Coosemans */ 5572c7879eaSTijl Coosemans #define MSR_P5_MC_ADDR 0x000 5582c7879eaSTijl Coosemans #define MSR_P5_MC_TYPE 0x001 5592c7879eaSTijl Coosemans #define MSR_TSC 0x010 5602c7879eaSTijl Coosemans #define MSR_P5_CESR 0x011 5612c7879eaSTijl Coosemans #define MSR_P5_CTR0 0x012 5622c7879eaSTijl Coosemans #define MSR_P5_CTR1 0x013 5632c7879eaSTijl Coosemans #define MSR_IA32_PLATFORM_ID 0x017 5642c7879eaSTijl Coosemans #define MSR_APICBASE 0x01b 5652c7879eaSTijl Coosemans #define MSR_EBL_CR_POWERON 0x02a 5662c7879eaSTijl Coosemans #define MSR_TEST_CTL 0x033 567bf70b875SNeel Natu #define MSR_IA32_FEATURE_CONTROL 0x03a 568e8c770a6SKonstantin Belousov #define MSR_IA32_SPEC_CTRL 0x048 569e8c770a6SKonstantin Belousov #define MSR_IA32_PRED_CMD 0x049 5702c7879eaSTijl Coosemans #define MSR_BIOS_UPDT_TRIG 0x079 5712c7879eaSTijl Coosemans #define MSR_BBL_CR_D0 0x088 5722c7879eaSTijl Coosemans #define MSR_BBL_CR_D1 0x089 5732c7879eaSTijl Coosemans #define MSR_BBL_CR_D2 0x08a 5742c7879eaSTijl Coosemans #define MSR_BIOS_SIGN 0x08b 5752c7879eaSTijl Coosemans #define MSR_PERFCTR0 0x0c1 5762c7879eaSTijl Coosemans #define MSR_PERFCTR1 0x0c2 5775295c3e6SNeel Natu #define MSR_PLATFORM_INFO 0x0ce 5782c7879eaSTijl Coosemans #define MSR_MPERF 0x0e7 5792c7879eaSTijl Coosemans #define MSR_APERF 0x0e8 5802c7879eaSTijl Coosemans #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 5812c7879eaSTijl Coosemans #define MSR_MTRRcap 0x0fe 582e8c770a6SKonstantin Belousov #define MSR_IA32_ARCH_CAP 0x10a 5838d32b463SKonstantin Belousov #define MSR_IA32_FLUSH_CMD 0x10b 5843dcf329eSKonstantin Belousov #define MSR_TSX_FORCE_ABORT 0x10f 5852c7879eaSTijl Coosemans #define MSR_BBL_CR_ADDR 0x116 5862c7879eaSTijl Coosemans #define MSR_BBL_CR_DECC 0x118 5872c7879eaSTijl Coosemans #define MSR_BBL_CR_CTL 0x119 5882c7879eaSTijl Coosemans #define MSR_BBL_CR_TRIG 0x11a 5892c7879eaSTijl Coosemans #define MSR_BBL_CR_BUSY 0x11b 5902c7879eaSTijl Coosemans #define MSR_BBL_CR_CTL3 0x11e 591837d7332SScott Long #define MSR_IA32_TSX_CTRL 0x122 592958d257eSKonstantin Belousov #define MSR_IA32_MCU_OPT_CTRL 0x123 5931d21f641SWarner Losh #define MSR_MISC_FEATURE_ENABLES 0x140 5942c7879eaSTijl Coosemans #define MSR_SYSENTER_CS_MSR 0x174 5952c7879eaSTijl Coosemans #define MSR_SYSENTER_ESP_MSR 0x175 5962c7879eaSTijl Coosemans #define MSR_SYSENTER_EIP_MSR 0x176 5972c7879eaSTijl Coosemans #define MSR_MCG_CAP 0x179 5982c7879eaSTijl Coosemans #define MSR_MCG_STATUS 0x17a 5992c7879eaSTijl Coosemans #define MSR_MCG_CTL 0x17b 6002c7879eaSTijl Coosemans #define MSR_EVNTSEL0 0x186 6012c7879eaSTijl Coosemans #define MSR_EVNTSEL1 0x187 6022c7879eaSTijl Coosemans #define MSR_THERM_CONTROL 0x19a 6032c7879eaSTijl Coosemans #define MSR_THERM_INTERRUPT 0x19b 6042c7879eaSTijl Coosemans #define MSR_THERM_STATUS 0x19c 6052c7879eaSTijl Coosemans #define MSR_IA32_MISC_ENABLE 0x1a0 6062c7879eaSTijl Coosemans #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 6075295c3e6SNeel Natu #define MSR_TURBO_RATIO_LIMIT 0x1ad 6085295c3e6SNeel Natu #define MSR_TURBO_RATIO_LIMIT1 0x1ae 6095e3574c8SConrad Meyer #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0 610338d5396SKoine Yuusuke #define MSR_IA32_PKG_THERM_STATUS 0x1b1 611338d5396SKoine Yuusuke #define MSR_IA32_PKG_THERM_INTERRUPT 0x1b2 6122c7879eaSTijl Coosemans #define MSR_DEBUGCTLMSR 0x1d9 6132c7879eaSTijl Coosemans #define MSR_LASTBRANCHFROMIP 0x1db 6142c7879eaSTijl Coosemans #define MSR_LASTBRANCHTOIP 0x1dc 6152c7879eaSTijl Coosemans #define MSR_LASTINTFROMIP 0x1dd 6162c7879eaSTijl Coosemans #define MSR_LASTINTTOIP 0x1de 6172c7879eaSTijl Coosemans #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 6182c7879eaSTijl Coosemans #define MSR_MTRRVarBase 0x200 6192c7879eaSTijl Coosemans #define MSR_MTRR64kBase 0x250 6202c7879eaSTijl Coosemans #define MSR_MTRR16kBase 0x258 6212c7879eaSTijl Coosemans #define MSR_MTRR4kBase 0x268 6222c7879eaSTijl Coosemans #define MSR_PAT 0x277 6232c7879eaSTijl Coosemans #define MSR_MC0_CTL2 0x280 6242c7879eaSTijl Coosemans #define MSR_MTRRdefType 0x2ff 6252c7879eaSTijl Coosemans #define MSR_MC0_CTL 0x400 6262c7879eaSTijl Coosemans #define MSR_MC0_STATUS 0x401 6272c7879eaSTijl Coosemans #define MSR_MC0_ADDR 0x402 6282c7879eaSTijl Coosemans #define MSR_MC0_MISC 0x403 6292c7879eaSTijl Coosemans #define MSR_MC1_CTL 0x404 6302c7879eaSTijl Coosemans #define MSR_MC1_STATUS 0x405 6312c7879eaSTijl Coosemans #define MSR_MC1_ADDR 0x406 6322c7879eaSTijl Coosemans #define MSR_MC1_MISC 0x407 6332c7879eaSTijl Coosemans #define MSR_MC2_CTL 0x408 6342c7879eaSTijl Coosemans #define MSR_MC2_STATUS 0x409 6352c7879eaSTijl Coosemans #define MSR_MC2_ADDR 0x40a 6362c7879eaSTijl Coosemans #define MSR_MC2_MISC 0x40b 6372c7879eaSTijl Coosemans #define MSR_MC3_CTL 0x40c 6382c7879eaSTijl Coosemans #define MSR_MC3_STATUS 0x40d 6392c7879eaSTijl Coosemans #define MSR_MC3_ADDR 0x40e 6402c7879eaSTijl Coosemans #define MSR_MC3_MISC 0x40f 6412c7879eaSTijl Coosemans #define MSR_MC4_CTL 0x410 6422c7879eaSTijl Coosemans #define MSR_MC4_STATUS 0x411 6432c7879eaSTijl Coosemans #define MSR_MC4_ADDR 0x412 6442c7879eaSTijl Coosemans #define MSR_MC4_MISC 0x413 6453bdba24cSAlexander Motin #define MSR_MCG_EXT_CTL 0x4d0 6465295c3e6SNeel Natu #define MSR_RAPL_POWER_UNIT 0x606 647c3498942SNeel Natu #define MSR_PKG_ENERGY_STATUS 0x611 648c3498942SNeel Natu #define MSR_DRAM_ENERGY_STATUS 0x619 649c3498942SNeel Natu #define MSR_PP0_ENERGY_STATUS 0x639 650c3498942SNeel Natu #define MSR_PP1_ENERGY_STATUS 0x641 65191890b73SBen Widawsky #define MSR_PPERF 0x64e 6527c4e7693SKonstantin Belousov #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */ 65391890b73SBen Widawsky #define MSR_IA32_PM_ENABLE 0x770 65491890b73SBen Widawsky #define MSR_IA32_HWP_CAPABILITIES 0x771 65591890b73SBen Widawsky #define MSR_IA32_HWP_REQUEST_PKG 0x772 65691890b73SBen Widawsky #define MSR_IA32_HWP_INTERRUPT 0x773 65791890b73SBen Widawsky #define MSR_IA32_HWP_REQUEST 0x774 65891890b73SBen Widawsky #define MSR_IA32_HWP_STATUS 0x777 6592c7879eaSTijl Coosemans 6602c7879eaSTijl Coosemans /* 66106fc6db9SJohn Baldwin * VMX MSRs 66206fc6db9SJohn Baldwin */ 66306fc6db9SJohn Baldwin #define MSR_VMX_BASIC 0x480 66406fc6db9SJohn Baldwin #define MSR_VMX_PINBASED_CTLS 0x481 66506fc6db9SJohn Baldwin #define MSR_VMX_PROCBASED_CTLS 0x482 66606fc6db9SJohn Baldwin #define MSR_VMX_EXIT_CTLS 0x483 66706fc6db9SJohn Baldwin #define MSR_VMX_ENTRY_CTLS 0x484 66806fc6db9SJohn Baldwin #define MSR_VMX_CR0_FIXED0 0x486 66906fc6db9SJohn Baldwin #define MSR_VMX_CR0_FIXED1 0x487 67006fc6db9SJohn Baldwin #define MSR_VMX_CR4_FIXED0 0x488 67106fc6db9SJohn Baldwin #define MSR_VMX_CR4_FIXED1 0x489 67206fc6db9SJohn Baldwin #define MSR_VMX_PROCBASED_CTLS2 0x48b 67306fc6db9SJohn Baldwin #define MSR_VMX_EPT_VPID_CAP 0x48c 67406fc6db9SJohn Baldwin #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d 67506fc6db9SJohn Baldwin #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e 67606fc6db9SJohn Baldwin #define MSR_VMX_TRUE_EXIT_CTLS 0x48f 67706fc6db9SJohn Baldwin #define MSR_VMX_TRUE_ENTRY_CTLS 0x490 67806fc6db9SJohn Baldwin 67906fc6db9SJohn Baldwin /* 6807c4e7693SKonstantin Belousov * X2APIC MSRs. 6817c4e7693SKonstantin Belousov * Writes are not serializing. 68226b1d645SPeter Grehan */ 6834c918926SKonstantin Belousov #define MSR_APIC_000 0x800 68426b1d645SPeter Grehan #define MSR_APIC_ID 0x802 68526b1d645SPeter Grehan #define MSR_APIC_VERSION 0x803 68626b1d645SPeter Grehan #define MSR_APIC_TPR 0x808 68726b1d645SPeter Grehan #define MSR_APIC_EOI 0x80b 68826b1d645SPeter Grehan #define MSR_APIC_LDR 0x80d 68926b1d645SPeter Grehan #define MSR_APIC_SVR 0x80f 69026b1d645SPeter Grehan #define MSR_APIC_ISR0 0x810 69126b1d645SPeter Grehan #define MSR_APIC_ISR1 0x811 69226b1d645SPeter Grehan #define MSR_APIC_ISR2 0x812 69326b1d645SPeter Grehan #define MSR_APIC_ISR3 0x813 69426b1d645SPeter Grehan #define MSR_APIC_ISR4 0x814 69526b1d645SPeter Grehan #define MSR_APIC_ISR5 0x815 69626b1d645SPeter Grehan #define MSR_APIC_ISR6 0x816 69726b1d645SPeter Grehan #define MSR_APIC_ISR7 0x817 69826b1d645SPeter Grehan #define MSR_APIC_TMR0 0x818 69926b1d645SPeter Grehan #define MSR_APIC_IRR0 0x820 70026b1d645SPeter Grehan #define MSR_APIC_ESR 0x828 70126b1d645SPeter Grehan #define MSR_APIC_LVT_CMCI 0x82F 70226b1d645SPeter Grehan #define MSR_APIC_ICR 0x830 70326b1d645SPeter Grehan #define MSR_APIC_LVT_TIMER 0x832 70426b1d645SPeter Grehan #define MSR_APIC_LVT_THERMAL 0x833 70526b1d645SPeter Grehan #define MSR_APIC_LVT_PCINT 0x834 70626b1d645SPeter Grehan #define MSR_APIC_LVT_LINT0 0x835 70726b1d645SPeter Grehan #define MSR_APIC_LVT_LINT1 0x836 70826b1d645SPeter Grehan #define MSR_APIC_LVT_ERROR 0x837 70926b1d645SPeter Grehan #define MSR_APIC_ICR_TIMER 0x838 71026b1d645SPeter Grehan #define MSR_APIC_CCR_TIMER 0x839 71126b1d645SPeter Grehan #define MSR_APIC_DCR_TIMER 0x83e 71226b1d645SPeter Grehan #define MSR_APIC_SELF_IPI 0x83f 71326b1d645SPeter Grehan 71427d21b9eSKonstantin Belousov #define MSR_IA32_XSS 0xda0 71527d21b9eSKonstantin Belousov 71626b1d645SPeter Grehan /* 717b510dab3SRuslan Bukin * Intel Processor Trace (PT) MSRs. 718b510dab3SRuslan Bukin */ 719b510dab3SRuslan Bukin #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */ 720b510dab3SRuslan Bukin #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */ 721b510dab3SRuslan Bukin #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */ 722b510dab3SRuslan Bukin #define RTIT_CTL_TRACEEN (1 << 0) 723b510dab3SRuslan Bukin #define RTIT_CTL_CYCEN (1 << 1) 724b510dab3SRuslan Bukin #define RTIT_CTL_OS (1 << 2) 725b510dab3SRuslan Bukin #define RTIT_CTL_USER (1 << 3) 726b510dab3SRuslan Bukin #define RTIT_CTL_PWREVTEN (1 << 4) 727b510dab3SRuslan Bukin #define RTIT_CTL_FUPONPTW (1 << 5) 728b510dab3SRuslan Bukin #define RTIT_CTL_FABRICEN (1 << 6) 729b510dab3SRuslan Bukin #define RTIT_CTL_CR3FILTER (1 << 7) 730b510dab3SRuslan Bukin #define RTIT_CTL_TOPA (1 << 8) 731b510dab3SRuslan Bukin #define RTIT_CTL_MTCEN (1 << 9) 732b510dab3SRuslan Bukin #define RTIT_CTL_TSCEN (1 << 10) 733b510dab3SRuslan Bukin #define RTIT_CTL_DISRETC (1 << 11) 734b510dab3SRuslan Bukin #define RTIT_CTL_PTWEN (1 << 12) 735b510dab3SRuslan Bukin #define RTIT_CTL_BRANCHEN (1 << 13) 736b510dab3SRuslan Bukin #define RTIT_CTL_MTC_FREQ_S 14 737b510dab3SRuslan Bukin #define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S) 738b510dab3SRuslan Bukin #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S) 739b510dab3SRuslan Bukin #define RTIT_CTL_CYC_THRESH_S 19 740b510dab3SRuslan Bukin #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S) 741b510dab3SRuslan Bukin #define RTIT_CTL_PSB_FREQ_S 24 742b510dab3SRuslan Bukin #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S) 743b510dab3SRuslan Bukin #define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4) 744b510dab3SRuslan Bukin #define RTIT_CTL_ADDR0_CFG_S 32 745b510dab3SRuslan Bukin #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S) 746b510dab3SRuslan Bukin #define RTIT_CTL_ADDR1_CFG_S 36 747b510dab3SRuslan Bukin #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S) 748b510dab3SRuslan Bukin #define RTIT_CTL_ADDR2_CFG_S 40 749b510dab3SRuslan Bukin #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S) 750b510dab3SRuslan Bukin #define RTIT_CTL_ADDR3_CFG_S 44 751b510dab3SRuslan Bukin #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S) 752b510dab3SRuslan Bukin #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */ 753b510dab3SRuslan Bukin #define RTIT_STATUS_FILTEREN (1 << 0) 754b510dab3SRuslan Bukin #define RTIT_STATUS_CONTEXTEN (1 << 1) 755b510dab3SRuslan Bukin #define RTIT_STATUS_TRIGGEREN (1 << 2) 756b510dab3SRuslan Bukin #define RTIT_STATUS_ERROR (1 << 4) 757b510dab3SRuslan Bukin #define RTIT_STATUS_STOPPED (1 << 5) 758b510dab3SRuslan Bukin #define RTIT_STATUS_PACKETBYTECNT_S 32 759b510dab3SRuslan Bukin #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S) 760b510dab3SRuslan Bukin #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */ 761b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2) 762b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2) 763b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */ 764b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */ 765b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */ 766b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */ 767b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */ 768b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */ 769b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */ 770b510dab3SRuslan Bukin #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */ 771b510dab3SRuslan Bukin 7723b418d1bSRuslan Bukin /* Intel Processor Trace Table of Physical Addresses (ToPA). */ 7733b418d1bSRuslan Bukin #define TOPA_SIZE_S 6 7743b418d1bSRuslan Bukin #define TOPA_SIZE_M (0xf << TOPA_SIZE_S) 7753b418d1bSRuslan Bukin #define TOPA_SIZE_4K (0 << TOPA_SIZE_S) 7763b418d1bSRuslan Bukin #define TOPA_SIZE_8K (1 << TOPA_SIZE_S) 7773b418d1bSRuslan Bukin #define TOPA_SIZE_16K (2 << TOPA_SIZE_S) 7783b418d1bSRuslan Bukin #define TOPA_SIZE_32K (3 << TOPA_SIZE_S) 7793b418d1bSRuslan Bukin #define TOPA_SIZE_64K (4 << TOPA_SIZE_S) 7803b418d1bSRuslan Bukin #define TOPA_SIZE_128K (5 << TOPA_SIZE_S) 7813b418d1bSRuslan Bukin #define TOPA_SIZE_256K (6 << TOPA_SIZE_S) 7823b418d1bSRuslan Bukin #define TOPA_SIZE_512K (7 << TOPA_SIZE_S) 7833b418d1bSRuslan Bukin #define TOPA_SIZE_1M (8 << TOPA_SIZE_S) 7843b418d1bSRuslan Bukin #define TOPA_SIZE_2M (9 << TOPA_SIZE_S) 7853b418d1bSRuslan Bukin #define TOPA_SIZE_4M (10 << TOPA_SIZE_S) 7863b418d1bSRuslan Bukin #define TOPA_SIZE_8M (11 << TOPA_SIZE_S) 7873b418d1bSRuslan Bukin #define TOPA_SIZE_16M (12 << TOPA_SIZE_S) 7883b418d1bSRuslan Bukin #define TOPA_SIZE_32M (13 << TOPA_SIZE_S) 7893b418d1bSRuslan Bukin #define TOPA_SIZE_64M (14 << TOPA_SIZE_S) 7903b418d1bSRuslan Bukin #define TOPA_SIZE_128M (15 << TOPA_SIZE_S) 7913b418d1bSRuslan Bukin #define TOPA_STOP (1 << 4) 7923b418d1bSRuslan Bukin #define TOPA_INT (1 << 2) 7933b418d1bSRuslan Bukin #define TOPA_END (1 << 0) 7943b418d1bSRuslan Bukin 795b510dab3SRuslan Bukin /* 796338d5396SKoine Yuusuke * Intel Hardware Feedback Interface / Thread Director MSRs 797338d5396SKoine Yuusuke */ 798338d5396SKoine Yuusuke #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 799338d5396SKoine Yuusuke #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 800338d5396SKoine Yuusuke #define MSR_IA32_THREAD_FEEDBACK_CHAR 0x17d2 801338d5396SKoine Yuusuke #define MSR_IA32_HW_FEEDBACK_THREAD_CONFIG 0x17d4 802338d5396SKoine Yuusuke 803338d5396SKoine Yuusuke /* 8042c7879eaSTijl Coosemans * Constants related to MSR's. 8052c7879eaSTijl Coosemans */ 80626b1d645SPeter Grehan #define APICBASE_RESERVED 0x000002ff 8072c7879eaSTijl Coosemans #define APICBASE_BSP 0x00000100 80826b1d645SPeter Grehan #define APICBASE_X2APIC 0x00000400 8092c7879eaSTijl Coosemans #define APICBASE_ENABLED 0x00000800 8102c7879eaSTijl Coosemans #define APICBASE_ADDRESS 0xfffff000 8112c7879eaSTijl Coosemans 812150369abSNeel Natu /* MSR_IA32_FEATURE_CONTROL related */ 813150369abSNeel Natu #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 814150369abSNeel Natu #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 815150369abSNeel Natu #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 8163bdba24cSAlexander Motin #define IA32_FEATURE_CONTROL_LMCE_EN 0x100000 /* enable local MCE */ 817150369abSNeel Natu 81890a2db45SKonstantin Belousov /* MSR IA32_MISC_ENABLE */ 81990a2db45SKonstantin Belousov #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL 82090a2db45SKonstantin Belousov #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL 82190a2db45SKonstantin Belousov #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL 82290a2db45SKonstantin Belousov #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL 82390a2db45SKonstantin Belousov #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL 82490a2db45SKonstantin Belousov #define IA32_MISC_EN_MONE 0x0000000000040000ULL 82590a2db45SKonstantin Belousov #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL 82690a2db45SKonstantin Belousov #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL 82790a2db45SKonstantin Belousov #define IA32_MISC_EN_XDD 0x0000000400000000ULL 82890a2db45SKonstantin Belousov 829319117fdSKonstantin Belousov /* 830319117fdSKonstantin Belousov * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel' 831319117fdSKonstantin Belousov * document 336996-001 Speculative Execution Side Channel Mitigations. 83216068ae4SConrad Meyer * 83316068ae4SConrad Meyer * AMD uses the same MSRs and bit definitions, as described in 111006-B 83416068ae4SConrad Meyer * "Indirect Branch Control Extension" and 124441 "Speculative Store Bypass 83516068ae4SConrad Meyer * Disable." 836319117fdSKonstantin Belousov */ 837e8c770a6SKonstantin Belousov /* MSR IA32_SPEC_CTRL */ 838c688c905SKonstantin Belousov #define IA32_SPEC_CTRL_IBRS 0x00000001 839c688c905SKonstantin Belousov #define IA32_SPEC_CTRL_STIBP 0x00000002 8409be4bbbbSKonstantin Belousov #define IA32_SPEC_CTRL_SSBD 0x00000004 841e8c770a6SKonstantin Belousov 842e8c770a6SKonstantin Belousov /* MSR IA32_PRED_CMD */ 843e8c770a6SKonstantin Belousov #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL 844e8c770a6SKonstantin Belousov 8458d32b463SKonstantin Belousov /* MSR IA32_FLUSH_CMD */ 8468d32b463SKonstantin Belousov #define IA32_FLUSH_CMD_L1D 0x00000001 8478d32b463SKonstantin Belousov 848958d257eSKonstantin Belousov /* MSR IA32_MCU_OPT_CTRL */ 849958d257eSKonstantin Belousov #define IA32_RNGDS_MITG_DIS 0x00000001 850958d257eSKonstantin Belousov 85191890b73SBen Widawsky /* MSR IA32_HWP_CAPABILITIES */ 85291890b73SBen Widawsky #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff) 85391890b73SBen Widawsky #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff) 85491890b73SBen Widawsky #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff) 85591890b73SBen Widawsky #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff) 85691890b73SBen Widawsky 85791890b73SBen Widawsky /* MSR IA32_HWP_REQUEST */ 85891890b73SBen Widawsky #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63) 85991890b73SBen Widawsky #define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62) 86091890b73SBen Widawsky #define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61) 86191890b73SBen Widawsky #define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60) 86291890b73SBen Widawsky #define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59) 86391890b73SBen Widawsky #define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42) 86491890b73SBen Widawsky #define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32) 86591890b73SBen Widawsky #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24) 86691890b73SBen Widawsky #define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16) 86791890b73SBen Widawsky #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8) 86891890b73SBen Widawsky #define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0) 86991890b73SBen Widawsky 870556a1a0bSConrad Meyer /* MSR IA32_ENERGY_PERF_BIAS */ 871556a1a0bSConrad Meyer #define IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK (0xfULL << 0) 872556a1a0bSConrad Meyer 873338d5396SKoine Yuusuke /* MSR IA32_HW_FEEDBACK_PTR */ 874338d5396SKoine Yuusuke #define IA32_HW_FEEDBACK_PTR_ENABLE (0x1ULL << 0) 875338d5396SKoine Yuusuke 876338d5396SKoine Yuusuke /* MSR IA32_HW_FEEDBACK_CONFIG */ 877338d5396SKoine Yuusuke #define IA32_HW_FEEDBACK_CONFIG_EN_HFI (0x1ULL << 0) 878338d5396SKoine Yuusuke #define IA32_HW_FEEDBACK_CONFIG_EN_THDIR (0x1ULL << 1) 879338d5396SKoine Yuusuke 880338d5396SKoine Yuusuke /* MSR IA32_PKG_THERM_STATUS */ 881338d5396SKoine Yuusuke #define IA32_PKG_THERM_STATUS_HFI_UPDATED (0x1ULL << 26) 882338d5396SKoine Yuusuke 883338d5396SKoine Yuusuke /* MSR IA32_PKG_THERM_INTERRUPT */ 884338d5396SKoine Yuusuke #define IA32_PKG_THERM_INTERRUPT_HFI_ENABLE (0x1ULL << 25) 885338d5396SKoine Yuusuke 8862c7879eaSTijl Coosemans /* 8872c7879eaSTijl Coosemans * PAT modes. 8882c7879eaSTijl Coosemans */ 8892c7879eaSTijl Coosemans #define PAT_UNCACHEABLE 0x00 8902c7879eaSTijl Coosemans #define PAT_WRITE_COMBINING 0x01 8912c7879eaSTijl Coosemans #define PAT_WRITE_THROUGH 0x04 8922c7879eaSTijl Coosemans #define PAT_WRITE_PROTECTED 0x05 8932c7879eaSTijl Coosemans #define PAT_WRITE_BACK 0x06 8942c7879eaSTijl Coosemans #define PAT_UNCACHED 0x07 8952c7879eaSTijl Coosemans #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 8962c7879eaSTijl Coosemans #define PAT_MASK(i) PAT_VALUE(i, 0xff) 8972c7879eaSTijl Coosemans 8982c7879eaSTijl Coosemans /* 8992c7879eaSTijl Coosemans * Constants related to MTRRs 9002c7879eaSTijl Coosemans */ 9012c7879eaSTijl Coosemans #define MTRR_UNCACHEABLE 0x00 9022c7879eaSTijl Coosemans #define MTRR_WRITE_COMBINING 0x01 9032c7879eaSTijl Coosemans #define MTRR_WRITE_THROUGH 0x04 9042c7879eaSTijl Coosemans #define MTRR_WRITE_PROTECTED 0x05 9052c7879eaSTijl Coosemans #define MTRR_WRITE_BACK 0x06 9062c7879eaSTijl Coosemans #define MTRR_N64K 8 /* numbers of fixed-size entries */ 9072c7879eaSTijl Coosemans #define MTRR_N16K 16 9082c7879eaSTijl Coosemans #define MTRR_N4K 64 9092c7879eaSTijl Coosemans #define MTRR_CAP_WC 0x0000000000000400 9102c7879eaSTijl Coosemans #define MTRR_CAP_FIXED 0x0000000000000100 9112c7879eaSTijl Coosemans #define MTRR_CAP_VCNT 0x00000000000000ff 9122c7879eaSTijl Coosemans #define MTRR_DEF_ENABLE 0x0000000000000800 9132c7879eaSTijl Coosemans #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 9142c7879eaSTijl Coosemans #define MTRR_DEF_TYPE 0x00000000000000ff 9152c7879eaSTijl Coosemans #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 9162c7879eaSTijl Coosemans #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 9172c7879eaSTijl Coosemans #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 9182c7879eaSTijl Coosemans #define MTRR_PHYSMASK_VALID 0x0000000000000800 9192c7879eaSTijl Coosemans 9202c7879eaSTijl Coosemans /* 9212c7879eaSTijl Coosemans * Cyrix configuration registers, accessible as IO ports. 9222c7879eaSTijl Coosemans */ 9232c7879eaSTijl Coosemans #define CCR0 0xc0 /* Configuration control register 0 */ 9242c7879eaSTijl Coosemans #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 9252c7879eaSTijl Coosemans non-cacheable */ 9262c7879eaSTijl Coosemans #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 9272c7879eaSTijl Coosemans #define CCR0_A20M 0x04 /* Enables A20M# input pin */ 9282c7879eaSTijl Coosemans #define CCR0_KEN 0x08 /* Enables KEN# input pin */ 9292c7879eaSTijl Coosemans #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 9302c7879eaSTijl Coosemans #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 9312c7879eaSTijl Coosemans state */ 9322c7879eaSTijl Coosemans #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 9332c7879eaSTijl Coosemans assoc */ 9342c7879eaSTijl Coosemans #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 9352c7879eaSTijl Coosemans 9362c7879eaSTijl Coosemans #define CCR1 0xc1 /* Configuration control register 1 */ 9372c7879eaSTijl Coosemans #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 9382c7879eaSTijl Coosemans #define CCR1_SMI 0x02 /* Enables SMM pins */ 9392c7879eaSTijl Coosemans #define CCR1_SMAC 0x04 /* System management memory access */ 9402c7879eaSTijl Coosemans #define CCR1_MMAC 0x08 /* Main memory access */ 9412c7879eaSTijl Coosemans #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 9422c7879eaSTijl Coosemans #define CCR1_SM3 0x80 /* SMM address space address region 3 */ 9432c7879eaSTijl Coosemans 9442c7879eaSTijl Coosemans #define CCR2 0xc2 9452c7879eaSTijl Coosemans #define CCR2_WB 0x02 /* Enables WB cache interface pins */ 9462c7879eaSTijl Coosemans #define CCR2_SADS 0x02 /* Slow ADS */ 9472c7879eaSTijl Coosemans #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 9482c7879eaSTijl Coosemans #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 9492c7879eaSTijl Coosemans #define CCR2_WT1 0x10 /* WT region 1 */ 9502c7879eaSTijl Coosemans #define CCR2_WPR1 0x10 /* Write-protect region 1 */ 9512c7879eaSTijl Coosemans #define CCR2_BARB 0x20 /* Flushes write-back cache when entering 9522c7879eaSTijl Coosemans hold state. */ 9532c7879eaSTijl Coosemans #define CCR2_BWRT 0x40 /* Enables burst write cycles */ 9542c7879eaSTijl Coosemans #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 9552c7879eaSTijl Coosemans 9562c7879eaSTijl Coosemans #define CCR3 0xc3 9572c7879eaSTijl Coosemans #define CCR3_SMILOCK 0x01 /* SMM register lock */ 9582c7879eaSTijl Coosemans #define CCR3_NMI 0x02 /* Enables NMI during SMM */ 9592c7879eaSTijl Coosemans #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 9602c7879eaSTijl Coosemans #define CCR3_SMMMODE 0x08 /* SMM Mode */ 9612c7879eaSTijl Coosemans #define CCR3_MAPEN0 0x10 /* Enables Map0 */ 9622c7879eaSTijl Coosemans #define CCR3_MAPEN1 0x20 /* Enables Map1 */ 9632c7879eaSTijl Coosemans #define CCR3_MAPEN2 0x40 /* Enables Map2 */ 9642c7879eaSTijl Coosemans #define CCR3_MAPEN3 0x80 /* Enables Map3 */ 9652c7879eaSTijl Coosemans 9662c7879eaSTijl Coosemans #define CCR4 0xe8 9672c7879eaSTijl Coosemans #define CCR4_IOMASK 0x07 968c1aa50bfSElyes Haouas #define CCR4_MEM 0x08 /* Enables memory bypassing */ 9692c7879eaSTijl Coosemans #define CCR4_DTE 0x10 /* Enables directory table entry cache */ 9702c7879eaSTijl Coosemans #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 9712c7879eaSTijl Coosemans #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 9722c7879eaSTijl Coosemans 9732c7879eaSTijl Coosemans #define CCR5 0xe9 9742c7879eaSTijl Coosemans #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 9752c7879eaSTijl Coosemans #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 9762c7879eaSTijl Coosemans #define CCR5_LBR1 0x10 /* Local bus region 1 */ 9772c7879eaSTijl Coosemans #define CCR5_ARREN 0x20 /* Enables ARR region */ 9782c7879eaSTijl Coosemans 9792c7879eaSTijl Coosemans #define CCR6 0xea 9802c7879eaSTijl Coosemans 9812c7879eaSTijl Coosemans #define CCR7 0xeb 9822c7879eaSTijl Coosemans 9832c7879eaSTijl Coosemans /* Performance Control Register (5x86 only). */ 9842c7879eaSTijl Coosemans #define PCR0 0x20 9852c7879eaSTijl Coosemans #define PCR0_RSTK 0x01 /* Enables return stack */ 9862c7879eaSTijl Coosemans #define PCR0_BTB 0x02 /* Enables branch target buffer */ 9872c7879eaSTijl Coosemans #define PCR0_LOOP 0x04 /* Enables loop */ 988c1aa50bfSElyes Haouas #define PCR0_AIS 0x08 /* Enables all instructions stalled to 9892c7879eaSTijl Coosemans serialize pipe. */ 9902c7879eaSTijl Coosemans #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 9912c7879eaSTijl Coosemans #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 9922c7879eaSTijl Coosemans #define PCR0_LSSER 0x80 /* Disable reorder */ 9932c7879eaSTijl Coosemans 9942c7879eaSTijl Coosemans /* Device Identification Registers */ 9952c7879eaSTijl Coosemans #define DIR0 0xfe 9962c7879eaSTijl Coosemans #define DIR1 0xff 9972c7879eaSTijl Coosemans 9982c7879eaSTijl Coosemans /* 9992c7879eaSTijl Coosemans * Machine Check register constants. 10002c7879eaSTijl Coosemans */ 10012c7879eaSTijl Coosemans #define MCG_CAP_COUNT 0x000000ff 10022c7879eaSTijl Coosemans #define MCG_CAP_CTL_P 0x00000100 10032c7879eaSTijl Coosemans #define MCG_CAP_EXT_P 0x00000200 10042c7879eaSTijl Coosemans #define MCG_CAP_CMCI_P 0x00000400 10052c7879eaSTijl Coosemans #define MCG_CAP_TES_P 0x00000800 10062c7879eaSTijl Coosemans #define MCG_CAP_EXT_CNT 0x00ff0000 10072c7879eaSTijl Coosemans #define MCG_CAP_SER_P 0x01000000 10083bdba24cSAlexander Motin #define MCG_CAP_EMC_P 0x02000000 10093bdba24cSAlexander Motin #define MCG_CAP_ELOG_P 0x04000000 10103bdba24cSAlexander Motin #define MCG_CAP_LMCE_P 0x08000000 10112c7879eaSTijl Coosemans #define MCG_STATUS_RIPV 0x00000001 10122c7879eaSTijl Coosemans #define MCG_STATUS_EIPV 0x00000002 10132c7879eaSTijl Coosemans #define MCG_STATUS_MCIP 0x00000004 10143bdba24cSAlexander Motin #define MCG_STATUS_LMCS 0x00000008 /* if MCG_CAP_LMCE_P */ 10152c7879eaSTijl Coosemans #define MCG_CTL_ENABLE 0xffffffffffffffff 10162c7879eaSTijl Coosemans #define MCG_CTL_DISABLE 0x0000000000000000 10172c7879eaSTijl Coosemans #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 10182c7879eaSTijl Coosemans #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 10192c7879eaSTijl Coosemans #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 10202c7879eaSTijl Coosemans #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 10212c7879eaSTijl Coosemans #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 10222c7879eaSTijl Coosemans #define MC_STATUS_MCA_ERROR 0x000000000000ffff 10232c7879eaSTijl Coosemans #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 10242c7879eaSTijl Coosemans #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 10252c7879eaSTijl Coosemans #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 10262c7879eaSTijl Coosemans #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 10272c7879eaSTijl Coosemans #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 10282c7879eaSTijl Coosemans #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 10292c7879eaSTijl Coosemans #define MC_STATUS_PCC 0x0200000000000000 10302c7879eaSTijl Coosemans #define MC_STATUS_ADDRV 0x0400000000000000 10312c7879eaSTijl Coosemans #define MC_STATUS_MISCV 0x0800000000000000 10322c7879eaSTijl Coosemans #define MC_STATUS_EN 0x1000000000000000 10332c7879eaSTijl Coosemans #define MC_STATUS_UC 0x2000000000000000 10342c7879eaSTijl Coosemans #define MC_STATUS_OVER 0x4000000000000000 10352c7879eaSTijl Coosemans #define MC_STATUS_VAL 0x8000000000000000 10362c7879eaSTijl Coosemans #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 10372c7879eaSTijl Coosemans #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 10383bdba24cSAlexander Motin #define MC_MISC_PCIE_RID 0x00000000ffff0000 10393bdba24cSAlexander Motin #define MC_MISC_PCIE_FUNC 0x0000000000070000 10403bdba24cSAlexander Motin #define MC_MISC_PCIE_SLOT 0x0000000000f80000 10413bdba24cSAlexander Motin #define MC_MISC_PCIE_BUS 0x00000000ff000000 10423bdba24cSAlexander Motin #define MC_MISC_PCIE_SEG 0x000000ff00000000 10432c7879eaSTijl Coosemans #define MC_CTL2_THRESHOLD 0x0000000000007fff 10442c7879eaSTijl Coosemans #define MC_CTL2_CMCI_EN 0x0000000040000000 10457abf4604SAndriy Gapon #define MC_AMDNB_BANK 4 1046d63edb4dSConrad Meyer #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */ 1047d63edb4dSConrad Meyer #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */ 1048d63edb4dSConrad Meyer #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */ 1049d63edb4dSConrad Meyer #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */ 1050d63edb4dSConrad Meyer #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */ 1051d63edb4dSConrad Meyer #define MC_MISC_AMD_LVT_SHIFT 52 1052d63edb4dSConrad Meyer #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */ 1053d63edb4dSConrad Meyer #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */ 1054d63edb4dSConrad Meyer #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */ 1055d63edb4dSConrad Meyer #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */ 1056d63edb4dSConrad Meyer #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */ 1057d63edb4dSConrad Meyer #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */ 1058d63edb4dSConrad Meyer #define MC_MISC_AMD_CNT_SHIFT 32 1059d63edb4dSConrad Meyer #define MC_MISC_AMD_CNT_MAX 0xfff 1060d63edb4dSConrad Meyer #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */ 1061d63edb4dSConrad Meyer #define MC_MISC_AMD_PTR_SHIFT 24 10622c7879eaSTijl Coosemans 106318f9bb6fSAndrew Gallatin /* AMD Scalable MCA */ 106418f9bb6fSAndrew Gallatin #define MSR_SMCA_MC0_CTL 0xc0002000 106518f9bb6fSAndrew Gallatin #define MSR_SMCA_MC0_STATUS 0xc0002001 106618f9bb6fSAndrew Gallatin #define MSR_SMCA_MC0_ADDR 0xc0002002 106718f9bb6fSAndrew Gallatin #define MSR_SMCA_MC0_MISC0 0xc0002003 106818f9bb6fSAndrew Gallatin #define MSR_SMCA_MC_CTL(x) (MSR_SMCA_MC0_CTL + 0x10 * (x)) 106918f9bb6fSAndrew Gallatin #define MSR_SMCA_MC_STATUS(x) (MSR_SMCA_MC0_STATUS + 0x10 * (x)) 107018f9bb6fSAndrew Gallatin #define MSR_SMCA_MC_ADDR(x) (MSR_SMCA_MC0_ADDR + 0x10 * (x)) 107118f9bb6fSAndrew Gallatin #define MSR_SMCA_MC_MISC(x) (MSR_SMCA_MC0_MISC0 + 0x10 * (x)) 107218f9bb6fSAndrew Gallatin 10732c7879eaSTijl Coosemans /* 10742c7879eaSTijl Coosemans * The following four 3-byte registers control the non-cacheable regions. 10752c7879eaSTijl Coosemans * These registers must be written as three separate bytes. 10762c7879eaSTijl Coosemans * 10772c7879eaSTijl Coosemans * NCRx+0: A31-A24 of starting address 10782c7879eaSTijl Coosemans * NCRx+1: A23-A16 of starting address 10792c7879eaSTijl Coosemans * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 10802c7879eaSTijl Coosemans * 10812c7879eaSTijl Coosemans * The non-cacheable region's starting address must be aligned to the 10822c7879eaSTijl Coosemans * size indicated by the NCR_SIZE_xx field. 10832c7879eaSTijl Coosemans */ 10842c7879eaSTijl Coosemans #define NCR1 0xc4 10852c7879eaSTijl Coosemans #define NCR2 0xc7 10862c7879eaSTijl Coosemans #define NCR3 0xca 10872c7879eaSTijl Coosemans #define NCR4 0xcd 10882c7879eaSTijl Coosemans 10892c7879eaSTijl Coosemans #define NCR_SIZE_0K 0 10902c7879eaSTijl Coosemans #define NCR_SIZE_4K 1 10912c7879eaSTijl Coosemans #define NCR_SIZE_8K 2 10922c7879eaSTijl Coosemans #define NCR_SIZE_16K 3 10932c7879eaSTijl Coosemans #define NCR_SIZE_32K 4 10942c7879eaSTijl Coosemans #define NCR_SIZE_64K 5 10952c7879eaSTijl Coosemans #define NCR_SIZE_128K 6 10962c7879eaSTijl Coosemans #define NCR_SIZE_256K 7 10972c7879eaSTijl Coosemans #define NCR_SIZE_512K 8 10982c7879eaSTijl Coosemans #define NCR_SIZE_1M 9 10992c7879eaSTijl Coosemans #define NCR_SIZE_2M 10 11002c7879eaSTijl Coosemans #define NCR_SIZE_4M 11 11012c7879eaSTijl Coosemans #define NCR_SIZE_8M 12 11022c7879eaSTijl Coosemans #define NCR_SIZE_16M 13 11032c7879eaSTijl Coosemans #define NCR_SIZE_32M 14 11042c7879eaSTijl Coosemans #define NCR_SIZE_4G 15 11052c7879eaSTijl Coosemans 11062c7879eaSTijl Coosemans /* 11072c7879eaSTijl Coosemans * The address region registers are used to specify the location and 11082c7879eaSTijl Coosemans * size for the eight address regions. 11092c7879eaSTijl Coosemans * 11102c7879eaSTijl Coosemans * ARRx + 0: A31-A24 of start address 11112c7879eaSTijl Coosemans * ARRx + 1: A23-A16 of start address 11122c7879eaSTijl Coosemans * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 11132c7879eaSTijl Coosemans */ 11142c7879eaSTijl Coosemans #define ARR0 0xc4 11152c7879eaSTijl Coosemans #define ARR1 0xc7 11162c7879eaSTijl Coosemans #define ARR2 0xca 11172c7879eaSTijl Coosemans #define ARR3 0xcd 11182c7879eaSTijl Coosemans #define ARR4 0xd0 11192c7879eaSTijl Coosemans #define ARR5 0xd3 11202c7879eaSTijl Coosemans #define ARR6 0xd6 11212c7879eaSTijl Coosemans #define ARR7 0xd9 11222c7879eaSTijl Coosemans 11232c7879eaSTijl Coosemans #define ARR_SIZE_0K 0 11242c7879eaSTijl Coosemans #define ARR_SIZE_4K 1 11252c7879eaSTijl Coosemans #define ARR_SIZE_8K 2 11262c7879eaSTijl Coosemans #define ARR_SIZE_16K 3 11272c7879eaSTijl Coosemans #define ARR_SIZE_32K 4 11282c7879eaSTijl Coosemans #define ARR_SIZE_64K 5 11292c7879eaSTijl Coosemans #define ARR_SIZE_128K 6 11302c7879eaSTijl Coosemans #define ARR_SIZE_256K 7 11312c7879eaSTijl Coosemans #define ARR_SIZE_512K 8 11322c7879eaSTijl Coosemans #define ARR_SIZE_1M 9 11332c7879eaSTijl Coosemans #define ARR_SIZE_2M 10 11342c7879eaSTijl Coosemans #define ARR_SIZE_4M 11 11352c7879eaSTijl Coosemans #define ARR_SIZE_8M 12 11362c7879eaSTijl Coosemans #define ARR_SIZE_16M 13 11372c7879eaSTijl Coosemans #define ARR_SIZE_32M 14 11382c7879eaSTijl Coosemans #define ARR_SIZE_4G 15 11392c7879eaSTijl Coosemans 11402c7879eaSTijl Coosemans /* 11412c7879eaSTijl Coosemans * The region control registers specify the attributes associated with 1142c1aa50bfSElyes Haouas * the ARRx address regions. 11432c7879eaSTijl Coosemans */ 11442c7879eaSTijl Coosemans #define RCR0 0xdc 11452c7879eaSTijl Coosemans #define RCR1 0xdd 11462c7879eaSTijl Coosemans #define RCR2 0xde 11472c7879eaSTijl Coosemans #define RCR3 0xdf 11482c7879eaSTijl Coosemans #define RCR4 0xe0 11492c7879eaSTijl Coosemans #define RCR5 0xe1 11502c7879eaSTijl Coosemans #define RCR6 0xe2 11512c7879eaSTijl Coosemans #define RCR7 0xe3 11522c7879eaSTijl Coosemans 11532c7879eaSTijl Coosemans #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 11542c7879eaSTijl Coosemans #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 11552c7879eaSTijl Coosemans #define RCR_WWO 0x02 /* Weak write ordering. */ 11562c7879eaSTijl Coosemans #define RCR_WL 0x04 /* Weak locking. */ 11572c7879eaSTijl Coosemans #define RCR_WG 0x08 /* Write gathering. */ 11582c7879eaSTijl Coosemans #define RCR_WT 0x10 /* Write-through. */ 11592c7879eaSTijl Coosemans #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 11602c7879eaSTijl Coosemans 11612c7879eaSTijl Coosemans /* AMD Write Allocate Top-Of-Memory and Control Register */ 11622c7879eaSTijl Coosemans #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 11632c7879eaSTijl Coosemans #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 11642c7879eaSTijl Coosemans #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 11652c7879eaSTijl Coosemans 11662c7879eaSTijl Coosemans /* AMD64 MSR's */ 11672c7879eaSTijl Coosemans #define MSR_EFER 0xc0000080 /* extended features */ 11682c7879eaSTijl Coosemans #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 11692c7879eaSTijl Coosemans #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 11702c7879eaSTijl Coosemans #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 11712c7879eaSTijl Coosemans #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 11722c7879eaSTijl Coosemans #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 11732c7879eaSTijl Coosemans #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 11742c7879eaSTijl Coosemans #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 11757e0a345bSKonstantin Belousov #define MSR_TSC_AUX 0xc0000103 11762c7879eaSTijl Coosemans #define MSR_PERFEVSEL0 0xc0010000 11772c7879eaSTijl Coosemans #define MSR_PERFEVSEL1 0xc0010001 11782c7879eaSTijl Coosemans #define MSR_PERFEVSEL2 0xc0010002 11792c7879eaSTijl Coosemans #define MSR_PERFEVSEL3 0xc0010003 1180b35ac068STijl Coosemans #define MSR_K7_PERFCTR0 0xc0010004 1181b35ac068STijl Coosemans #define MSR_K7_PERFCTR1 0xc0010005 1182b35ac068STijl Coosemans #define MSR_K7_PERFCTR2 0xc0010006 1183b35ac068STijl Coosemans #define MSR_K7_PERFCTR3 0xc0010007 11842c7879eaSTijl Coosemans #define MSR_SYSCFG 0xc0010010 11852c7879eaSTijl Coosemans #define MSR_HWCR 0xc0010015 11862c7879eaSTijl Coosemans #define MSR_IORRBASE0 0xc0010016 11872c7879eaSTijl Coosemans #define MSR_IORRMASK0 0xc0010017 11882c7879eaSTijl Coosemans #define MSR_IORRBASE1 0xc0010018 11892c7879eaSTijl Coosemans #define MSR_IORRMASK1 0xc0010019 11902c7879eaSTijl Coosemans #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 11912c7879eaSTijl Coosemans #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 1192e011dc96SNeel Natu #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ 1193fe15b854SKonstantin Belousov #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 1194fe15b854SKonstantin Belousov #define MSR_MC0_CTL_MASK 0xc0010044 1195d3ba71b2SKonstantin Belousov #define MSR_AMDK8_IPM 0xc0010055 1196e011dc96SNeel Natu #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ 1197e011dc96SNeel Natu #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ 1198e011dc96SNeel Natu #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ 1199e011dc96SNeel Natu #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ 1200e011dc96SNeel Natu #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ 1201e011dc96SNeel Natu #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ 1202e011dc96SNeel Natu #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ 1203e011dc96SNeel Natu #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ 1204300c34e4SKonstantin Belousov #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */ 1205fe15b854SKonstantin Belousov #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ 1206bebcdc00SJohn Baldwin #define MSR_LS_CFG 0xc0011020 1207fe15b854SKonstantin Belousov #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ 1208d8dc46f6SJohn Baldwin #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ 1209e011dc96SNeel Natu 1210125bbadfSOlivier Certner /* MSR_AMDK8_IPM */ 1211125bbadfSOlivier Certner #define AMDK8_SMIONCMPHALT (1ULL << 27) 1212125bbadfSOlivier Certner #define AMDK8_C1EONCMPHALT (1ULL << 28) 1213125bbadfSOlivier Certner 1214e011dc96SNeel Natu /* MSR_VM_CR related */ 1215e011dc96SNeel Natu #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ 12162c7879eaSTijl Coosemans 1217125bbadfSOlivier Certner /* MSR_DE_CFG */ 1218125bbadfSOlivier Certner #define DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT 0x1 1219125bbadfSOlivier Certner #define DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT 0x2000 1220ebaea1bcSOlivier Certner #define DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 0x200 1221d3ba71b2SKonstantin Belousov 12222c7879eaSTijl Coosemans /* VIA ACE crypto featureset: for via_feature_rng */ 12232c7879eaSTijl Coosemans #define VIA_HAS_RNG 1 /* cpu has RNG */ 12242c7879eaSTijl Coosemans 12252c7879eaSTijl Coosemans /* VIA ACE crypto featureset: for via_feature_xcrypt */ 12262c7879eaSTijl Coosemans #define VIA_HAS_AES 1 /* cpu has AES */ 12272c7879eaSTijl Coosemans #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 12282c7879eaSTijl Coosemans #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 12292c7879eaSTijl Coosemans #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 12302c7879eaSTijl Coosemans 12312c7879eaSTijl Coosemans /* Centaur Extended Feature flags */ 12322c7879eaSTijl Coosemans #define VIA_CPUID_HAS_RNG 0x000004 12332c7879eaSTijl Coosemans #define VIA_CPUID_DO_RNG 0x000008 12342c7879eaSTijl Coosemans #define VIA_CPUID_HAS_ACE 0x000040 12352c7879eaSTijl Coosemans #define VIA_CPUID_DO_ACE 0x000080 12362c7879eaSTijl Coosemans #define VIA_CPUID_HAS_ACE2 0x000100 12372c7879eaSTijl Coosemans #define VIA_CPUID_DO_ACE2 0x000200 12382c7879eaSTijl Coosemans #define VIA_CPUID_HAS_PHE 0x000400 12392c7879eaSTijl Coosemans #define VIA_CPUID_DO_PHE 0x000800 12402c7879eaSTijl Coosemans #define VIA_CPUID_HAS_PMM 0x001000 12412c7879eaSTijl Coosemans #define VIA_CPUID_DO_PMM 0x002000 12422c7879eaSTijl Coosemans 12432c7879eaSTijl Coosemans /* VIA ACE xcrypt-* instruction context control options */ 12442c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 12452c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_ALG_M 0x00000070 12462c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 12472c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 12482c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 12492c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 12502c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_NORMAL 0x00000000 12512c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 12522c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 12532c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 12542c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 12552c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 12562c7879eaSTijl Coosemans #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 12572c7879eaSTijl Coosemans 12582c7879eaSTijl Coosemans #endif /* !_MACHINE_SPECIALREG_H_ */ 1259