1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef __X86_PCI_CFGREG_H__ 31 #define __X86_PCI_CFGREG_H__ 32 33 #define CONF1_ADDR_PORT 0x0cf8 34 #define CONF1_DATA_PORT 0x0cfc 35 36 #define CONF1_ENABLE 0x80000000ul 37 #define CONF1_ENABLE_CHK 0x80000000ul 38 #define CONF1_ENABLE_MSK 0x7f000000ul 39 #define CONF1_ENABLE_CHK1 0xff000001ul 40 #define CONF1_ENABLE_MSK1 0x80000001ul 41 #define CONF1_ENABLE_RES1 0x80000000ul 42 43 #define CONF2_ENABLE_PORT 0x0cf8 44 #define CONF2_FORWARD_PORT 0x0cfa 45 46 #define CONF2_ENABLE_CHK 0x0e 47 #define CONF2_ENABLE_RES 0x0e 48 49 enum { 50 CFGMECH_NONE = 0, 51 CFGMECH_1, 52 CFGMECH_2, 53 CFGMECH_PCIE, 54 }; 55 56 extern int cfgmech; 57 58 rman_res_t hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count); 59 int pcie_cfgregopen(uint64_t base, uint16_t domain, uint8_t minbus, uint8_t maxbus); 60 int pci_cfgregopen(void); 61 u_int32_t pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes); 62 void pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, u_int32_t data, int bytes); 63 #ifdef __HAVE_PIR 64 void pci_pir_open(void); 65 int pci_pir_probe(int bus, int require_parse); 66 int pci_pir_route_interrupt(int bus, int device, int func, int pin); 67 #endif 68 69 #endif /* !__X86_PCI_CFGREG_H__ */ 70