1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _X86_APICVAR_H_ 32 #define _X86_APICVAR_H_ 33 34 /* 35 * Local && I/O APIC variable definitions. 36 */ 37 38 /* 39 * Layout of local APIC interrupt vectors: 40 * 41 * 0xff (255) +-------------+ 42 * | | 15 (Spurious / IPIs / Local Interrupts) 43 * 0xf0 (240) +-------------+ 44 * | | 14 (I/O Interrupts / Timer) 45 * 0xe0 (224) +-------------+ 46 * | | 13 (I/O Interrupts) 47 * 0xd0 (208) +-------------+ 48 * | | 12 (I/O Interrupts) 49 * 0xc0 (192) +-------------+ 50 * | | 11 (I/O Interrupts) 51 * 0xb0 (176) +-------------+ 52 * | | 10 (I/O Interrupts) 53 * 0xa0 (160) +-------------+ 54 * | | 9 (I/O Interrupts) 55 * 0x90 (144) +-------------+ 56 * | | 8 (I/O Interrupts / System Calls) 57 * 0x80 (128) +-------------+ 58 * | | 7 (I/O Interrupts) 59 * 0x70 (112) +-------------+ 60 * | | 6 (I/O Interrupts) 61 * 0x60 (96) +-------------+ 62 * | | 5 (I/O Interrupts) 63 * 0x50 (80) +-------------+ 64 * | | 4 (I/O Interrupts) 65 * 0x40 (64) +-------------+ 66 * | | 3 (I/O Interrupts) 67 * 0x30 (48) +-------------+ 68 * | | 2 (ATPIC Interrupts) 69 * 0x20 (32) +-------------+ 70 * | | 1 (Exceptions, traps, faults, etc.) 71 * 0x10 (16) +-------------+ 72 * | | 0 (Exceptions, traps, faults, etc.) 73 * 0x00 (0) +-------------+ 74 * 75 * Note: 0x80 needs to be handled specially and not allocated to an 76 * I/O device! 77 */ 78 79 #define xAPIC_MAX_APIC_ID 0xfe 80 #define xAPIC_ID_ALL 0xff 81 #define MAX_APIC_ID 0x200 82 #define APIC_ID_ALL 0xffffffff 83 84 #define IOAPIC_MAX_ID xAPIC_MAX_APIC_ID 85 86 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 87 #define APIC_IO_INTS (IDT_IO_INTS + 16) 88 #define APIC_NUM_IOINTS 191 89 90 /* The timer interrupt is used for clock handling and drives hardclock, etc. */ 91 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 92 93 /* 94 ********************* !!! WARNING !!! ****************************** 95 * Each local apic has an interrupt receive fifo that is two entries deep 96 * for each interrupt priority class (higher 4 bits of interrupt vector). 97 * Once the fifo is full the APIC can no longer receive interrupts for this 98 * class and sending IPIs from other CPUs will be blocked. 99 * To avoid deadlocks there should be no more than two IPI interrupts 100 * pending at the same time. 101 * Currently this is guaranteed by dividing the IPIs in two groups that have 102 * each at most one IPI interrupt pending. The first group is protected by the 103 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 104 * at a time) The second group uses a single interrupt and a bitmap to avoid 105 * redundant IPI interrupts. 106 */ 107 108 /* Interrupts for local APIC LVT entries other than the timer. */ 109 #define APIC_LOCAL_INTS 240 110 #define APIC_ERROR_INT APIC_LOCAL_INTS 111 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 112 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 113 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 114 115 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 116 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ 117 #define IPI_INVLPG (APIC_IPI_INTS + 2) 118 #define IPI_INVLRNG (APIC_IPI_INTS + 3) 119 #define IPI_INVLCACHE (APIC_IPI_INTS + 4) 120 /* Vector to handle bitmap based IPIs */ 121 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5) 122 123 /* IPIs handled by IPI_BITMAP_VECTOR */ 124 #define IPI_AST 0 /* Generate software trap. */ 125 #define IPI_PREEMPT 1 126 #define IPI_HARDCLOCK 2 127 #define IPI_BITMAP_LAST IPI_HARDCLOCK 128 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 129 130 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */ 131 #define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */ 132 #ifdef __i386__ 133 #define IPI_LAZYPMAP (APIC_IPI_INTS + 8) /* Lazy pmap release. */ 134 #define IPI_DYN_FIRST (APIC_IPI_INTS + 9) 135 #else 136 #define IPI_DYN_FIRST (APIC_IPI_INTS + 8) 137 #endif 138 #define IPI_DYN_LAST (253) /* IPIs allocated at runtime */ 139 140 /* 141 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since 142 * it is delivered using an NMI anyways. 143 */ 144 #define IPI_NMI_FIRST 254 145 #define IPI_TRACE 254 /* Interrupt for tracing. */ 146 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */ 147 148 /* 149 * The spurious interrupt can share the priority class with the IPIs since 150 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 151 */ 152 #define APIC_SPURIOUS_INT 255 153 154 #ifndef LOCORE 155 156 #define APIC_IPI_DEST_SELF -1 157 #define APIC_IPI_DEST_ALL -2 158 #define APIC_IPI_DEST_OTHERS -3 159 160 #define APIC_BUS_UNKNOWN -1 161 #define APIC_BUS_ISA 0 162 #define APIC_BUS_EISA 1 163 #define APIC_BUS_PCI 2 164 #define APIC_BUS_MAX APIC_BUS_PCI 165 166 #define IRQ_EXTINT (NUM_IO_INTS + 1) 167 #define IRQ_NMI (NUM_IO_INTS + 2) 168 #define IRQ_SMI (NUM_IO_INTS + 3) 169 #define IRQ_DISABLED (NUM_IO_INTS + 4) 170 171 /* 172 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including 173 * CPU's and I/O APIC's. 174 */ 175 struct apic_enumerator { 176 const char *apic_name; 177 int (*apic_probe)(void); 178 int (*apic_probe_cpus)(void); 179 int (*apic_setup_local)(void); 180 int (*apic_setup_io)(void); 181 SLIST_ENTRY(apic_enumerator) apic_next; 182 }; 183 184 inthand_t 185 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 186 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 187 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 188 IDTVEC(spuriousint), IDTVEC(timerint); 189 190 extern vm_paddr_t lapic_paddr; 191 extern int *apic_cpuids; 192 193 void apic_register_enumerator(struct apic_enumerator *enumerator); 194 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 195 int ioapic_disable_pin(void *cookie, u_int pin); 196 int ioapic_get_vector(void *cookie, u_int pin); 197 void ioapic_register(void *cookie); 198 int ioapic_remap_vector(void *cookie, u_int pin, int vector); 199 int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 200 int ioapic_set_extint(void *cookie, u_int pin); 201 int ioapic_set_nmi(void *cookie, u_int pin); 202 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 203 int ioapic_set_triggermode(void *cookie, u_int pin, 204 enum intr_trigger trigger); 205 int ioapic_set_smi(void *cookie, u_int pin); 206 207 /* 208 * Struct containing pointers to APIC functions whose 209 * implementation is run time selectable. 210 */ 211 struct apic_ops { 212 void (*create)(u_int, int); 213 void (*init)(vm_paddr_t); 214 void (*xapic_mode)(void); 215 bool (*is_x2apic)(void); 216 void (*setup)(int); 217 void (*dump)(const char *); 218 void (*disable)(void); 219 void (*eoi)(void); 220 int (*id)(void); 221 int (*intr_pending)(u_int); 222 void (*set_logical_id)(u_int, u_int, u_int); 223 u_int (*cpuid)(u_int); 224 225 /* Vectors */ 226 u_int (*alloc_vector)(u_int, u_int); 227 u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int); 228 void (*enable_vector)(u_int, u_int); 229 void (*disable_vector)(u_int, u_int); 230 void (*free_vector)(u_int, u_int, u_int); 231 232 233 /* PMC */ 234 int (*enable_pmc)(void); 235 void (*disable_pmc)(void); 236 void (*reenable_pmc)(void); 237 238 /* CMC */ 239 void (*enable_cmc)(void); 240 241 /* AMD ELVT */ 242 int (*enable_mca_elvt)(void); 243 244 /* IPI */ 245 void (*ipi_raw)(register_t, u_int); 246 void (*ipi_vectored)(u_int, int); 247 int (*ipi_wait)(int); 248 int (*ipi_alloc)(inthand_t *ipifunc); 249 void (*ipi_free)(int vector); 250 251 /* LVT */ 252 int (*set_lvt_mask)(u_int, u_int, u_char); 253 int (*set_lvt_mode)(u_int, u_int, u_int32_t); 254 int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity); 255 int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger); 256 }; 257 258 extern struct apic_ops apic_ops; 259 260 static inline void 261 lapic_create(u_int apic_id, int boot_cpu) 262 { 263 264 apic_ops.create(apic_id, boot_cpu); 265 } 266 267 static inline void 268 lapic_init(vm_paddr_t addr) 269 { 270 271 apic_ops.init(addr); 272 } 273 274 static inline void 275 lapic_xapic_mode(void) 276 { 277 278 apic_ops.xapic_mode(); 279 } 280 281 static inline bool 282 lapic_is_x2apic(void) 283 { 284 285 return (apic_ops.is_x2apic()); 286 } 287 288 static inline void 289 lapic_setup(int boot) 290 { 291 292 apic_ops.setup(boot); 293 } 294 295 static inline void 296 lapic_dump(const char *str) 297 { 298 299 apic_ops.dump(str); 300 } 301 302 static inline void 303 lapic_disable(void) 304 { 305 306 apic_ops.disable(); 307 } 308 309 static inline void 310 lapic_eoi(void) 311 { 312 313 apic_ops.eoi(); 314 } 315 316 static inline int 317 lapic_id(void) 318 { 319 320 return (apic_ops.id()); 321 } 322 323 static inline int 324 lapic_intr_pending(u_int vector) 325 { 326 327 return (apic_ops.intr_pending(vector)); 328 } 329 330 /* XXX: UNUSED */ 331 static inline void 332 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 333 { 334 335 apic_ops.set_logical_id(apic_id, cluster, cluster_id); 336 } 337 338 static inline u_int 339 apic_cpuid(u_int apic_id) 340 { 341 342 return (apic_ops.cpuid(apic_id)); 343 } 344 345 static inline u_int 346 apic_alloc_vector(u_int apic_id, u_int irq) 347 { 348 349 return (apic_ops.alloc_vector(apic_id, irq)); 350 } 351 352 static inline u_int 353 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 354 { 355 356 return (apic_ops.alloc_vectors(apic_id, irqs, count, align)); 357 } 358 359 static inline void 360 apic_enable_vector(u_int apic_id, u_int vector) 361 { 362 363 apic_ops.enable_vector(apic_id, vector); 364 } 365 366 static inline void 367 apic_disable_vector(u_int apic_id, u_int vector) 368 { 369 370 apic_ops.disable_vector(apic_id, vector); 371 } 372 373 static inline void 374 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 375 { 376 377 apic_ops.free_vector(apic_id, vector, irq); 378 } 379 380 static inline int 381 lapic_enable_pmc(void) 382 { 383 384 return (apic_ops.enable_pmc()); 385 } 386 387 static inline void 388 lapic_disable_pmc(void) 389 { 390 391 apic_ops.disable_pmc(); 392 } 393 394 static inline void 395 lapic_reenable_pmc(void) 396 { 397 398 apic_ops.reenable_pmc(); 399 } 400 401 static inline void 402 lapic_enable_cmc(void) 403 { 404 405 apic_ops.enable_cmc(); 406 } 407 408 static inline int 409 lapic_enable_mca_elvt(void) 410 { 411 412 return (apic_ops.enable_mca_elvt()); 413 } 414 415 static inline void 416 lapic_ipi_raw(register_t icrlo, u_int dest) 417 { 418 419 apic_ops.ipi_raw(icrlo, dest); 420 } 421 422 static inline void 423 lapic_ipi_vectored(u_int vector, int dest) 424 { 425 426 apic_ops.ipi_vectored(vector, dest); 427 } 428 429 static inline int 430 lapic_ipi_wait(int delay) 431 { 432 433 return (apic_ops.ipi_wait(delay)); 434 } 435 436 static inline int 437 lapic_ipi_alloc(inthand_t *ipifunc) 438 { 439 440 return (apic_ops.ipi_alloc(ipifunc)); 441 } 442 443 static inline void 444 lapic_ipi_free(int vector) 445 { 446 447 return (apic_ops.ipi_free(vector)); 448 } 449 450 static inline int 451 lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked) 452 { 453 454 return (apic_ops.set_lvt_mask(apic_id, lvt, masked)); 455 } 456 457 static inline int 458 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode) 459 { 460 461 return (apic_ops.set_lvt_mode(apic_id, lvt, mode)); 462 } 463 464 static inline int 465 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol) 466 { 467 468 return (apic_ops.set_lvt_polarity(apic_id, lvt, pol)); 469 } 470 471 static inline int 472 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger) 473 { 474 475 return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger)); 476 } 477 478 void lapic_handle_cmc(void); 479 void lapic_handle_error(void); 480 void lapic_handle_intr(int vector, struct trapframe *frame); 481 void lapic_handle_timer(struct trapframe *frame); 482 483 int ioapic_get_rid(u_int apic_id, uint16_t *ridp); 484 485 extern int x2apic_mode; 486 extern int lapic_eoi_suppression; 487 488 #ifdef _SYS_SYSCTL_H_ 489 SYSCTL_DECL(_hw_apic); 490 #endif 491 492 #endif /* !LOCORE */ 493 #endif /* _X86_APICVAR_H_ */ 494