1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _X86_APICVAR_H_ 30 #define _X86_APICVAR_H_ 31 32 /* 33 * Local && I/O APIC variable definitions. 34 */ 35 36 /* 37 * Layout of local APIC interrupt vectors: 38 * 39 * 0xff (255) +-------------+ 40 * | | 15 (Spurious / IPIs / Local Interrupts) 41 * 0xf0 (240) +-------------+ 42 * | | 14 (I/O Interrupts / Timer) 43 * 0xe0 (224) +-------------+ 44 * | | 13 (I/O Interrupts) 45 * 0xd0 (208) +-------------+ 46 * | | 12 (I/O Interrupts) 47 * 0xc0 (192) +-------------+ 48 * | | 11 (I/O Interrupts) 49 * 0xb0 (176) +-------------+ 50 * | | 10 (I/O Interrupts) 51 * 0xa0 (160) +-------------+ 52 * | | 9 (I/O Interrupts) 53 * 0x90 (144) +-------------+ 54 * | | 8 (I/O Interrupts / System Calls) 55 * 0x80 (128) +-------------+ 56 * | | 7 (I/O Interrupts) 57 * 0x70 (112) +-------------+ 58 * | | 6 (I/O Interrupts) 59 * 0x60 (96) +-------------+ 60 * | | 5 (I/O Interrupts) 61 * 0x50 (80) +-------------+ 62 * | | 4 (I/O Interrupts) 63 * 0x40 (64) +-------------+ 64 * | | 3 (I/O Interrupts) 65 * 0x30 (48) +-------------+ 66 * | | 2 (ATPIC Interrupts) 67 * 0x20 (32) +-------------+ 68 * | | 1 (Exceptions, traps, faults, etc.) 69 * 0x10 (16) +-------------+ 70 * | | 0 (Exceptions, traps, faults, etc.) 71 * 0x00 (0) +-------------+ 72 * 73 * Note: 0x80 needs to be handled specially and not allocated to an 74 * I/O device! 75 */ 76 77 #define xAPIC_MAX_APIC_ID 0xfe 78 #define xAPIC_ID_ALL 0xff 79 #define MAX_APIC_ID 0x200 80 #define APIC_ID_ALL 0xffffffff 81 82 #define IOAPIC_MAX_ID xAPIC_MAX_APIC_ID 83 84 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 85 #define APIC_IO_INTS (IDT_IO_INTS + 16) 86 #define APIC_NUM_IOINTS 191 87 88 /* The timer interrupt is used for clock handling and drives hardclock, etc. */ 89 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 90 91 /* 92 ********************* !!! WARNING !!! ****************************** 93 * Each local apic has an interrupt receive fifo that is two entries deep 94 * for each interrupt priority class (higher 4 bits of interrupt vector). 95 * Once the fifo is full the APIC can no longer receive interrupts for this 96 * class and sending IPIs from other CPUs will be blocked. 97 * To avoid deadlocks there should be no more than two IPI interrupts 98 * pending at the same time. 99 * Currently this is guaranteed by dividing the IPIs in two groups that have 100 * each at most one IPI interrupt pending. The first group is protected by the 101 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 102 * at a time) The second group uses a single interrupt and a bitmap to avoid 103 * redundant IPI interrupts. 104 */ 105 106 /* Interrupts for local APIC LVT entries other than the timer. */ 107 #define APIC_LOCAL_INTS 240 108 #define APIC_ERROR_INT APIC_LOCAL_INTS 109 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 110 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 111 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 112 113 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 114 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ 115 #define IPI_INVLPG (APIC_IPI_INTS + 2) 116 #define IPI_INVLRNG (APIC_IPI_INTS + 3) 117 #define IPI_INVLCACHE (APIC_IPI_INTS + 4) 118 /* Vector to handle bitmap based IPIs */ 119 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5) 120 121 /* IPIs handled by IPI_BITMAP_VECTOR */ 122 #define IPI_AST 0 /* Generate software trap. */ 123 #define IPI_PREEMPT 1 124 #define IPI_HARDCLOCK 2 125 #define IPI_BITMAP_LAST IPI_HARDCLOCK 126 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 127 128 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */ 129 #define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */ 130 #ifdef __i386__ 131 #define IPI_LAZYPMAP (APIC_IPI_INTS + 8) /* Lazy pmap release. */ 132 #define IPI_DYN_FIRST (APIC_IPI_INTS + 9) 133 #else 134 #define IPI_DYN_FIRST (APIC_IPI_INTS + 8) 135 #endif 136 #define IPI_DYN_LAST (253) /* IPIs allocated at runtime */ 137 138 /* 139 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since 140 * it is delivered using an NMI anyways. 141 */ 142 #define IPI_NMI_FIRST 254 143 #define IPI_TRACE 254 /* Interrupt for tracing. */ 144 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */ 145 146 /* 147 * The spurious interrupt can share the priority class with the IPIs since 148 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 149 */ 150 #define APIC_SPURIOUS_INT 255 151 152 #ifndef LOCORE 153 154 #define APIC_IPI_DEST_SELF -1 155 #define APIC_IPI_DEST_ALL -2 156 #define APIC_IPI_DEST_OTHERS -3 157 158 #define APIC_BUS_UNKNOWN -1 159 #define APIC_BUS_ISA 0 160 #define APIC_BUS_EISA 1 161 #define APIC_BUS_PCI 2 162 #define APIC_BUS_MAX APIC_BUS_PCI 163 164 #define IRQ_EXTINT (NUM_IO_INTS + 1) 165 #define IRQ_NMI (NUM_IO_INTS + 2) 166 #define IRQ_SMI (NUM_IO_INTS + 3) 167 #define IRQ_DISABLED (NUM_IO_INTS + 4) 168 169 /* 170 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including 171 * CPU's and I/O APIC's. 172 */ 173 struct apic_enumerator { 174 const char *apic_name; 175 int (*apic_probe)(void); 176 int (*apic_probe_cpus)(void); 177 int (*apic_setup_local)(void); 178 int (*apic_setup_io)(void); 179 SLIST_ENTRY(apic_enumerator) apic_next; 180 }; 181 182 inthand_t 183 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 184 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 185 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 186 IDTVEC(spuriousint), IDTVEC(timerint); 187 188 extern vm_paddr_t lapic_paddr; 189 extern int *apic_cpuids; 190 191 void apic_register_enumerator(struct apic_enumerator *enumerator); 192 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 193 int ioapic_disable_pin(void *cookie, u_int pin); 194 int ioapic_get_vector(void *cookie, u_int pin); 195 void ioapic_register(void *cookie); 196 int ioapic_remap_vector(void *cookie, u_int pin, int vector); 197 int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 198 int ioapic_set_extint(void *cookie, u_int pin); 199 int ioapic_set_nmi(void *cookie, u_int pin); 200 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 201 int ioapic_set_triggermode(void *cookie, u_int pin, 202 enum intr_trigger trigger); 203 int ioapic_set_smi(void *cookie, u_int pin); 204 205 /* 206 * Struct containing pointers to APIC functions whose 207 * implementation is run time selectable. 208 */ 209 struct apic_ops { 210 void (*create)(u_int, int); 211 void (*init)(vm_paddr_t); 212 void (*xapic_mode)(void); 213 bool (*is_x2apic)(void); 214 void (*setup)(int); 215 void (*dump)(const char *); 216 void (*disable)(void); 217 void (*eoi)(void); 218 int (*id)(void); 219 int (*intr_pending)(u_int); 220 void (*set_logical_id)(u_int, u_int, u_int); 221 u_int (*cpuid)(u_int); 222 223 /* Vectors */ 224 u_int (*alloc_vector)(u_int, u_int); 225 u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int); 226 void (*enable_vector)(u_int, u_int); 227 void (*disable_vector)(u_int, u_int); 228 void (*free_vector)(u_int, u_int, u_int); 229 230 231 /* PMC */ 232 int (*enable_pmc)(void); 233 void (*disable_pmc)(void); 234 void (*reenable_pmc)(void); 235 236 /* CMC */ 237 void (*enable_cmc)(void); 238 239 /* AMD ELVT */ 240 int (*enable_mca_elvt)(void); 241 242 /* IPI */ 243 void (*ipi_raw)(register_t, u_int); 244 void (*ipi_vectored)(u_int, int); 245 int (*ipi_wait)(int); 246 int (*ipi_alloc)(inthand_t *ipifunc); 247 void (*ipi_free)(int vector); 248 249 /* LVT */ 250 int (*set_lvt_mask)(u_int, u_int, u_char); 251 int (*set_lvt_mode)(u_int, u_int, u_int32_t); 252 int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity); 253 int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger); 254 }; 255 256 extern struct apic_ops apic_ops; 257 258 static inline void 259 lapic_create(u_int apic_id, int boot_cpu) 260 { 261 262 apic_ops.create(apic_id, boot_cpu); 263 } 264 265 static inline void 266 lapic_init(vm_paddr_t addr) 267 { 268 269 apic_ops.init(addr); 270 } 271 272 static inline void 273 lapic_xapic_mode(void) 274 { 275 276 apic_ops.xapic_mode(); 277 } 278 279 static inline bool 280 lapic_is_x2apic(void) 281 { 282 283 return (apic_ops.is_x2apic()); 284 } 285 286 static inline void 287 lapic_setup(int boot) 288 { 289 290 apic_ops.setup(boot); 291 } 292 293 static inline void 294 lapic_dump(const char *str) 295 { 296 297 apic_ops.dump(str); 298 } 299 300 static inline void 301 lapic_disable(void) 302 { 303 304 apic_ops.disable(); 305 } 306 307 static inline void 308 lapic_eoi(void) 309 { 310 311 apic_ops.eoi(); 312 } 313 314 static inline int 315 lapic_id(void) 316 { 317 318 return (apic_ops.id()); 319 } 320 321 static inline int 322 lapic_intr_pending(u_int vector) 323 { 324 325 return (apic_ops.intr_pending(vector)); 326 } 327 328 /* XXX: UNUSED */ 329 static inline void 330 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 331 { 332 333 apic_ops.set_logical_id(apic_id, cluster, cluster_id); 334 } 335 336 static inline u_int 337 apic_cpuid(u_int apic_id) 338 { 339 340 return (apic_ops.cpuid(apic_id)); 341 } 342 343 static inline u_int 344 apic_alloc_vector(u_int apic_id, u_int irq) 345 { 346 347 return (apic_ops.alloc_vector(apic_id, irq)); 348 } 349 350 static inline u_int 351 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 352 { 353 354 return (apic_ops.alloc_vectors(apic_id, irqs, count, align)); 355 } 356 357 static inline void 358 apic_enable_vector(u_int apic_id, u_int vector) 359 { 360 361 apic_ops.enable_vector(apic_id, vector); 362 } 363 364 static inline void 365 apic_disable_vector(u_int apic_id, u_int vector) 366 { 367 368 apic_ops.disable_vector(apic_id, vector); 369 } 370 371 static inline void 372 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 373 { 374 375 apic_ops.free_vector(apic_id, vector, irq); 376 } 377 378 static inline int 379 lapic_enable_pmc(void) 380 { 381 382 return (apic_ops.enable_pmc()); 383 } 384 385 static inline void 386 lapic_disable_pmc(void) 387 { 388 389 apic_ops.disable_pmc(); 390 } 391 392 static inline void 393 lapic_reenable_pmc(void) 394 { 395 396 apic_ops.reenable_pmc(); 397 } 398 399 static inline void 400 lapic_enable_cmc(void) 401 { 402 403 apic_ops.enable_cmc(); 404 } 405 406 static inline int 407 lapic_enable_mca_elvt(void) 408 { 409 410 return (apic_ops.enable_mca_elvt()); 411 } 412 413 static inline void 414 lapic_ipi_raw(register_t icrlo, u_int dest) 415 { 416 417 apic_ops.ipi_raw(icrlo, dest); 418 } 419 420 static inline void 421 lapic_ipi_vectored(u_int vector, int dest) 422 { 423 424 apic_ops.ipi_vectored(vector, dest); 425 } 426 427 static inline int 428 lapic_ipi_wait(int delay) 429 { 430 431 return (apic_ops.ipi_wait(delay)); 432 } 433 434 static inline int 435 lapic_ipi_alloc(inthand_t *ipifunc) 436 { 437 438 return (apic_ops.ipi_alloc(ipifunc)); 439 } 440 441 static inline void 442 lapic_ipi_free(int vector) 443 { 444 445 return (apic_ops.ipi_free(vector)); 446 } 447 448 static inline int 449 lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked) 450 { 451 452 return (apic_ops.set_lvt_mask(apic_id, lvt, masked)); 453 } 454 455 static inline int 456 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode) 457 { 458 459 return (apic_ops.set_lvt_mode(apic_id, lvt, mode)); 460 } 461 462 static inline int 463 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol) 464 { 465 466 return (apic_ops.set_lvt_polarity(apic_id, lvt, pol)); 467 } 468 469 static inline int 470 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger) 471 { 472 473 return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger)); 474 } 475 476 void lapic_handle_cmc(void); 477 void lapic_handle_error(void); 478 void lapic_handle_intr(int vector, struct trapframe *frame); 479 void lapic_handle_timer(struct trapframe *frame); 480 481 int ioapic_get_rid(u_int apic_id, uint16_t *ridp); 482 483 extern int x2apic_mode; 484 extern int lapic_eoi_suppression; 485 486 #ifdef _SYS_SYSCTL_H_ 487 SYSCTL_DECL(_hw_apic); 488 #endif 489 490 #endif /* !LOCORE */ 491 #endif /* _X86_APICVAR_H_ */ 492