1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _X86_APICVAR_H_ 30 #define _X86_APICVAR_H_ 31 32 /* 33 * Local && I/O APIC variable definitions. 34 */ 35 36 /* 37 * Layout of local APIC interrupt vectors: 38 * 39 * 0xff (255) +-------------+ 40 * | | 15 (Spurious / IPIs / Local Interrupts) 41 * 0xf0 (240) +-------------+ 42 * | | 14 (I/O Interrupts / Timer) 43 * 0xe0 (224) +-------------+ 44 * | | 13 (I/O Interrupts) 45 * 0xd0 (208) +-------------+ 46 * | | 12 (I/O Interrupts) 47 * 0xc0 (192) +-------------+ 48 * | | 11 (I/O Interrupts) 49 * 0xb0 (176) +-------------+ 50 * | | 10 (I/O Interrupts) 51 * 0xa0 (160) +-------------+ 52 * | | 9 (I/O Interrupts) 53 * 0x90 (144) +-------------+ 54 * | | 8 (I/O Interrupts / System Calls) 55 * 0x80 (128) +-------------+ 56 * | | 7 (I/O Interrupts) 57 * 0x70 (112) +-------------+ 58 * | | 6 (I/O Interrupts) 59 * 0x60 (96) +-------------+ 60 * | | 5 (I/O Interrupts) 61 * 0x50 (80) +-------------+ 62 * | | 4 (I/O Interrupts) 63 * 0x40 (64) +-------------+ 64 * | | 3 (I/O Interrupts) 65 * 0x30 (48) +-------------+ 66 * | | 2 (ATPIC Interrupts) 67 * 0x20 (32) +-------------+ 68 * | | 1 (Exceptions, traps, faults, etc.) 69 * 0x10 (16) +-------------+ 70 * | | 0 (Exceptions, traps, faults, etc.) 71 * 0x00 (0) +-------------+ 72 * 73 * Note: 0x80 needs to be handled specially and not allocated to an 74 * I/O device! 75 */ 76 77 #define MAX_APIC_ID 0xfe 78 #define APIC_ID_ALL 0xff 79 80 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 81 #define APIC_IO_INTS (IDT_IO_INTS + 16) 82 #define APIC_NUM_IOINTS 191 83 84 /* The timer interrupt is used for clock handling and drives hardclock, etc. */ 85 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 86 87 /* 88 ********************* !!! WARNING !!! ****************************** 89 * Each local apic has an interrupt receive fifo that is two entries deep 90 * for each interrupt priority class (higher 4 bits of interrupt vector). 91 * Once the fifo is full the APIC can no longer receive interrupts for this 92 * class and sending IPIs from other CPUs will be blocked. 93 * To avoid deadlocks there should be no more than two IPI interrupts 94 * pending at the same time. 95 * Currently this is guaranteed by dividing the IPIs in two groups that have 96 * each at most one IPI interrupt pending. The first group is protected by the 97 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 98 * at a time) The second group uses a single interrupt and a bitmap to avoid 99 * redundant IPI interrupts. 100 */ 101 102 /* Interrupts for local APIC LVT entries other than the timer. */ 103 #define APIC_LOCAL_INTS 240 104 #define APIC_ERROR_INT APIC_LOCAL_INTS 105 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 106 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 107 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 108 109 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 110 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ 111 #define IPI_INVLPG (APIC_IPI_INTS + 2) 112 #define IPI_INVLRNG (APIC_IPI_INTS + 3) 113 #define IPI_INVLCACHE (APIC_IPI_INTS + 4) 114 #ifdef __i386__ 115 #define IPI_LAZYPMAP (APIC_IPI_INTS + 5) /* Lazy pmap release. */ 116 #endif 117 /* Vector to handle bitmap based IPIs */ 118 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6) 119 120 /* IPIs handled by IPI_BITMAP_VECTOR */ 121 #define IPI_AST 0 /* Generate software trap. */ 122 #define IPI_PREEMPT 1 123 #define IPI_HARDCLOCK 2 124 #define IPI_BITMAP_LAST IPI_HARDCLOCK 125 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 126 127 #define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */ 128 #define IPI_SUSPEND (APIC_IPI_INTS + 8) /* Suspend CPU until restarted. */ 129 #define IPI_STOP_HARD (APIC_IPI_INTS + 9) /* Stop CPU with a NMI. */ 130 131 /* 132 * The spurious interrupt can share the priority class with the IPIs since 133 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 134 */ 135 #define APIC_SPURIOUS_INT 255 136 137 #ifndef LOCORE 138 139 #define APIC_IPI_DEST_SELF -1 140 #define APIC_IPI_DEST_ALL -2 141 #define APIC_IPI_DEST_OTHERS -3 142 143 #define APIC_BUS_UNKNOWN -1 144 #define APIC_BUS_ISA 0 145 #define APIC_BUS_EISA 1 146 #define APIC_BUS_PCI 2 147 #define APIC_BUS_MAX APIC_BUS_PCI 148 149 /* 150 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including 151 * CPU's and I/O APIC's. 152 */ 153 struct apic_enumerator { 154 const char *apic_name; 155 int (*apic_probe)(void); 156 int (*apic_probe_cpus)(void); 157 int (*apic_setup_local)(void); 158 int (*apic_setup_io)(void); 159 SLIST_ENTRY(apic_enumerator) apic_next; 160 }; 161 162 inthand_t 163 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 164 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 165 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 166 IDTVEC(spuriousint), IDTVEC(timerint); 167 168 extern vm_paddr_t lapic_paddr; 169 extern int apic_cpuids[]; 170 171 void apic_register_enumerator(struct apic_enumerator *enumerator); 172 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 173 int ioapic_disable_pin(void *cookie, u_int pin); 174 int ioapic_get_vector(void *cookie, u_int pin); 175 void ioapic_register(void *cookie); 176 int ioapic_remap_vector(void *cookie, u_int pin, int vector); 177 int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 178 int ioapic_set_extint(void *cookie, u_int pin); 179 int ioapic_set_nmi(void *cookie, u_int pin); 180 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 181 int ioapic_set_triggermode(void *cookie, u_int pin, 182 enum intr_trigger trigger); 183 int ioapic_set_smi(void *cookie, u_int pin); 184 185 /* 186 * Struct containing pointers to APIC functions whose 187 * implementation is run time selectable. 188 */ 189 struct apic_ops { 190 void (*create)(u_int, int); 191 void (*init)(vm_paddr_t); 192 void (*setup)(int); 193 void (*dump)(const char *); 194 void (*disable)(void); 195 void (*eoi)(void); 196 int (*id)(void); 197 int (*intr_pending)(u_int); 198 void (*set_logical_id)(u_int, u_int, u_int); 199 u_int (*cpuid)(u_int); 200 201 /* Vectors */ 202 u_int (*alloc_vector)(u_int, u_int); 203 u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int); 204 void (*enable_vector)(u_int, u_int); 205 void (*disable_vector)(u_int, u_int); 206 void (*free_vector)(u_int, u_int, u_int); 207 208 209 /* PMC */ 210 int (*enable_pmc)(void); 211 void (*disable_pmc)(void); 212 void (*reenable_pmc)(void); 213 214 /* CMC */ 215 void (*enable_cmc)(void); 216 217 /* IPI */ 218 void (*ipi_raw)(register_t, u_int); 219 void (*ipi_vectored)(u_int, int); 220 int (*ipi_wait)(int); 221 222 /* LVT */ 223 int (*set_lvt_mask)(u_int, u_int, u_char); 224 int (*set_lvt_mode)(u_int, u_int, u_int32_t); 225 int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity); 226 int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger); 227 }; 228 229 extern struct apic_ops apic_ops; 230 231 static inline void 232 lapic_create(u_int apic_id, int boot_cpu) 233 { 234 235 apic_ops.create(apic_id, boot_cpu); 236 } 237 238 static inline void 239 lapic_init(vm_paddr_t addr) 240 { 241 242 apic_ops.init(addr); 243 } 244 245 static inline void 246 lapic_setup(int boot) 247 { 248 249 apic_ops.setup(boot); 250 } 251 252 static inline void 253 lapic_dump(const char *str) 254 { 255 256 apic_ops.dump(str); 257 } 258 259 static inline void 260 lapic_disable(void) 261 { 262 263 apic_ops.disable(); 264 } 265 266 static inline void 267 lapic_eoi(void) 268 { 269 270 apic_ops.eoi(); 271 } 272 273 static inline int 274 lapic_id(void) 275 { 276 277 return (apic_ops.id()); 278 } 279 280 static inline int 281 lapic_intr_pending(u_int vector) 282 { 283 284 return (apic_ops.intr_pending(vector)); 285 } 286 287 /* XXX: UNUSED */ 288 static inline void 289 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 290 { 291 292 apic_ops.set_logical_id(apic_id, cluster, cluster_id); 293 } 294 295 static inline u_int 296 apic_cpuid(u_int apic_id) 297 { 298 299 return (apic_ops.cpuid(apic_id)); 300 } 301 302 static inline u_int 303 apic_alloc_vector(u_int apic_id, u_int irq) 304 { 305 306 return (apic_ops.alloc_vector(apic_id, irq)); 307 } 308 309 static inline u_int 310 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 311 { 312 313 return (apic_ops.alloc_vectors(apic_id, irqs, count, align)); 314 } 315 316 static inline void 317 apic_enable_vector(u_int apic_id, u_int vector) 318 { 319 320 apic_ops.enable_vector(apic_id, vector); 321 } 322 323 static inline void 324 apic_disable_vector(u_int apic_id, u_int vector) 325 { 326 327 apic_ops.disable_vector(apic_id, vector); 328 } 329 330 static inline void 331 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 332 { 333 334 apic_ops.free_vector(apic_id, vector, irq); 335 } 336 337 static inline int 338 lapic_enable_pmc(void) 339 { 340 341 return (apic_ops.enable_pmc()); 342 } 343 344 static inline void 345 lapic_disable_pmc(void) 346 { 347 348 apic_ops.disable_pmc(); 349 } 350 351 static inline void 352 lapic_reenable_pmc(void) 353 { 354 355 apic_ops.reenable_pmc(); 356 } 357 358 static inline void 359 lapic_enable_cmc(void) 360 { 361 362 apic_ops.enable_cmc(); 363 } 364 365 static inline void 366 lapic_ipi_raw(register_t icrlo, u_int dest) 367 { 368 369 apic_ops.ipi_raw(icrlo, dest); 370 } 371 372 static inline void 373 lapic_ipi_vectored(u_int vector, int dest) 374 { 375 376 apic_ops.ipi_vectored(vector, dest); 377 } 378 379 static inline int 380 lapic_ipi_wait(int delay) 381 { 382 383 return (apic_ops.ipi_wait(delay)); 384 } 385 386 static inline int 387 lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked) 388 { 389 390 return (apic_ops.set_lvt_mask(apic_id, lvt, masked)); 391 } 392 393 static inline int 394 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode) 395 { 396 397 return (apic_ops.set_lvt_mode(apic_id, lvt, mode)); 398 } 399 400 static inline int 401 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol) 402 { 403 404 return (apic_ops.set_lvt_polarity(apic_id, lvt, pol)); 405 } 406 407 static inline int 408 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger) 409 { 410 411 return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger)); 412 } 413 414 void lapic_handle_cmc(void); 415 void lapic_handle_error(void); 416 void lapic_handle_intr(int vector, struct trapframe *frame); 417 void lapic_handle_timer(struct trapframe *frame); 418 void xen_intr_handle_upcall(struct trapframe *frame); 419 420 #endif /* !LOCORE */ 421 #endif /* _X86_APICVAR_H_ */ 422