1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _X86_APICVAR_H_ 29 #define _X86_APICVAR_H_ 30 31 /* 32 * Local && I/O APIC variable definitions. 33 */ 34 35 /* 36 * Layout of local APIC interrupt vectors: 37 * 38 * 0xff (255) +-------------+ 39 * | | 15 (Spurious / IPIs / Local Interrupts) 40 * 0xf0 (240) +-------------+ 41 * | | 14 (I/O Interrupts / Timer) 42 * 0xe0 (224) +-------------+ 43 * | | 13 (I/O Interrupts) 44 * 0xd0 (208) +-------------+ 45 * | | 12 (I/O Interrupts) 46 * 0xc0 (192) +-------------+ 47 * | | 11 (I/O Interrupts) 48 * 0xb0 (176) +-------------+ 49 * | | 10 (I/O Interrupts) 50 * 0xa0 (160) +-------------+ 51 * | | 9 (I/O Interrupts) 52 * 0x90 (144) +-------------+ 53 * | | 8 (I/O Interrupts / System Calls) 54 * 0x80 (128) +-------------+ 55 * | | 7 (I/O Interrupts) 56 * 0x70 (112) +-------------+ 57 * | | 6 (I/O Interrupts) 58 * 0x60 (96) +-------------+ 59 * | | 5 (I/O Interrupts) 60 * 0x50 (80) +-------------+ 61 * | | 4 (I/O Interrupts) 62 * 0x40 (64) +-------------+ 63 * | | 3 (I/O Interrupts) 64 * 0x30 (48) +-------------+ 65 * | | 2 (ATPIC Interrupts) 66 * 0x20 (32) +-------------+ 67 * | | 1 (Exceptions, traps, faults, etc.) 68 * 0x10 (16) +-------------+ 69 * | | 0 (Exceptions, traps, faults, etc.) 70 * 0x00 (0) +-------------+ 71 * 72 * Note: 0x80 needs to be handled specially and not allocated to an 73 * I/O device! 74 */ 75 76 #define xAPIC_MAX_APIC_ID 0xfe 77 #define xAPIC_ID_ALL 0xff 78 #define MAX_APIC_ID 0x800 79 #define APIC_ID_ALL 0xffffffff 80 81 #define IOAPIC_MAX_ID xAPIC_MAX_APIC_ID 82 83 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 84 #define APIC_IO_INTS (IDT_IO_INTS + 16) 85 #define APIC_NUM_IOINTS 191 86 87 /* The timer interrupt is used for clock handling and drives hardclock, etc. */ 88 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 89 90 /* 91 ********************* !!! WARNING !!! ****************************** 92 * Each local apic has an interrupt receive fifo that is two entries deep 93 * for each interrupt priority class (higher 4 bits of interrupt vector). 94 * Once the fifo is full the APIC can no longer receive interrupts for this 95 * class and sending IPIs from other CPUs will be blocked. 96 * To avoid deadlocks there should be no more than two IPI interrupts 97 * pending at the same time. 98 * Currently this is guaranteed by dividing the IPIs in two groups that have 99 * each at most one IPI interrupt pending. The first group is protected by the 100 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 101 * at a time) The second group uses a single interrupt and a bitmap to avoid 102 * redundant IPI interrupts. 103 */ 104 105 /* Interrupts for local APIC LVT entries other than the timer. */ 106 #define APIC_LOCAL_INTS 240 107 #define APIC_ERROR_INT APIC_LOCAL_INTS 108 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 109 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 110 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 111 112 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 113 #define IPI_INVLOP (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs, amd64 */ 114 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs, i386 */ 115 #define IPI_INVLPG (APIC_IPI_INTS + 2) 116 #define IPI_INVLRNG (APIC_IPI_INTS + 3) 117 #define IPI_INVLCACHE (APIC_IPI_INTS + 4) 118 /* Vector to handle bitmap based IPIs */ 119 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5) 120 121 /* IPIs handled by IPI_BITMAP_VECTOR */ 122 #define IPI_AST 0 /* Generate software trap. */ 123 #define IPI_PREEMPT 1 124 #define IPI_HARDCLOCK 2 125 #define IPI_TRACE 3 /* Collect stack trace. */ 126 #define IPI_BITMAP_LAST IPI_TRACE 127 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 128 129 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */ 130 #define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */ 131 #define IPI_SWI (APIC_IPI_INTS + 8) /* Run clk_intr_event. */ 132 #define IPI_DYN_FIRST (APIC_IPI_INTS + 9) 133 #define IPI_DYN_LAST (254) /* IPIs allocated at runtime */ 134 135 /* 136 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since 137 * it is delivered using an NMI anyways. 138 */ 139 #define IPI_NMI_FIRST 255 140 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */ 141 142 /* 143 * The spurious interrupt can share the priority class with the IPIs since 144 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 145 */ 146 #define APIC_SPURIOUS_INT 255 147 148 #ifndef LOCORE 149 150 #define APIC_IPI_DEST_SELF -1 151 #define APIC_IPI_DEST_ALL -2 152 #define APIC_IPI_DEST_OTHERS -3 153 154 #define APIC_BUS_UNKNOWN -1 155 #define APIC_BUS_ISA 0 156 #define APIC_BUS_EISA 1 157 #define APIC_BUS_PCI 2 158 #define APIC_BUS_MAX APIC_BUS_PCI 159 160 #define IRQ_EXTINT -1 161 #define IRQ_NMI -2 162 #define IRQ_SMI -3 163 #define IRQ_DISABLED -4 164 165 /* 166 * An APIC enumerator is a pseudo bus driver that enumerates APIC's including 167 * CPU's and I/O APIC's. 168 */ 169 struct apic_enumerator { 170 const char *apic_name; 171 int (*apic_probe)(void); 172 int (*apic_probe_cpus)(void); 173 int (*apic_setup_local)(void); 174 int (*apic_setup_io)(void); 175 SLIST_ENTRY(apic_enumerator) apic_next; 176 }; 177 178 inthand_t 179 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 180 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 181 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 182 IDTVEC(spuriousint), IDTVEC(timerint), 183 IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti), 184 IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti), 185 IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti), 186 IDTVEC(spuriousint_pti), IDTVEC(timerint_pti); 187 188 extern vm_paddr_t lapic_paddr; 189 extern int *apic_cpuids; 190 191 /* Allow to replace the lapic_ipi_vectored implementation. */ 192 extern void (*ipi_vectored)(u_int, int); 193 194 void apic_register_enumerator(struct apic_enumerator *enumerator); 195 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 196 int ioapic_disable_pin(void *cookie, u_int pin); 197 int ioapic_get_vector(void *cookie, u_int pin); 198 void ioapic_register(void *cookie); 199 int ioapic_remap_vector(void *cookie, u_int pin, int vector); 200 int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 201 int ioapic_set_extint(void *cookie, u_int pin); 202 int ioapic_set_nmi(void *cookie, u_int pin); 203 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 204 int ioapic_set_triggermode(void *cookie, u_int pin, 205 enum intr_trigger trigger); 206 int ioapic_set_smi(void *cookie, u_int pin); 207 208 void lapic_create(u_int apic_id, int boot_cpu); 209 void lapic_init(vm_paddr_t addr); 210 void lapic_xapic_mode(void); 211 bool lapic_is_x2apic(void); 212 void lapic_setup(int boot); 213 void lapic_dump(const char *str); 214 void lapic_disable(void); 215 void lapic_eoi(void); 216 int lapic_id(void); 217 int lapic_intr_pending(u_int vector); 218 /* XXX: UNUSED */ 219 void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id); 220 u_int apic_cpuid(u_int apic_id); 221 u_int apic_alloc_vector(u_int apic_id, u_int irq); 222 u_int apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align); 223 void apic_enable_vector(u_int apic_id, u_int vector); 224 void apic_disable_vector(u_int apic_id, u_int vector); 225 void apic_free_vector(u_int apic_id, u_int vector, u_int irq); 226 void lapic_calibrate_timer(void); 227 int lapic_enable_pmc(void); 228 void lapic_disable_pmc(void); 229 void lapic_reenable_pmc(void); 230 void lapic_enable_cmc(void); 231 int lapic_enable_mca_elvt(void); 232 void lapic_ipi_raw(register_t icrlo, u_int dest); 233 234 static inline void 235 lapic_ipi_vectored(u_int vector, int dest) 236 { 237 238 ipi_vectored(vector, dest); 239 } 240 241 int lapic_ipi_wait(int delay); 242 int lapic_ipi_alloc(inthand_t *ipifunc); 243 void lapic_ipi_free(int vector); 244 int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked); 245 int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode); 246 int lapic_set_lvt_polarity(u_int apic_id, u_int lvt, 247 enum intr_polarity pol); 248 int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, 249 enum intr_trigger trigger); 250 void lapic_handle_cmc(void); 251 void lapic_handle_error(void); 252 void lapic_handle_intr(int vector, struct trapframe *frame); 253 void lapic_handle_timer(struct trapframe *frame); 254 255 int ioapic_get_rid(u_int apic_id, uint16_t *ridp); 256 257 extern int x2apic_mode; 258 extern int lapic_eoi_suppression; 259 260 #ifdef _SYS_SYSCTL_H_ 261 SYSCTL_DECL(_hw_apic); 262 #endif 263 264 #endif /* !LOCORE */ 265 #endif /* _X86_APICVAR_H_ */ 266