1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _X86_APICVAR_H_ 30 #define _X86_APICVAR_H_ 31 32 /* 33 * Local && I/O APIC variable definitions. 34 */ 35 36 /* 37 * Layout of local APIC interrupt vectors: 38 * 39 * 0xff (255) +-------------+ 40 * | | 15 (Spurious / IPIs / Local Interrupts) 41 * 0xf0 (240) +-------------+ 42 * | | 14 (I/O Interrupts / Timer) 43 * 0xe0 (224) +-------------+ 44 * | | 13 (I/O Interrupts) 45 * 0xd0 (208) +-------------+ 46 * | | 12 (I/O Interrupts) 47 * 0xc0 (192) +-------------+ 48 * | | 11 (I/O Interrupts) 49 * 0xb0 (176) +-------------+ 50 * | | 10 (I/O Interrupts) 51 * 0xa0 (160) +-------------+ 52 * | | 9 (I/O Interrupts) 53 * 0x90 (144) +-------------+ 54 * | | 8 (I/O Interrupts / System Calls) 55 * 0x80 (128) +-------------+ 56 * | | 7 (I/O Interrupts) 57 * 0x70 (112) +-------------+ 58 * | | 6 (I/O Interrupts) 59 * 0x60 (96) +-------------+ 60 * | | 5 (I/O Interrupts) 61 * 0x50 (80) +-------------+ 62 * | | 4 (I/O Interrupts) 63 * 0x40 (64) +-------------+ 64 * | | 3 (I/O Interrupts) 65 * 0x30 (48) +-------------+ 66 * | | 2 (ATPIC Interrupts) 67 * 0x20 (32) +-------------+ 68 * | | 1 (Exceptions, traps, faults, etc.) 69 * 0x10 (16) +-------------+ 70 * | | 0 (Exceptions, traps, faults, etc.) 71 * 0x00 (0) +-------------+ 72 * 73 * Note: 0x80 needs to be handled specially and not allocated to an 74 * I/O device! 75 */ 76 77 #define MAX_APIC_ID 0xfe 78 #define APIC_ID_ALL 0xff 79 80 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 81 #define APIC_IO_INTS (IDT_IO_INTS + 16) 82 #define APIC_NUM_IOINTS 191 83 84 /* The timer interrupt is used for clock handling and drives hardclock, etc. */ 85 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 86 87 /* 88 ********************* !!! WARNING !!! ****************************** 89 * Each local apic has an interrupt receive fifo that is two entries deep 90 * for each interrupt priority class (higher 4 bits of interrupt vector). 91 * Once the fifo is full the APIC can no longer receive interrupts for this 92 * class and sending IPIs from other CPUs will be blocked. 93 * To avoid deadlocks there should be no more than two IPI interrupts 94 * pending at the same time. 95 * Currently this is guaranteed by dividing the IPIs in two groups that have 96 * each at most one IPI interrupt pending. The first group is protected by the 97 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 98 * at a time) The second group uses a single interrupt and a bitmap to avoid 99 * redundant IPI interrupts. 100 */ 101 102 /* Interrupts for local APIC LVT entries other than the timer. */ 103 #define APIC_LOCAL_INTS 240 104 #define APIC_ERROR_INT APIC_LOCAL_INTS 105 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 106 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 107 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 108 109 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 110 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ 111 #define IPI_INVLPG (APIC_IPI_INTS + 2) 112 #define IPI_INVLRNG (APIC_IPI_INTS + 3) 113 #define IPI_INVLCACHE (APIC_IPI_INTS + 4) 114 #ifdef __i386__ 115 #define IPI_LAZYPMAP (APIC_IPI_INTS + 5) /* Lazy pmap release. */ 116 #endif 117 /* Vector to handle bitmap based IPIs */ 118 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6) 119 120 /* IPIs handled by IPI_BITMAP_VECTOR */ 121 #define IPI_AST 0 /* Generate software trap. */ 122 #define IPI_PREEMPT 1 123 #define IPI_HARDCLOCK 2 124 #define IPI_BITMAP_LAST IPI_HARDCLOCK 125 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 126 127 #define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */ 128 #define IPI_SUSPEND (APIC_IPI_INTS + 8) /* Suspend CPU until restarted. */ 129 130 /* 131 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since 132 * it is delivered using an NMI anyways. 133 */ 134 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */ 135 136 /* 137 * The spurious interrupt can share the priority class with the IPIs since 138 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 139 */ 140 #define APIC_SPURIOUS_INT 255 141 142 #ifndef LOCORE 143 144 #define APIC_IPI_DEST_SELF -1 145 #define APIC_IPI_DEST_ALL -2 146 #define APIC_IPI_DEST_OTHERS -3 147 148 #define APIC_BUS_UNKNOWN -1 149 #define APIC_BUS_ISA 0 150 #define APIC_BUS_EISA 1 151 #define APIC_BUS_PCI 2 152 #define APIC_BUS_MAX APIC_BUS_PCI 153 154 /* 155 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including 156 * CPU's and I/O APIC's. 157 */ 158 struct apic_enumerator { 159 const char *apic_name; 160 int (*apic_probe)(void); 161 int (*apic_probe_cpus)(void); 162 int (*apic_setup_local)(void); 163 int (*apic_setup_io)(void); 164 SLIST_ENTRY(apic_enumerator) apic_next; 165 }; 166 167 inthand_t 168 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 169 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 170 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 171 IDTVEC(spuriousint), IDTVEC(timerint); 172 173 extern vm_paddr_t lapic_paddr; 174 extern int apic_cpuids[]; 175 176 void apic_register_enumerator(struct apic_enumerator *enumerator); 177 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 178 int ioapic_disable_pin(void *cookie, u_int pin); 179 int ioapic_get_vector(void *cookie, u_int pin); 180 void ioapic_register(void *cookie); 181 int ioapic_remap_vector(void *cookie, u_int pin, int vector); 182 int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 183 int ioapic_set_extint(void *cookie, u_int pin); 184 int ioapic_set_nmi(void *cookie, u_int pin); 185 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 186 int ioapic_set_triggermode(void *cookie, u_int pin, 187 enum intr_trigger trigger); 188 int ioapic_set_smi(void *cookie, u_int pin); 189 190 /* 191 * Struct containing pointers to APIC functions whose 192 * implementation is run time selectable. 193 */ 194 struct apic_ops { 195 void (*create)(u_int, int); 196 void (*init)(vm_paddr_t); 197 void (*xapic_mode)(void); 198 void (*setup)(int); 199 void (*dump)(const char *); 200 void (*disable)(void); 201 void (*eoi)(void); 202 int (*id)(void); 203 int (*intr_pending)(u_int); 204 void (*set_logical_id)(u_int, u_int, u_int); 205 u_int (*cpuid)(u_int); 206 207 /* Vectors */ 208 u_int (*alloc_vector)(u_int, u_int); 209 u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int); 210 void (*enable_vector)(u_int, u_int); 211 void (*disable_vector)(u_int, u_int); 212 void (*free_vector)(u_int, u_int, u_int); 213 214 215 /* PMC */ 216 int (*enable_pmc)(void); 217 void (*disable_pmc)(void); 218 void (*reenable_pmc)(void); 219 220 /* CMC */ 221 void (*enable_cmc)(void); 222 223 /* IPI */ 224 void (*ipi_raw)(register_t, u_int); 225 void (*ipi_vectored)(u_int, int); 226 int (*ipi_wait)(int); 227 228 /* LVT */ 229 int (*set_lvt_mask)(u_int, u_int, u_char); 230 int (*set_lvt_mode)(u_int, u_int, u_int32_t); 231 int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity); 232 int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger); 233 }; 234 235 extern struct apic_ops apic_ops; 236 237 static inline void 238 lapic_create(u_int apic_id, int boot_cpu) 239 { 240 241 apic_ops.create(apic_id, boot_cpu); 242 } 243 244 static inline void 245 lapic_init(vm_paddr_t addr) 246 { 247 248 apic_ops.init(addr); 249 } 250 251 static inline void 252 lapic_xapic_mode(void) 253 { 254 255 apic_ops.xapic_mode(); 256 } 257 258 static inline void 259 lapic_setup(int boot) 260 { 261 262 apic_ops.setup(boot); 263 } 264 265 static inline void 266 lapic_dump(const char *str) 267 { 268 269 apic_ops.dump(str); 270 } 271 272 static inline void 273 lapic_disable(void) 274 { 275 276 apic_ops.disable(); 277 } 278 279 static inline void 280 lapic_eoi(void) 281 { 282 283 apic_ops.eoi(); 284 } 285 286 static inline int 287 lapic_id(void) 288 { 289 290 return (apic_ops.id()); 291 } 292 293 static inline int 294 lapic_intr_pending(u_int vector) 295 { 296 297 return (apic_ops.intr_pending(vector)); 298 } 299 300 /* XXX: UNUSED */ 301 static inline void 302 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 303 { 304 305 apic_ops.set_logical_id(apic_id, cluster, cluster_id); 306 } 307 308 static inline u_int 309 apic_cpuid(u_int apic_id) 310 { 311 312 return (apic_ops.cpuid(apic_id)); 313 } 314 315 static inline u_int 316 apic_alloc_vector(u_int apic_id, u_int irq) 317 { 318 319 return (apic_ops.alloc_vector(apic_id, irq)); 320 } 321 322 static inline u_int 323 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 324 { 325 326 return (apic_ops.alloc_vectors(apic_id, irqs, count, align)); 327 } 328 329 static inline void 330 apic_enable_vector(u_int apic_id, u_int vector) 331 { 332 333 apic_ops.enable_vector(apic_id, vector); 334 } 335 336 static inline void 337 apic_disable_vector(u_int apic_id, u_int vector) 338 { 339 340 apic_ops.disable_vector(apic_id, vector); 341 } 342 343 static inline void 344 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 345 { 346 347 apic_ops.free_vector(apic_id, vector, irq); 348 } 349 350 static inline int 351 lapic_enable_pmc(void) 352 { 353 354 return (apic_ops.enable_pmc()); 355 } 356 357 static inline void 358 lapic_disable_pmc(void) 359 { 360 361 apic_ops.disable_pmc(); 362 } 363 364 static inline void 365 lapic_reenable_pmc(void) 366 { 367 368 apic_ops.reenable_pmc(); 369 } 370 371 static inline void 372 lapic_enable_cmc(void) 373 { 374 375 apic_ops.enable_cmc(); 376 } 377 378 static inline void 379 lapic_ipi_raw(register_t icrlo, u_int dest) 380 { 381 382 apic_ops.ipi_raw(icrlo, dest); 383 } 384 385 static inline void 386 lapic_ipi_vectored(u_int vector, int dest) 387 { 388 389 apic_ops.ipi_vectored(vector, dest); 390 } 391 392 static inline int 393 lapic_ipi_wait(int delay) 394 { 395 396 return (apic_ops.ipi_wait(delay)); 397 } 398 399 static inline int 400 lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked) 401 { 402 403 return (apic_ops.set_lvt_mask(apic_id, lvt, masked)); 404 } 405 406 static inline int 407 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode) 408 { 409 410 return (apic_ops.set_lvt_mode(apic_id, lvt, mode)); 411 } 412 413 static inline int 414 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol) 415 { 416 417 return (apic_ops.set_lvt_polarity(apic_id, lvt, pol)); 418 } 419 420 static inline int 421 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger) 422 { 423 424 return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger)); 425 } 426 427 void lapic_handle_cmc(void); 428 void lapic_handle_error(void); 429 void lapic_handle_intr(int vector, struct trapframe *frame); 430 void lapic_handle_timer(struct trapframe *frame); 431 void xen_intr_handle_upcall(struct trapframe *frame); 432 433 extern int x2apic_mode; 434 extern int lapic_eoi_suppression; 435 436 #ifdef _SYS_SYSCTL_H_ 437 SYSCTL_DECL(_hw_apic); 438 #endif 439 440 #endif /* !LOCORE */ 441 #endif /* _X86_APICVAR_H_ */ 442