1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005 Nate Lawson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Throttle clock frequency by using the thermal control circuit. This 31 * operates independently of SpeedStep and ACPI throttling and is supported 32 * on Pentium 4 and later models (feature TM). 33 * 34 * Reference: Intel Developer's manual v.3 #245472-012 35 * 36 * The original version of this driver was written by Ted Unangst for 37 * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson 38 * for use with the cpufreq framework. 39 */ 40 41 #include <sys/cdefs.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/cpu.h> 46 #include <sys/kernel.h> 47 #include <sys/module.h> 48 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #include "cpufreq_if.h" 53 54 #include <contrib/dev/acpica/include/acpi.h> 55 56 #include <dev/acpica/acpivar.h> 57 #include "acpi_if.h" 58 59 struct p4tcc_softc { 60 device_t dev; 61 int set_count; 62 int lowest_val; 63 int auto_mode; 64 }; 65 66 #define TCC_NUM_SETTINGS 8 67 68 #define TCC_ENABLE_ONDEMAND (1<<4) 69 #define TCC_REG_OFFSET 1 70 #define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS) 71 72 static int p4tcc_features(driver_t *driver, u_int *features); 73 static void p4tcc_identify(driver_t *driver, device_t parent); 74 static int p4tcc_probe(device_t dev); 75 static int p4tcc_attach(device_t dev); 76 static int p4tcc_detach(device_t dev); 77 static int p4tcc_settings(device_t dev, struct cf_setting *sets, 78 int *count); 79 static int p4tcc_set(device_t dev, const struct cf_setting *set); 80 static int p4tcc_get(device_t dev, struct cf_setting *set); 81 static int p4tcc_type(device_t dev, int *type); 82 83 static device_method_t p4tcc_methods[] = { 84 /* Device interface */ 85 DEVMETHOD(device_identify, p4tcc_identify), 86 DEVMETHOD(device_probe, p4tcc_probe), 87 DEVMETHOD(device_attach, p4tcc_attach), 88 DEVMETHOD(device_detach, p4tcc_detach), 89 90 /* cpufreq interface */ 91 DEVMETHOD(cpufreq_drv_set, p4tcc_set), 92 DEVMETHOD(cpufreq_drv_get, p4tcc_get), 93 DEVMETHOD(cpufreq_drv_type, p4tcc_type), 94 DEVMETHOD(cpufreq_drv_settings, p4tcc_settings), 95 96 /* ACPI interface */ 97 DEVMETHOD(acpi_get_features, p4tcc_features), 98 {0, 0} 99 }; 100 101 static driver_t p4tcc_driver = { 102 "p4tcc", 103 p4tcc_methods, 104 sizeof(struct p4tcc_softc), 105 }; 106 107 DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, 0, 0); 108 109 static int 110 p4tcc_features(driver_t *driver, u_int *features) 111 { 112 113 /* Notify the ACPI CPU that we support direct access to MSRs */ 114 *features = ACPI_CAP_THR_MSRS; 115 return (0); 116 } 117 118 static void 119 p4tcc_identify(driver_t *driver, device_t parent) 120 { 121 122 if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM)) 123 return; 124 125 /* Make sure we're not being doubly invoked. */ 126 if (device_find_child(parent, "p4tcc", -1) != NULL) 127 return; 128 129 /* 130 * We attach a p4tcc child for every CPU since settings need to 131 * be performed on every CPU in the SMP case. See section 13.15.3 132 * of the IA32 Intel Architecture Software Developer's Manual, 133 * Volume 3, for more info. 134 */ 135 if (BUS_ADD_CHILD(parent, 10, "p4tcc", device_get_unit(parent)) 136 == NULL) 137 device_printf(parent, "add p4tcc child failed\n"); 138 } 139 140 static int 141 p4tcc_probe(device_t dev) 142 { 143 144 if (resource_disabled("p4tcc", 0)) 145 return (ENXIO); 146 147 device_set_desc(dev, "CPU Frequency Thermal Control"); 148 return (0); 149 } 150 151 static int 152 p4tcc_attach(device_t dev) 153 { 154 struct p4tcc_softc *sc; 155 struct cf_setting set; 156 157 sc = device_get_softc(dev); 158 sc->dev = dev; 159 sc->set_count = TCC_NUM_SETTINGS; 160 161 /* 162 * On boot, the TCC is usually in Automatic mode where reading the 163 * current performance level is likely to produce bogus results. 164 * We record that state here and don't trust the contents of the 165 * status MSR until we've set it ourselves. 166 */ 167 sc->auto_mode = TRUE; 168 169 /* 170 * XXX: After a cursory glance at various Intel specification 171 * XXX: updates it seems like these tests for errata is bogus. 172 * XXX: As far as I can tell, the failure mode is benign, in 173 * XXX: that cpus with no errata will have their bottom two 174 * XXX: STPCLK# rates disabled, so rather than waste more time 175 * XXX: hunting down intel docs, just document it and punt. /phk 176 */ 177 switch (cpu_id & 0xff) { 178 case 0x22: 179 case 0x24: 180 case 0x25: 181 case 0x27: 182 case 0x29: 183 /* 184 * These CPU models hang when set to 12.5%. 185 * See Errata O50, P44, and Z21. 186 */ 187 sc->set_count -= 1; 188 break; 189 case 0x07: /* errata N44 and P18 */ 190 case 0x0a: 191 case 0x12: 192 case 0x13: 193 case 0x62: /* Pentium D B1: errata AA21 */ 194 case 0x64: /* Pentium D C1: errata AA21 */ 195 case 0x65: /* Pentium D D0: errata AA21 */ 196 /* 197 * These CPU models hang when set to 12.5% or 25%. 198 * See Errata N44, P18l and AA21. 199 */ 200 sc->set_count -= 2; 201 break; 202 } 203 sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1; 204 205 /* 206 * Before we finish attach, switch to 100%. It's possible the BIOS 207 * set us to a lower rate. The user can override this after boot. 208 */ 209 set.freq = 10000; 210 p4tcc_set(dev, &set); 211 212 cpufreq_register(dev); 213 return (0); 214 } 215 216 static int 217 p4tcc_detach(device_t dev) 218 { 219 struct cf_setting set; 220 int error; 221 222 error = cpufreq_unregister(dev); 223 if (error) 224 return (error); 225 226 /* 227 * Before we finish detach, switch to Automatic mode. 228 */ 229 set.freq = 10000; 230 p4tcc_set(dev, &set); 231 return(0); 232 } 233 234 static int 235 p4tcc_settings(device_t dev, struct cf_setting *sets, int *count) 236 { 237 struct p4tcc_softc *sc; 238 int i, val; 239 240 sc = device_get_softc(dev); 241 if (sets == NULL || count == NULL) 242 return (EINVAL); 243 if (*count < sc->set_count) 244 return (E2BIG); 245 246 /* Return a list of valid settings for this driver. */ 247 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); 248 val = TCC_NUM_SETTINGS; 249 for (i = 0; i < sc->set_count; i++, val--) { 250 sets[i].freq = TCC_SPEED_PERCENT(val); 251 sets[i].dev = dev; 252 } 253 *count = sc->set_count; 254 255 return (0); 256 } 257 258 static int 259 p4tcc_set(device_t dev, const struct cf_setting *set) 260 { 261 struct p4tcc_softc *sc; 262 uint64_t mask, msr; 263 int val; 264 265 if (set == NULL) 266 return (EINVAL); 267 sc = device_get_softc(dev); 268 269 /* 270 * Validate requested state converts to a setting that is an integer 271 * from [sc->lowest_val .. TCC_NUM_SETTINGS]. 272 */ 273 val = set->freq * TCC_NUM_SETTINGS / 10000; 274 if (val * 10000 != set->freq * TCC_NUM_SETTINGS || 275 val < sc->lowest_val || val > TCC_NUM_SETTINGS) 276 return (EINVAL); 277 278 /* 279 * Read the current register and mask off the old setting and 280 * On-Demand bit. If the new val is < 100%, set it and the On-Demand 281 * bit, otherwise just return to Automatic mode. 282 */ 283 msr = rdmsr(MSR_THERM_CONTROL); 284 mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET; 285 msr &= ~(mask | TCC_ENABLE_ONDEMAND); 286 if (val < TCC_NUM_SETTINGS) 287 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; 288 wrmsr(MSR_THERM_CONTROL, msr); 289 290 /* 291 * Record whether we're now in Automatic or On-Demand mode. We have 292 * to cache this since there is no reliable way to check if TCC is in 293 * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of 294 * the ACPI Thermal Monitor Control Register produces 0 no matter 295 * what the current mode. 296 */ 297 if (msr & TCC_ENABLE_ONDEMAND) 298 sc->auto_mode = FALSE; 299 else 300 sc->auto_mode = TRUE; 301 302 return (0); 303 } 304 305 static int 306 p4tcc_get(device_t dev, struct cf_setting *set) 307 { 308 struct p4tcc_softc *sc; 309 uint64_t msr; 310 int val; 311 312 if (set == NULL) 313 return (EINVAL); 314 sc = device_get_softc(dev); 315 316 /* 317 * Read the current register and extract the current setting. If 318 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%). 319 * 320 * XXX This is not completely reliable since at high temperatures 321 * the CPU may be automatically throttling to 50% but it's the best 322 * we can do. 323 */ 324 if (!sc->auto_mode) { 325 msr = rdmsr(MSR_THERM_CONTROL); 326 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); 327 } else 328 val = TCC_NUM_SETTINGS; 329 330 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 331 set->freq = TCC_SPEED_PERCENT(val); 332 set->dev = dev; 333 334 return (0); 335 } 336 337 static int 338 p4tcc_type(device_t dev, int *type) 339 { 340 341 if (type == NULL) 342 return (EINVAL); 343 344 *type = CPUFREQ_TYPE_RELATIVE; 345 return (0); 346 } 347