1 /*- 2 * Copyright (c) 2005 Nate Lawson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Throttle clock frequency by using the thermal control circuit. This 29 * operates independently of SpeedStep and ACPI throttling and is supported 30 * on Pentium 4 and later models (feature TM). 31 * 32 * Reference: Intel Developer's manual v.3 #245472-012 33 * 34 * The original version of this driver was written by Ted Unangst for 35 * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson 36 * for use with the cpufreq framework. 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/cpu.h> 46 #include <sys/kernel.h> 47 #include <sys/module.h> 48 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #include "cpufreq_if.h" 53 54 #include <contrib/dev/acpica/include/acpi.h> 55 56 #include <dev/acpica/acpivar.h> 57 #include "acpi_if.h" 58 59 struct p4tcc_softc { 60 device_t dev; 61 int set_count; 62 int lowest_val; 63 int auto_mode; 64 }; 65 66 #define TCC_NUM_SETTINGS 8 67 68 #define TCC_ENABLE_ONDEMAND (1<<4) 69 #define TCC_REG_OFFSET 1 70 #define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS) 71 72 static int p4tcc_features(driver_t *driver, u_int *features); 73 static void p4tcc_identify(driver_t *driver, device_t parent); 74 static int p4tcc_probe(device_t dev); 75 static int p4tcc_attach(device_t dev); 76 static int p4tcc_settings(device_t dev, struct cf_setting *sets, 77 int *count); 78 static int p4tcc_set(device_t dev, const struct cf_setting *set); 79 static int p4tcc_get(device_t dev, struct cf_setting *set); 80 static int p4tcc_type(device_t dev, int *type); 81 82 static device_method_t p4tcc_methods[] = { 83 /* Device interface */ 84 DEVMETHOD(device_identify, p4tcc_identify), 85 DEVMETHOD(device_probe, p4tcc_probe), 86 DEVMETHOD(device_attach, p4tcc_attach), 87 88 /* cpufreq interface */ 89 DEVMETHOD(cpufreq_drv_set, p4tcc_set), 90 DEVMETHOD(cpufreq_drv_get, p4tcc_get), 91 DEVMETHOD(cpufreq_drv_type, p4tcc_type), 92 DEVMETHOD(cpufreq_drv_settings, p4tcc_settings), 93 94 /* ACPI interface */ 95 DEVMETHOD(acpi_get_features, p4tcc_features), 96 97 {0, 0} 98 }; 99 100 static driver_t p4tcc_driver = { 101 "p4tcc", 102 p4tcc_methods, 103 sizeof(struct p4tcc_softc), 104 }; 105 106 static devclass_t p4tcc_devclass; 107 DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0); 108 109 static int 110 p4tcc_features(driver_t *driver, u_int *features) 111 { 112 113 /* Notify the ACPI CPU that we support direct access to MSRs */ 114 *features = ACPI_CAP_THR_MSRS; 115 return (0); 116 } 117 118 static void 119 p4tcc_identify(driver_t *driver, device_t parent) 120 { 121 122 if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM)) 123 return; 124 125 /* Make sure we're not being doubly invoked. */ 126 if (device_find_child(parent, "p4tcc", -1) != NULL) 127 return; 128 129 /* 130 * We attach a p4tcc child for every CPU since settings need to 131 * be performed on every CPU in the SMP case. See section 13.15.3 132 * of the IA32 Intel Architecture Software Developer's Manual, 133 * Volume 3, for more info. 134 */ 135 if (BUS_ADD_CHILD(parent, 10, "p4tcc", -1) == NULL) 136 device_printf(parent, "add p4tcc child failed\n"); 137 } 138 139 static int 140 p4tcc_probe(device_t dev) 141 { 142 143 if (resource_disabled("p4tcc", 0)) 144 return (ENXIO); 145 146 device_set_desc(dev, "CPU Frequency Thermal Control"); 147 return (0); 148 } 149 150 static int 151 p4tcc_attach(device_t dev) 152 { 153 struct p4tcc_softc *sc; 154 struct cf_setting set; 155 156 sc = device_get_softc(dev); 157 sc->dev = dev; 158 sc->set_count = TCC_NUM_SETTINGS; 159 160 /* 161 * On boot, the TCC is usually in Automatic mode where reading the 162 * current performance level is likely to produce bogus results. 163 * We record that state here and don't trust the contents of the 164 * status MSR until we've set it ourselves. 165 */ 166 sc->auto_mode = TRUE; 167 168 /* 169 * XXX: After a cursory glance at various Intel specification 170 * XXX: updates it seems like these tests for errata is bogus. 171 * XXX: As far as I can tell, the failure mode is benign, in 172 * XXX: that cpus with no errata will have their bottom two 173 * XXX: STPCLK# rates disabled, so rather than waste more time 174 * XXX: hunting down intel docs, just document it and punt. /phk 175 */ 176 switch (cpu_id & 0xff) { 177 case 0x22: 178 case 0x24: 179 case 0x25: 180 case 0x27: 181 case 0x29: 182 /* 183 * These CPU models hang when set to 12.5%. 184 * See Errata O50, P44, and Z21. 185 */ 186 sc->set_count -= 1; 187 break; 188 case 0x07: /* errata N44 and P18 */ 189 case 0x0a: 190 case 0x12: 191 case 0x13: 192 case 0x62: /* Pentium D B1: errata AA21 */ 193 case 0x64: /* Pentium D C1: errata AA21 */ 194 case 0x65: /* Pentium D D0: errata AA21 */ 195 /* 196 * These CPU models hang when set to 12.5% or 25%. 197 * See Errata N44, P18l and AA21. 198 */ 199 sc->set_count -= 2; 200 break; 201 } 202 sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1; 203 204 /* 205 * Before we finish attach, switch to 100%. It's possible the BIOS 206 * set us to a lower rate. The user can override this after boot. 207 */ 208 set.freq = 10000; 209 p4tcc_set(dev, &set); 210 211 cpufreq_register(dev); 212 return (0); 213 } 214 215 static int 216 p4tcc_settings(device_t dev, struct cf_setting *sets, int *count) 217 { 218 struct p4tcc_softc *sc; 219 int i, val; 220 221 sc = device_get_softc(dev); 222 if (sets == NULL || count == NULL) 223 return (EINVAL); 224 if (*count < sc->set_count) 225 return (E2BIG); 226 227 /* Return a list of valid settings for this driver. */ 228 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); 229 val = TCC_NUM_SETTINGS; 230 for (i = 0; i < sc->set_count; i++, val--) { 231 sets[i].freq = TCC_SPEED_PERCENT(val); 232 sets[i].dev = dev; 233 } 234 *count = sc->set_count; 235 236 return (0); 237 } 238 239 static int 240 p4tcc_set(device_t dev, const struct cf_setting *set) 241 { 242 struct p4tcc_softc *sc; 243 uint64_t mask, msr; 244 int val; 245 246 if (set == NULL) 247 return (EINVAL); 248 sc = device_get_softc(dev); 249 250 /* 251 * Validate requested state converts to a setting that is an integer 252 * from [sc->lowest_val .. TCC_NUM_SETTINGS]. 253 */ 254 val = set->freq * TCC_NUM_SETTINGS / 10000; 255 if (val * 10000 != set->freq * TCC_NUM_SETTINGS || 256 val < sc->lowest_val || val > TCC_NUM_SETTINGS) 257 return (EINVAL); 258 259 /* 260 * Read the current register and mask off the old setting and 261 * On-Demand bit. If the new val is < 100%, set it and the On-Demand 262 * bit, otherwise just return to Automatic mode. 263 */ 264 msr = rdmsr(MSR_THERM_CONTROL); 265 mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET; 266 msr &= ~(mask | TCC_ENABLE_ONDEMAND); 267 if (val < TCC_NUM_SETTINGS) 268 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; 269 wrmsr(MSR_THERM_CONTROL, msr); 270 271 /* 272 * Record whether we're now in Automatic or On-Demand mode. We have 273 * to cache this since there is no reliable way to check if TCC is in 274 * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of 275 * the ACPI Thermal Monitor Control Register produces 0 no matter 276 * what the current mode. 277 */ 278 if (msr & TCC_ENABLE_ONDEMAND) 279 sc->auto_mode = TRUE; 280 else 281 sc->auto_mode = FALSE; 282 283 return (0); 284 } 285 286 static int 287 p4tcc_get(device_t dev, struct cf_setting *set) 288 { 289 struct p4tcc_softc *sc; 290 uint64_t msr; 291 int val; 292 293 if (set == NULL) 294 return (EINVAL); 295 sc = device_get_softc(dev); 296 297 /* 298 * Read the current register and extract the current setting. If 299 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%). 300 * 301 * XXX This is not completely reliable since at high temperatures 302 * the CPU may be automatically throttling to 50% but it's the best 303 * we can do. 304 */ 305 if (!sc->auto_mode) { 306 msr = rdmsr(MSR_THERM_CONTROL); 307 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); 308 } else 309 val = TCC_NUM_SETTINGS; 310 311 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 312 set->freq = TCC_SPEED_PERCENT(val); 313 set->dev = dev; 314 315 return (0); 316 } 317 318 static int 319 p4tcc_type(device_t dev, int *type) 320 { 321 322 if (type == NULL) 323 return (EINVAL); 324 325 *type = CPUFREQ_TYPE_RELATIVE; 326 return (0); 327 } 328