1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004 Colin Percival 5 * Copyright (c) 2005 Nate Lawson 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted providing that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 21 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/cpu.h> 36 #include <sys/kernel.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/smp.h> 40 #include <sys/systm.h> 41 42 #include "cpufreq_if.h" 43 #include <machine/clock.h> 44 #include <machine/cputypes.h> 45 #include <machine/md_var.h> 46 #include <machine/specialreg.h> 47 48 #include <contrib/dev/acpica/include/acpi.h> 49 50 #include <dev/acpica/acpivar.h> 51 #include "acpi_if.h" 52 53 /* Status/control registers (from the IA-32 System Programming Guide). */ 54 #define MSR_PERF_STATUS 0x198 55 #define MSR_PERF_CTL 0x199 56 57 /* Register and bit for enabling SpeedStep. */ 58 #define MSR_MISC_ENABLE 0x1a0 59 #define MSR_SS_ENABLE (1<<16) 60 61 /* Frequency and MSR control values. */ 62 typedef struct { 63 uint16_t freq; 64 uint16_t volts; 65 uint16_t id16; 66 int power; 67 } freq_info; 68 69 /* Identifying characteristics of a processor and supported frequencies. */ 70 typedef struct { 71 const u_int vendor_id; 72 uint32_t id32; 73 freq_info *freqtab; 74 } cpu_info; 75 76 struct est_softc { 77 device_t dev; 78 int acpi_settings; 79 int msr_settings; 80 freq_info *freq_list; 81 }; 82 83 /* Convert MHz and mV into IDs for passing to the MSR. */ 84 #define ID16(MHz, mV, bus_clk) \ 85 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 86 #define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 87 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 88 89 /* Format for storing IDs in our table. */ 90 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 91 { MHz, mV, ID16(MHz, mV, bus_clk), mW } 92 #define FREQ_INFO(MHz, mV, bus_clk) \ 93 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 94 #define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 95 { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 96 #define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 97 { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 98 99 static int msr_info_enabled = 0; 100 TUNABLE_INT("hw.est.msr_info", &msr_info_enabled); 101 static int strict = -1; 102 TUNABLE_INT("hw.est.strict", &strict); 103 104 /* Default bus clock value for Centrino processors. */ 105 #define INTEL_BUS_CLK 100 106 107 /* XXX Update this if new CPUs have more settings. */ 108 #define EST_MAX_SETTINGS 10 109 CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 110 111 /* Estimate in microseconds of latency for performing a transition. */ 112 #define EST_TRANS_LAT 1000 113 114 /* 115 * Frequency (MHz) and voltage (mV) settings. 116 * 117 * Dothan processors have multiple VID#s with different settings for 118 * each VID#. Since we can't uniquely identify this info 119 * without undisclosed methods from Intel, we can't support newer 120 * processors with this table method. If ACPI Px states are supported, 121 * we get info from them. 122 * 123 * Data from the "Intel Pentium M Processor Datasheet", 124 * Order Number 252612-003, Table 5. 125 */ 126 static freq_info PM17_130[] = { 127 /* 130nm 1.70GHz Pentium M */ 128 FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 129 FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 130 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 131 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 132 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 133 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 134 FREQ_INFO( 0, 0, 1), 135 }; 136 static freq_info PM16_130[] = { 137 /* 130nm 1.60GHz Pentium M */ 138 FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 139 FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 140 FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 141 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 142 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 143 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 144 FREQ_INFO( 0, 0, 1), 145 }; 146 static freq_info PM15_130[] = { 147 /* 130nm 1.50GHz Pentium M */ 148 FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 149 FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 150 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 151 FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 152 FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 153 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 154 FREQ_INFO( 0, 0, 1), 155 }; 156 static freq_info PM14_130[] = { 157 /* 130nm 1.40GHz Pentium M */ 158 FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 159 FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 160 FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 161 FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 162 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 163 FREQ_INFO( 0, 0, 1), 164 }; 165 static freq_info PM13_130[] = { 166 /* 130nm 1.30GHz Pentium M */ 167 FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 168 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 169 FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 170 FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 171 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 172 FREQ_INFO( 0, 0, 1), 173 }; 174 static freq_info PM13_LV_130[] = { 175 /* 130nm 1.30GHz Low Voltage Pentium M */ 176 FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 177 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 178 FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 179 FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 180 FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 181 FREQ_INFO( 800, 988, INTEL_BUS_CLK), 182 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 183 FREQ_INFO( 0, 0, 1), 184 }; 185 static freq_info PM12_LV_130[] = { 186 /* 130 nm 1.20GHz Low Voltage Pentium M */ 187 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 188 FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 189 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 190 FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 191 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 192 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 193 FREQ_INFO( 0, 0, 1), 194 }; 195 static freq_info PM11_LV_130[] = { 196 /* 130 nm 1.10GHz Low Voltage Pentium M */ 197 FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 198 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 199 FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 200 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 201 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 202 FREQ_INFO( 0, 0, 1), 203 }; 204 static freq_info PM11_ULV_130[] = { 205 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 206 FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 207 FREQ_INFO(1000, 988, INTEL_BUS_CLK), 208 FREQ_INFO( 900, 972, INTEL_BUS_CLK), 209 FREQ_INFO( 800, 956, INTEL_BUS_CLK), 210 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 211 FREQ_INFO( 0, 0, 1), 212 }; 213 static freq_info PM10_ULV_130[] = { 214 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 215 FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 216 FREQ_INFO( 900, 988, INTEL_BUS_CLK), 217 FREQ_INFO( 800, 972, INTEL_BUS_CLK), 218 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 219 FREQ_INFO( 0, 0, 1), 220 }; 221 222 /* 223 * Data from "Intel Pentium M Processor on 90nm Process with 224 * 2-MB L2 Cache Datasheet", Order Number 302189-008, Table 5. 225 */ 226 static freq_info PM_765A_90[] = { 227 /* 90 nm 2.10GHz Pentium M, VID #A */ 228 FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 229 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 230 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 231 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 232 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 233 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 234 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 235 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 236 FREQ_INFO( 0, 0, 1), 237 }; 238 static freq_info PM_765B_90[] = { 239 /* 90 nm 2.10GHz Pentium M, VID #B */ 240 FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 241 FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 242 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 243 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 244 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 245 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 246 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 247 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 248 FREQ_INFO( 0, 0, 1), 249 }; 250 static freq_info PM_765C_90[] = { 251 /* 90 nm 2.10GHz Pentium M, VID #C */ 252 FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 253 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 254 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 255 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 256 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 257 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 258 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 259 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 260 FREQ_INFO( 0, 0, 1), 261 }; 262 static freq_info PM_765E_90[] = { 263 /* 90 nm 2.10GHz Pentium M, VID #E */ 264 FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 265 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 266 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 267 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 268 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 269 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 270 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 271 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 272 FREQ_INFO( 0, 0, 1), 273 }; 274 static freq_info PM_755A_90[] = { 275 /* 90 nm 2.00GHz Pentium M, VID #A */ 276 FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 277 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 278 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 279 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 280 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 281 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 282 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 283 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 284 FREQ_INFO( 0, 0, 1), 285 }; 286 static freq_info PM_755B_90[] = { 287 /* 90 nm 2.00GHz Pentium M, VID #B */ 288 FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 289 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 290 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 291 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 292 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 293 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 294 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 295 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 296 FREQ_INFO( 0, 0, 1), 297 }; 298 static freq_info PM_755C_90[] = { 299 /* 90 nm 2.00GHz Pentium M, VID #C */ 300 FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 301 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 302 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 303 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 304 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 305 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 306 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 307 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 308 FREQ_INFO( 0, 0, 1), 309 }; 310 static freq_info PM_755D_90[] = { 311 /* 90 nm 2.00GHz Pentium M, VID #D */ 312 FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 313 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 314 FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 315 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 316 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 317 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 318 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 319 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 320 FREQ_INFO( 0, 0, 1), 321 }; 322 static freq_info PM_745A_90[] = { 323 /* 90 nm 1.80GHz Pentium M, VID #A */ 324 FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 325 FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 326 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 327 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 328 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 329 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 330 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 331 FREQ_INFO( 0, 0, 1), 332 }; 333 static freq_info PM_745B_90[] = { 334 /* 90 nm 1.80GHz Pentium M, VID #B */ 335 FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 336 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 337 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 338 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 339 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 340 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 341 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 342 FREQ_INFO( 0, 0, 1), 343 }; 344 static freq_info PM_745C_90[] = { 345 /* 90 nm 1.80GHz Pentium M, VID #C */ 346 FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 347 FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 348 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 349 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 350 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 351 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 352 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 353 FREQ_INFO( 0, 0, 1), 354 }; 355 static freq_info PM_745D_90[] = { 356 /* 90 nm 1.80GHz Pentium M, VID #D */ 357 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 358 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 359 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 360 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 361 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 362 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 363 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 364 FREQ_INFO( 0, 0, 1), 365 }; 366 static freq_info PM_735A_90[] = { 367 /* 90 nm 1.70GHz Pentium M, VID #A */ 368 FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 369 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 370 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 371 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 372 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 373 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 374 FREQ_INFO( 0, 0, 1), 375 }; 376 static freq_info PM_735B_90[] = { 377 /* 90 nm 1.70GHz Pentium M, VID #B */ 378 FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 379 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 380 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 381 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 382 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 383 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 384 FREQ_INFO( 0, 0, 1), 385 }; 386 static freq_info PM_735C_90[] = { 387 /* 90 nm 1.70GHz Pentium M, VID #C */ 388 FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 389 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 390 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 391 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 392 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 393 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 394 FREQ_INFO( 0, 0, 1), 395 }; 396 static freq_info PM_735D_90[] = { 397 /* 90 nm 1.70GHz Pentium M, VID #D */ 398 FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 399 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 400 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 401 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 402 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 403 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 404 FREQ_INFO( 0, 0, 1), 405 }; 406 static freq_info PM_725A_90[] = { 407 /* 90 nm 1.60GHz Pentium M, VID #A */ 408 FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 409 FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 410 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 411 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 412 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 413 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 414 FREQ_INFO( 0, 0, 1), 415 }; 416 static freq_info PM_725B_90[] = { 417 /* 90 nm 1.60GHz Pentium M, VID #B */ 418 FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 419 FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 420 FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 421 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 422 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 423 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 424 FREQ_INFO( 0, 0, 1), 425 }; 426 static freq_info PM_725C_90[] = { 427 /* 90 nm 1.60GHz Pentium M, VID #C */ 428 FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 429 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 430 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 431 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 432 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 433 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 434 FREQ_INFO( 0, 0, 1), 435 }; 436 static freq_info PM_725D_90[] = { 437 /* 90 nm 1.60GHz Pentium M, VID #D */ 438 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 439 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 440 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 441 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 442 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 443 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 444 FREQ_INFO( 0, 0, 1), 445 }; 446 static freq_info PM_715A_90[] = { 447 /* 90 nm 1.50GHz Pentium M, VID #A */ 448 FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 449 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 450 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 451 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 452 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 453 FREQ_INFO( 0, 0, 1), 454 }; 455 static freq_info PM_715B_90[] = { 456 /* 90 nm 1.50GHz Pentium M, VID #B */ 457 FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 458 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 459 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 460 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 461 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 462 FREQ_INFO( 0, 0, 1), 463 }; 464 static freq_info PM_715C_90[] = { 465 /* 90 nm 1.50GHz Pentium M, VID #C */ 466 FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 467 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 468 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 469 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 470 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 471 FREQ_INFO( 0, 0, 1), 472 }; 473 static freq_info PM_715D_90[] = { 474 /* 90 nm 1.50GHz Pentium M, VID #D */ 475 FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 476 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 477 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 478 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 479 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 480 FREQ_INFO( 0, 0, 1), 481 }; 482 static freq_info PM_778_90[] = { 483 /* 90 nm 1.60GHz Low Voltage Pentium M */ 484 FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 485 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 486 FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 487 FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 488 FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 489 FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 490 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 491 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 492 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 493 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 494 FREQ_INFO( 0, 0, 1), 495 }; 496 static freq_info PM_758_90[] = { 497 /* 90 nm 1.50GHz Low Voltage Pentium M */ 498 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 499 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 500 FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 501 FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 502 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 503 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 504 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 505 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 506 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 507 FREQ_INFO( 0, 0, 1), 508 }; 509 static freq_info PM_738_90[] = { 510 /* 90 nm 1.40GHz Low Voltage Pentium M */ 511 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 512 FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 513 FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 514 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 515 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 516 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 517 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 518 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 519 FREQ_INFO( 0, 0, 1), 520 }; 521 static freq_info PM_773G_90[] = { 522 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 523 FREQ_INFO(1300, 956, INTEL_BUS_CLK), 524 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 525 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 526 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 527 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 528 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 529 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 530 }; 531 static freq_info PM_773H_90[] = { 532 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 533 FREQ_INFO(1300, 940, INTEL_BUS_CLK), 534 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 535 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 536 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 537 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 538 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 539 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 540 }; 541 static freq_info PM_773I_90[] = { 542 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 543 FREQ_INFO(1300, 924, INTEL_BUS_CLK), 544 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 545 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 546 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 547 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 548 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 549 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 550 }; 551 static freq_info PM_773J_90[] = { 552 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 553 FREQ_INFO(1300, 908, INTEL_BUS_CLK), 554 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 555 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 556 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 557 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 558 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 559 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 560 }; 561 static freq_info PM_773K_90[] = { 562 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 563 FREQ_INFO(1300, 892, INTEL_BUS_CLK), 564 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 565 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 566 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 567 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 568 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 569 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 570 }; 571 static freq_info PM_773L_90[] = { 572 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 573 FREQ_INFO(1300, 876, INTEL_BUS_CLK), 574 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 575 FREQ_INFO(1100, 860, INTEL_BUS_CLK), 576 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 577 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 578 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 579 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 580 }; 581 static freq_info PM_753G_90[] = { 582 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 583 FREQ_INFO(1200, 956, INTEL_BUS_CLK), 584 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 585 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 586 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 587 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 588 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 589 }; 590 static freq_info PM_753H_90[] = { 591 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 592 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 593 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 594 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 595 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 596 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 597 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 598 }; 599 static freq_info PM_753I_90[] = { 600 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 601 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 602 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 603 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 604 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 605 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 606 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 607 }; 608 static freq_info PM_753J_90[] = { 609 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 610 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 611 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 612 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 613 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 614 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 615 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 616 }; 617 static freq_info PM_753K_90[] = { 618 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 619 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 620 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 621 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 622 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 623 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 624 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 625 }; 626 static freq_info PM_753L_90[] = { 627 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 628 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 629 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 630 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 631 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 632 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 633 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 634 }; 635 636 static freq_info PM_733JG_90[] = { 637 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 638 FREQ_INFO(1100, 956, INTEL_BUS_CLK), 639 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 640 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 641 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 642 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 643 }; 644 static freq_info PM_733JH_90[] = { 645 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 646 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 647 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 648 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 649 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 650 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 651 }; 652 static freq_info PM_733JI_90[] = { 653 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 654 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 655 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 656 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 657 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 658 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 659 }; 660 static freq_info PM_733JJ_90[] = { 661 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 662 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 663 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 664 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 665 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 666 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 667 }; 668 static freq_info PM_733JK_90[] = { 669 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 670 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 671 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 672 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 673 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 674 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 675 }; 676 static freq_info PM_733JL_90[] = { 677 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 678 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 679 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 680 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 681 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 682 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 683 }; 684 static freq_info PM_733_90[] = { 685 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 686 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 687 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 688 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 689 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 690 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 691 FREQ_INFO( 0, 0, 1), 692 }; 693 static freq_info PM_723_90[] = { 694 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 695 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 696 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 697 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 698 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 699 FREQ_INFO( 0, 0, 1), 700 }; 701 702 /* 703 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 704 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 705 */ 706 static freq_info C7M_795[] = { 707 /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 708 FREQ_INFO_PWR(2000, 1148, 133, 20000), 709 FREQ_INFO_PWR(1867, 1132, 133, 18000), 710 FREQ_INFO_PWR(1600, 1100, 133, 15000), 711 FREQ_INFO_PWR(1467, 1052, 133, 13000), 712 FREQ_INFO_PWR(1200, 1004, 133, 10000), 713 FREQ_INFO_PWR( 800, 844, 133, 7000), 714 FREQ_INFO_PWR( 667, 844, 133, 6000), 715 FREQ_INFO_PWR( 533, 844, 133, 5000), 716 FREQ_INFO(0, 0, 1), 717 }; 718 static freq_info C7M_785[] = { 719 /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 720 FREQ_INFO_PWR(1867, 1148, 133, 18000), 721 FREQ_INFO_PWR(1600, 1100, 133, 15000), 722 FREQ_INFO_PWR(1467, 1052, 133, 13000), 723 FREQ_INFO_PWR(1200, 1004, 133, 10000), 724 FREQ_INFO_PWR( 800, 844, 133, 7000), 725 FREQ_INFO_PWR( 667, 844, 133, 6000), 726 FREQ_INFO_PWR( 533, 844, 133, 5000), 727 FREQ_INFO(0, 0, 1), 728 }; 729 static freq_info C7M_765[] = { 730 /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 731 FREQ_INFO_PWR(1600, 1084, 133, 15000), 732 FREQ_INFO_PWR(1467, 1052, 133, 13000), 733 FREQ_INFO_PWR(1200, 1004, 133, 10000), 734 FREQ_INFO_PWR( 800, 844, 133, 7000), 735 FREQ_INFO_PWR( 667, 844, 133, 6000), 736 FREQ_INFO_PWR( 533, 844, 133, 5000), 737 FREQ_INFO(0, 0, 1), 738 }; 739 740 static freq_info C7M_794[] = { 741 /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 742 FREQ_INFO_PWR(2000, 1148, 100, 20000), 743 FREQ_INFO_PWR(1800, 1132, 100, 18000), 744 FREQ_INFO_PWR(1600, 1100, 100, 15000), 745 FREQ_INFO_PWR(1400, 1052, 100, 13000), 746 FREQ_INFO_PWR(1000, 1004, 100, 10000), 747 FREQ_INFO_PWR( 800, 844, 100, 7000), 748 FREQ_INFO_PWR( 600, 844, 100, 6000), 749 FREQ_INFO_PWR( 400, 844, 100, 5000), 750 FREQ_INFO(0, 0, 1), 751 }; 752 static freq_info C7M_784[] = { 753 /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 754 FREQ_INFO_PWR(1800, 1148, 100, 18000), 755 FREQ_INFO_PWR(1600, 1100, 100, 15000), 756 FREQ_INFO_PWR(1400, 1052, 100, 13000), 757 FREQ_INFO_PWR(1000, 1004, 100, 10000), 758 FREQ_INFO_PWR( 800, 844, 100, 7000), 759 FREQ_INFO_PWR( 600, 844, 100, 6000), 760 FREQ_INFO_PWR( 400, 844, 100, 5000), 761 FREQ_INFO(0, 0, 1), 762 }; 763 static freq_info C7M_764[] = { 764 /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 765 FREQ_INFO_PWR(1600, 1084, 100, 15000), 766 FREQ_INFO_PWR(1400, 1052, 100, 13000), 767 FREQ_INFO_PWR(1000, 1004, 100, 10000), 768 FREQ_INFO_PWR( 800, 844, 100, 7000), 769 FREQ_INFO_PWR( 600, 844, 100, 6000), 770 FREQ_INFO_PWR( 400, 844, 100, 5000), 771 FREQ_INFO(0, 0, 1), 772 }; 773 static freq_info C7M_754[] = { 774 /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 775 FREQ_INFO_PWR(1500, 1004, 100, 12000), 776 FREQ_INFO_PWR(1400, 988, 100, 11000), 777 FREQ_INFO_PWR(1000, 940, 100, 9000), 778 FREQ_INFO_PWR( 800, 844, 100, 7000), 779 FREQ_INFO_PWR( 600, 844, 100, 6000), 780 FREQ_INFO_PWR( 400, 844, 100, 5000), 781 FREQ_INFO(0, 0, 1), 782 }; 783 static freq_info C7M_771[] = { 784 /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 785 FREQ_INFO_PWR(1200, 860, 100, 7000), 786 FREQ_INFO_PWR(1000, 860, 100, 6000), 787 FREQ_INFO_PWR( 800, 844, 100, 5500), 788 FREQ_INFO_PWR( 600, 844, 100, 5000), 789 FREQ_INFO_PWR( 400, 844, 100, 4000), 790 FREQ_INFO(0, 0, 1), 791 }; 792 793 static freq_info C7M_775_ULV[] = { 794 /* 1.50GHz Centaur C7-M ULV */ 795 FREQ_INFO_PWR(1500, 956, 100, 7500), 796 FREQ_INFO_PWR(1400, 940, 100, 6000), 797 FREQ_INFO_PWR(1000, 860, 100, 5000), 798 FREQ_INFO_PWR( 800, 828, 100, 2800), 799 FREQ_INFO_PWR( 600, 796, 100, 2500), 800 FREQ_INFO_PWR( 400, 796, 100, 2000), 801 FREQ_INFO(0, 0, 1), 802 }; 803 static freq_info C7M_772_ULV[] = { 804 /* 1.20GHz Centaur C7-M ULV */ 805 FREQ_INFO_PWR(1200, 844, 100, 5000), 806 FREQ_INFO_PWR(1000, 844, 100, 4000), 807 FREQ_INFO_PWR( 800, 828, 100, 2800), 808 FREQ_INFO_PWR( 600, 796, 100, 2500), 809 FREQ_INFO_PWR( 400, 796, 100, 2000), 810 FREQ_INFO(0, 0, 1), 811 }; 812 static freq_info C7M_779_ULV[] = { 813 /* 1.00GHz Centaur C7-M ULV */ 814 FREQ_INFO_PWR(1000, 796, 100, 3500), 815 FREQ_INFO_PWR( 800, 796, 100, 2800), 816 FREQ_INFO_PWR( 600, 796, 100, 2500), 817 FREQ_INFO_PWR( 400, 796, 100, 2000), 818 FREQ_INFO(0, 0, 1), 819 }; 820 static freq_info C7M_770_ULV[] = { 821 /* 1.00GHz Centaur C7-M ULV */ 822 FREQ_INFO_PWR(1000, 844, 100, 5000), 823 FREQ_INFO_PWR( 800, 796, 100, 2800), 824 FREQ_INFO_PWR( 600, 796, 100, 2500), 825 FREQ_INFO_PWR( 400, 796, 100, 2000), 826 FREQ_INFO(0, 0, 1), 827 }; 828 829 static cpu_info ESTprocs[] = { 830 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 831 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 832 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 833 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 834 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 835 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 836 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 837 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 838 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 839 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 840 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 841 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 842 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 843 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 844 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 845 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 846 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 847 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 848 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 849 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 850 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 851 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 852 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 853 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 854 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 855 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 856 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 857 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 858 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 859 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 860 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 861 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 862 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 863 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 864 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 865 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 866 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 867 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 868 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 869 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 870 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 871 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 872 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 873 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 874 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 875 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 876 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 877 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 878 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 879 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 880 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 881 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 882 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 883 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 884 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 885 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 886 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 887 888 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 889 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 890 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 891 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 892 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 893 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 894 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 895 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 896 CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 897 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 898 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 899 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 900 { 0, 0, NULL }, 901 }; 902 903 static void est_identify(driver_t *driver, device_t parent); 904 static int est_features(driver_t *driver, u_int *features); 905 static int est_probe(device_t parent); 906 static int est_attach(device_t parent); 907 static int est_detach(device_t parent); 908 static int est_get_info(device_t dev); 909 static int est_acpi_info(device_t dev, freq_info **freqs); 910 static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); 911 static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs); 912 static freq_info *est_get_current(freq_info *freq_list); 913 static int est_settings(device_t dev, struct cf_setting *sets, int *count); 914 static int est_set(device_t dev, const struct cf_setting *set); 915 static int est_get(device_t dev, struct cf_setting *set); 916 static int est_type(device_t dev, int *type); 917 static int est_set_id16(device_t dev, uint16_t id16, int need_check); 918 static void est_get_id16(uint16_t *id16_p); 919 920 static device_method_t est_methods[] = { 921 /* Device interface */ 922 DEVMETHOD(device_identify, est_identify), 923 DEVMETHOD(device_probe, est_probe), 924 DEVMETHOD(device_attach, est_attach), 925 DEVMETHOD(device_detach, est_detach), 926 927 /* cpufreq interface */ 928 DEVMETHOD(cpufreq_drv_set, est_set), 929 DEVMETHOD(cpufreq_drv_get, est_get), 930 DEVMETHOD(cpufreq_drv_type, est_type), 931 DEVMETHOD(cpufreq_drv_settings, est_settings), 932 933 /* ACPI interface */ 934 DEVMETHOD(acpi_get_features, est_features), 935 936 {0, 0} 937 }; 938 939 static driver_t est_driver = { 940 "est", 941 est_methods, 942 sizeof(struct est_softc), 943 }; 944 945 static devclass_t est_devclass; 946 DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 947 948 static int 949 est_features(driver_t *driver, u_int *features) 950 { 951 952 /* 953 * Notify the ACPI CPU that we support direct access to MSRs. 954 * XXX C1 "I/O then Halt" seems necessary for some broken BIOS. 955 */ 956 *features = ACPI_CAP_PERF_MSRS | ACPI_CAP_C1_IO_HALT; 957 return (0); 958 } 959 960 static void 961 est_identify(driver_t *driver, device_t parent) 962 { 963 device_t child; 964 965 /* Make sure we're not being doubly invoked. */ 966 if (device_find_child(parent, "est", -1) != NULL) 967 return; 968 969 /* Check that CPUID is supported and the vendor is Intel.*/ 970 if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL && 971 cpu_vendor_id != CPU_VENDOR_CENTAUR)) 972 return; 973 974 /* 975 * Check if the CPU supports EST. 976 */ 977 if (!(cpu_feature2 & CPUID2_EST)) 978 return; 979 980 /* 981 * We add a child for each CPU since settings must be performed 982 * on each CPU in the SMP case. 983 */ 984 child = BUS_ADD_CHILD(parent, 10, "est", -1); 985 if (child == NULL) 986 device_printf(parent, "add est child failed\n"); 987 } 988 989 static int 990 est_probe(device_t dev) 991 { 992 device_t perf_dev; 993 uint64_t msr; 994 int error, type; 995 996 if (resource_disabled("est", 0)) 997 return (ENXIO); 998 999 /* 1000 * If the ACPI perf driver has attached and is not just offering 1001 * info, let it manage things. 1002 */ 1003 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1004 if (perf_dev && device_is_attached(perf_dev)) { 1005 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 1006 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 1007 return (ENXIO); 1008 } 1009 1010 /* Attempt to enable SpeedStep if not currently enabled. */ 1011 msr = rdmsr(MSR_MISC_ENABLE); 1012 if ((msr & MSR_SS_ENABLE) == 0) { 1013 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 1014 if (bootverbose) 1015 device_printf(dev, "enabling SpeedStep\n"); 1016 1017 /* Check if the enable failed. */ 1018 msr = rdmsr(MSR_MISC_ENABLE); 1019 if ((msr & MSR_SS_ENABLE) == 0) { 1020 device_printf(dev, "failed to enable SpeedStep\n"); 1021 return (ENXIO); 1022 } 1023 } 1024 1025 device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 1026 return (0); 1027 } 1028 1029 static int 1030 est_attach(device_t dev) 1031 { 1032 struct est_softc *sc; 1033 1034 sc = device_get_softc(dev); 1035 sc->dev = dev; 1036 1037 /* On SMP system we can't guarantie independent freq setting. */ 1038 if (strict == -1 && mp_ncpus > 1) 1039 strict = 0; 1040 /* Check CPU for supported settings. */ 1041 if (est_get_info(dev)) 1042 return (ENXIO); 1043 1044 cpufreq_register(dev); 1045 return (0); 1046 } 1047 1048 static int 1049 est_detach(device_t dev) 1050 { 1051 struct est_softc *sc; 1052 int error; 1053 1054 error = cpufreq_unregister(dev); 1055 if (error) 1056 return (error); 1057 1058 sc = device_get_softc(dev); 1059 if (sc->acpi_settings || sc->msr_settings) 1060 free(sc->freq_list, M_DEVBUF); 1061 return (0); 1062 } 1063 1064 /* 1065 * Probe for supported CPU settings. First, check our static table of 1066 * settings. If no match, try using the ones offered by acpi_perf 1067 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1068 * series) export both legacy SMM IO-based access and direct MSR access 1069 * but the direct access specifies invalid values for _PSS. 1070 */ 1071 static int 1072 est_get_info(device_t dev) 1073 { 1074 struct est_softc *sc; 1075 uint64_t msr; 1076 int error; 1077 1078 sc = device_get_softc(dev); 1079 msr = rdmsr(MSR_PERF_STATUS); 1080 error = est_table_info(dev, msr, &sc->freq_list); 1081 if (error) 1082 error = est_acpi_info(dev, &sc->freq_list); 1083 if (error) 1084 error = est_msr_info(dev, msr, &sc->freq_list); 1085 1086 if (error) { 1087 printf( 1088 "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1089 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1090 return (ENXIO); 1091 } 1092 1093 return (0); 1094 } 1095 1096 static int 1097 est_acpi_info(device_t dev, freq_info **freqs) 1098 { 1099 struct est_softc *sc; 1100 struct cf_setting *sets; 1101 freq_info *table; 1102 device_t perf_dev; 1103 int count, error, i, j; 1104 uint16_t saved_id16; 1105 1106 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1107 if (perf_dev == NULL || !device_is_attached(perf_dev)) 1108 return (ENXIO); 1109 1110 /* Fetch settings from acpi_perf. */ 1111 sc = device_get_softc(dev); 1112 table = NULL; 1113 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1114 if (sets == NULL) 1115 return (ENOMEM); 1116 count = MAX_SETTINGS; 1117 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1118 if (error) 1119 goto out; 1120 1121 /* Parse settings into our local table format. */ 1122 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 1123 if (table == NULL) { 1124 error = ENOMEM; 1125 goto out; 1126 } 1127 est_get_id16(&saved_id16); 1128 for (i = 0, j = 0; i < count; i++) { 1129 /* 1130 * Confirm id16 value is correct. 1131 */ 1132 if (sets[i].freq > 0) { 1133 error = est_set_id16(dev, sets[i].spec[0], strict); 1134 if (error != 0) { 1135 if (bootverbose) 1136 device_printf(dev, "Invalid freq %u, " 1137 "ignored.\n", sets[i].freq); 1138 continue; 1139 } 1140 table[j].freq = sets[i].freq; 1141 table[j].volts = sets[i].volts; 1142 table[j].id16 = sets[i].spec[0]; 1143 table[j].power = sets[i].power; 1144 ++j; 1145 } 1146 } 1147 /* restore saved setting */ 1148 est_set_id16(dev, saved_id16, 0); 1149 1150 /* Mark end of table with a terminator. */ 1151 bzero(&table[j], sizeof(freq_info)); 1152 1153 sc->acpi_settings = TRUE; 1154 *freqs = table; 1155 error = 0; 1156 1157 out: 1158 if (sets) 1159 free(sets, M_TEMP); 1160 if (error && table) 1161 free(table, M_DEVBUF); 1162 return (error); 1163 } 1164 1165 static int 1166 est_table_info(device_t dev, uint64_t msr, freq_info **freqs) 1167 { 1168 cpu_info *p; 1169 uint32_t id; 1170 1171 /* Find a table which matches (vendor, id32). */ 1172 id = msr >> 32; 1173 for (p = ESTprocs; p->id32 != 0; p++) { 1174 if (p->vendor_id == cpu_vendor_id && p->id32 == id) 1175 break; 1176 } 1177 if (p->id32 == 0) 1178 return (EOPNOTSUPP); 1179 1180 /* Make sure the current setpoint is valid. */ 1181 if (est_get_current(p->freqtab) == NULL) { 1182 device_printf(dev, "current setting not found in table\n"); 1183 return (EOPNOTSUPP); 1184 } 1185 1186 *freqs = p->freqtab; 1187 return (0); 1188 } 1189 1190 static int 1191 bus_speed_ok(int bus) 1192 { 1193 1194 switch (bus) { 1195 case 100: 1196 case 133: 1197 case 333: 1198 return (1); 1199 default: 1200 return (0); 1201 } 1202 } 1203 1204 /* 1205 * Flesh out a simple rate table containing the high and low frequencies 1206 * based on the current clock speed and the upper 32 bits of the MSR. 1207 */ 1208 static int 1209 est_msr_info(device_t dev, uint64_t msr, freq_info **freqs) 1210 { 1211 struct est_softc *sc; 1212 freq_info *fp; 1213 int bus, freq, volts; 1214 uint16_t id; 1215 1216 if (!msr_info_enabled) 1217 return (EOPNOTSUPP); 1218 1219 /* Figure out the bus clock. */ 1220 freq = atomic_load_acq_64(&tsc_freq) / 1000000; 1221 id = msr >> 32; 1222 bus = freq / (id >> 8); 1223 device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus); 1224 if (!bus_speed_ok(bus)) { 1225 /* We may be running on the low frequency. */ 1226 id = msr >> 48; 1227 bus = freq / (id >> 8); 1228 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus); 1229 if (!bus_speed_ok(bus)) 1230 return (EOPNOTSUPP); 1231 1232 /* Calculate high frequency. */ 1233 id = msr >> 32; 1234 freq = ((id >> 8) & 0xff) * bus; 1235 } 1236 1237 /* Fill out a new freq table containing just the high and low freqs. */ 1238 sc = device_get_softc(dev); 1239 fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO); 1240 1241 /* First, the high frequency. */ 1242 volts = id & 0xff; 1243 if (volts != 0) { 1244 volts <<= 4; 1245 volts += 700; 1246 } 1247 fp[0].freq = freq; 1248 fp[0].volts = volts; 1249 fp[0].id16 = id; 1250 fp[0].power = CPUFREQ_VAL_UNKNOWN; 1251 device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq, 1252 volts); 1253 1254 /* Second, the low frequency. */ 1255 id = msr >> 48; 1256 freq = ((id >> 8) & 0xff) * bus; 1257 volts = id & 0xff; 1258 if (volts != 0) { 1259 volts <<= 4; 1260 volts += 700; 1261 } 1262 fp[1].freq = freq; 1263 fp[1].volts = volts; 1264 fp[1].id16 = id; 1265 fp[1].power = CPUFREQ_VAL_UNKNOWN; 1266 device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq, 1267 volts); 1268 1269 /* Table is already terminated due to M_ZERO. */ 1270 sc->msr_settings = TRUE; 1271 *freqs = fp; 1272 return (0); 1273 } 1274 1275 static void 1276 est_get_id16(uint16_t *id16_p) 1277 { 1278 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1279 } 1280 1281 static int 1282 est_set_id16(device_t dev, uint16_t id16, int need_check) 1283 { 1284 uint64_t msr; 1285 uint16_t new_id16; 1286 int ret = 0; 1287 1288 /* Read the current register, mask out the old, set the new id. */ 1289 msr = rdmsr(MSR_PERF_CTL); 1290 msr = (msr & ~0xffff) | id16; 1291 wrmsr(MSR_PERF_CTL, msr); 1292 1293 if (need_check) { 1294 /* Wait a short while and read the new status. */ 1295 DELAY(EST_TRANS_LAT); 1296 est_get_id16(&new_id16); 1297 if (new_id16 != id16) { 1298 if (bootverbose) 1299 device_printf(dev, "Invalid id16 (set, cur) " 1300 "= (%u, %u)\n", id16, new_id16); 1301 ret = ENXIO; 1302 } 1303 } 1304 return (ret); 1305 } 1306 1307 static freq_info * 1308 est_get_current(freq_info *freq_list) 1309 { 1310 freq_info *f; 1311 int i; 1312 uint16_t id16; 1313 1314 /* 1315 * Try a few times to get a valid value. Sometimes, if the CPU 1316 * is in the middle of an asynchronous transition (i.e., P4TCC), 1317 * we get a temporary invalid result. 1318 */ 1319 for (i = 0; i < 5; i++) { 1320 est_get_id16(&id16); 1321 for (f = freq_list; f->id16 != 0; f++) { 1322 if (f->id16 == id16) 1323 return (f); 1324 } 1325 DELAY(100); 1326 } 1327 return (NULL); 1328 } 1329 1330 static int 1331 est_settings(device_t dev, struct cf_setting *sets, int *count) 1332 { 1333 struct est_softc *sc; 1334 freq_info *f; 1335 int i; 1336 1337 sc = device_get_softc(dev); 1338 if (*count < EST_MAX_SETTINGS) 1339 return (E2BIG); 1340 1341 i = 0; 1342 for (f = sc->freq_list; f->freq != 0; f++, i++) { 1343 sets[i].freq = f->freq; 1344 sets[i].volts = f->volts; 1345 sets[i].power = f->power; 1346 sets[i].lat = EST_TRANS_LAT; 1347 sets[i].dev = dev; 1348 } 1349 *count = i; 1350 1351 return (0); 1352 } 1353 1354 static int 1355 est_set(device_t dev, const struct cf_setting *set) 1356 { 1357 struct est_softc *sc; 1358 freq_info *f; 1359 1360 /* Find the setting matching the requested one. */ 1361 sc = device_get_softc(dev); 1362 for (f = sc->freq_list; f->freq != 0; f++) { 1363 if (f->freq == set->freq) 1364 break; 1365 } 1366 if (f->freq == 0) 1367 return (EINVAL); 1368 1369 /* Read the current register, mask out the old, set the new id. */ 1370 est_set_id16(dev, f->id16, 0); 1371 1372 return (0); 1373 } 1374 1375 static int 1376 est_get(device_t dev, struct cf_setting *set) 1377 { 1378 struct est_softc *sc; 1379 freq_info *f; 1380 1381 sc = device_get_softc(dev); 1382 f = est_get_current(sc->freq_list); 1383 if (f == NULL) 1384 return (ENXIO); 1385 1386 set->freq = f->freq; 1387 set->volts = f->volts; 1388 set->power = f->power; 1389 set->lat = EST_TRANS_LAT; 1390 set->dev = dev; 1391 return (0); 1392 } 1393 1394 static int 1395 est_type(device_t dev, int *type) 1396 { 1397 1398 if (type == NULL) 1399 return (EINVAL); 1400 1401 *type = CPUFREQ_TYPE_ABSOLUTE; 1402 return (0); 1403 } 1404