1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004 Colin Percival 5 * Copyright (c) 2005 Nate Lawson 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted providing that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 21 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/cpu.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/module.h> 36 #include <sys/smp.h> 37 #include <sys/systm.h> 38 39 #include "cpufreq_if.h" 40 #include <machine/clock.h> 41 #include <machine/cputypes.h> 42 #include <machine/md_var.h> 43 #include <machine/specialreg.h> 44 45 #include <contrib/dev/acpica/include/acpi.h> 46 47 #include <dev/acpica/acpivar.h> 48 #include "acpi_if.h" 49 50 #include <x86/cpufreq/hwpstate_intel_internal.h> 51 52 /* Status/control registers (from the IA-32 System Programming Guide). */ 53 #define MSR_PERF_STATUS 0x198 54 #define MSR_PERF_CTL 0x199 55 56 /* Register and bit for enabling SpeedStep. */ 57 #define MSR_MISC_ENABLE 0x1a0 58 #define MSR_SS_ENABLE (1<<16) 59 60 /* Frequency and MSR control values. */ 61 typedef struct { 62 uint16_t freq; 63 uint16_t volts; 64 uint16_t id16; 65 int power; 66 } freq_info; 67 68 /* Identifying characteristics of a processor and supported frequencies. */ 69 typedef struct { 70 const u_int vendor_id; 71 uint32_t id32; 72 freq_info *freqtab; 73 size_t tablen; 74 } cpu_info; 75 76 struct est_softc { 77 device_t dev; 78 int acpi_settings; 79 int msr_settings; 80 freq_info *freq_list; 81 size_t flist_len; 82 }; 83 84 /* Convert MHz and mV into IDs for passing to the MSR. */ 85 #define ID16(MHz, mV, bus_clk) \ 86 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 87 #define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 88 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 89 90 /* Format for storing IDs in our table. */ 91 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 92 { MHz, mV, ID16(MHz, mV, bus_clk), mW } 93 #define FREQ_INFO(MHz, mV, bus_clk) \ 94 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 95 #define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 96 { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab, nitems(tab) } 97 #define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 98 { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab, nitems(tab) } 99 100 static int msr_info_enabled = 0; 101 TUNABLE_INT("hw.est.msr_info", &msr_info_enabled); 102 static int strict = -1; 103 TUNABLE_INT("hw.est.strict", &strict); 104 105 /* Default bus clock value for Centrino processors. */ 106 #define INTEL_BUS_CLK 100 107 108 /* XXX Update this if new CPUs have more settings. */ 109 #define EST_MAX_SETTINGS 10 110 CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 111 112 /* Estimate in microseconds of latency for performing a transition. */ 113 #define EST_TRANS_LAT 1000 114 115 /* 116 * Frequency (MHz) and voltage (mV) settings. 117 * 118 * Dothan processors have multiple VID#s with different settings for 119 * each VID#. Since we can't uniquely identify this info 120 * without undisclosed methods from Intel, we can't support newer 121 * processors with this table method. If ACPI Px states are supported, 122 * we get info from them. 123 * 124 * Data from the "Intel Pentium M Processor Datasheet", 125 * Order Number 252612-003, Table 5. 126 */ 127 static freq_info PM17_130[] = { 128 /* 130nm 1.70GHz Pentium M */ 129 FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 130 FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 131 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 132 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 133 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 134 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 135 }; 136 static freq_info PM16_130[] = { 137 /* 130nm 1.60GHz Pentium M */ 138 FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 139 FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 140 FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 141 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 142 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 143 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 144 }; 145 static freq_info PM15_130[] = { 146 /* 130nm 1.50GHz Pentium M */ 147 FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 148 FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 149 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 150 FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 151 FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 152 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 153 }; 154 static freq_info PM14_130[] = { 155 /* 130nm 1.40GHz Pentium M */ 156 FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 157 FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 158 FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 159 FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 160 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 161 }; 162 static freq_info PM13_130[] = { 163 /* 130nm 1.30GHz Pentium M */ 164 FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 165 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 166 FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 167 FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 168 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 169 }; 170 static freq_info PM13_LV_130[] = { 171 /* 130nm 1.30GHz Low Voltage Pentium M */ 172 FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 173 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 174 FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 175 FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 176 FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 177 FREQ_INFO( 800, 988, INTEL_BUS_CLK), 178 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 179 }; 180 static freq_info PM12_LV_130[] = { 181 /* 130 nm 1.20GHz Low Voltage Pentium M */ 182 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 183 FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 184 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 185 FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 186 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 187 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 188 }; 189 static freq_info PM11_LV_130[] = { 190 /* 130 nm 1.10GHz Low Voltage Pentium M */ 191 FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 192 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 193 FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 194 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 195 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 196 }; 197 static freq_info PM11_ULV_130[] = { 198 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 199 FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 200 FREQ_INFO(1000, 988, INTEL_BUS_CLK), 201 FREQ_INFO( 900, 972, INTEL_BUS_CLK), 202 FREQ_INFO( 800, 956, INTEL_BUS_CLK), 203 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 204 }; 205 static freq_info PM10_ULV_130[] = { 206 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 207 FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 208 FREQ_INFO( 900, 988, INTEL_BUS_CLK), 209 FREQ_INFO( 800, 972, INTEL_BUS_CLK), 210 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 211 }; 212 213 /* 214 * Data from "Intel Pentium M Processor on 90nm Process with 215 * 2-MB L2 Cache Datasheet", Order Number 302189-008, Table 5. 216 */ 217 static freq_info PM_765A_90[] = { 218 /* 90 nm 2.10GHz Pentium M, VID #A */ 219 FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 220 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 221 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 222 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 223 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 224 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 225 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 226 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 227 }; 228 static freq_info PM_765B_90[] = { 229 /* 90 nm 2.10GHz Pentium M, VID #B */ 230 FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 231 FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 232 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 233 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 234 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 235 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 236 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 237 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 238 }; 239 static freq_info PM_765C_90[] = { 240 /* 90 nm 2.10GHz Pentium M, VID #C */ 241 FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 242 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 243 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 244 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 245 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 246 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 247 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 248 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 249 }; 250 static freq_info PM_765E_90[] = { 251 /* 90 nm 2.10GHz Pentium M, VID #E */ 252 FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 253 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 254 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 255 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 256 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 257 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 258 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 259 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 260 }; 261 static freq_info PM_755A_90[] = { 262 /* 90 nm 2.00GHz Pentium M, VID #A */ 263 FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 264 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 265 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 266 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 267 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 268 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 269 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 270 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 271 }; 272 static freq_info PM_755B_90[] = { 273 /* 90 nm 2.00GHz Pentium M, VID #B */ 274 FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 275 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 276 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 277 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 278 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 279 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 280 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 281 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 282 }; 283 static freq_info PM_755C_90[] = { 284 /* 90 nm 2.00GHz Pentium M, VID #C */ 285 FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 286 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 287 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 288 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 289 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 290 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 291 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 292 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 293 }; 294 static freq_info PM_755D_90[] = { 295 /* 90 nm 2.00GHz Pentium M, VID #D */ 296 FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 297 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 298 FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 299 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 300 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 301 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 302 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 303 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 304 }; 305 static freq_info PM_745A_90[] = { 306 /* 90 nm 1.80GHz Pentium M, VID #A */ 307 FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 308 FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 309 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 310 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 311 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 312 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 313 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 314 }; 315 static freq_info PM_745B_90[] = { 316 /* 90 nm 1.80GHz Pentium M, VID #B */ 317 FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 318 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 319 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 320 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 321 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 322 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 323 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 324 }; 325 static freq_info PM_745C_90[] = { 326 /* 90 nm 1.80GHz Pentium M, VID #C */ 327 FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 328 FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 329 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 330 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 331 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 332 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 333 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 334 }; 335 static freq_info PM_745D_90[] = { 336 /* 90 nm 1.80GHz Pentium M, VID #D */ 337 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 338 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 339 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 340 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 341 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 342 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 343 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 344 }; 345 static freq_info PM_735A_90[] = { 346 /* 90 nm 1.70GHz Pentium M, VID #A */ 347 FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 348 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 349 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 350 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 351 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 352 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 353 }; 354 static freq_info PM_735B_90[] = { 355 /* 90 nm 1.70GHz Pentium M, VID #B */ 356 FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 357 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 358 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 359 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 360 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 361 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 362 }; 363 static freq_info PM_735C_90[] = { 364 /* 90 nm 1.70GHz Pentium M, VID #C */ 365 FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 366 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 367 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 368 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 369 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 370 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 371 }; 372 static freq_info PM_735D_90[] = { 373 /* 90 nm 1.70GHz Pentium M, VID #D */ 374 FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 375 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 376 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 377 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 378 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 379 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 380 }; 381 static freq_info PM_725A_90[] = { 382 /* 90 nm 1.60GHz Pentium M, VID #A */ 383 FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 384 FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 385 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 386 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 387 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 388 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 389 }; 390 static freq_info PM_725B_90[] = { 391 /* 90 nm 1.60GHz Pentium M, VID #B */ 392 FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 393 FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 394 FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 395 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 396 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 397 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 398 }; 399 static freq_info PM_725C_90[] = { 400 /* 90 nm 1.60GHz Pentium M, VID #C */ 401 FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 402 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 403 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 404 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 405 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 406 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 407 }; 408 static freq_info PM_725D_90[] = { 409 /* 90 nm 1.60GHz Pentium M, VID #D */ 410 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 411 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 412 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 413 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 414 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 415 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 416 }; 417 static freq_info PM_715A_90[] = { 418 /* 90 nm 1.50GHz Pentium M, VID #A */ 419 FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 420 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 421 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 422 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 423 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 424 }; 425 static freq_info PM_715B_90[] = { 426 /* 90 nm 1.50GHz Pentium M, VID #B */ 427 FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 428 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 429 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 430 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 431 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 432 }; 433 static freq_info PM_715C_90[] = { 434 /* 90 nm 1.50GHz Pentium M, VID #C */ 435 FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 436 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 437 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 438 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 439 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 440 }; 441 static freq_info PM_715D_90[] = { 442 /* 90 nm 1.50GHz Pentium M, VID #D */ 443 FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 444 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 445 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 446 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 447 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 448 }; 449 static freq_info PM_778_90[] = { 450 /* 90 nm 1.60GHz Low Voltage Pentium M */ 451 FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 452 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 453 FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 454 FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 455 FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 456 FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 457 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 458 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 459 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 460 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 461 }; 462 static freq_info PM_758_90[] = { 463 /* 90 nm 1.50GHz Low Voltage Pentium M */ 464 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 465 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 466 FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 467 FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 468 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 469 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 470 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 471 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 472 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 473 }; 474 static freq_info PM_738_90[] = { 475 /* 90 nm 1.40GHz Low Voltage Pentium M */ 476 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 477 FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 478 FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 479 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 480 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 481 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 482 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 483 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 484 }; 485 static freq_info PM_773G_90[] = { 486 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 487 FREQ_INFO(1300, 956, INTEL_BUS_CLK), 488 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 489 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 490 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 491 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 492 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 493 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 494 }; 495 static freq_info PM_773H_90[] = { 496 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 497 FREQ_INFO(1300, 940, INTEL_BUS_CLK), 498 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 499 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 500 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 501 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 502 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 503 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 504 }; 505 static freq_info PM_773I_90[] = { 506 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 507 FREQ_INFO(1300, 924, INTEL_BUS_CLK), 508 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 509 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 510 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 511 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 512 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 513 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 514 }; 515 static freq_info PM_773J_90[] = { 516 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 517 FREQ_INFO(1300, 908, INTEL_BUS_CLK), 518 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 519 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 520 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 521 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 522 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 523 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 524 }; 525 static freq_info PM_773K_90[] = { 526 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 527 FREQ_INFO(1300, 892, INTEL_BUS_CLK), 528 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 529 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 530 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 531 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 532 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 533 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 534 }; 535 static freq_info PM_773L_90[] = { 536 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 537 FREQ_INFO(1300, 876, INTEL_BUS_CLK), 538 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 539 FREQ_INFO(1100, 860, INTEL_BUS_CLK), 540 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 541 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 542 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 543 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 544 }; 545 static freq_info PM_753G_90[] = { 546 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 547 FREQ_INFO(1200, 956, INTEL_BUS_CLK), 548 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 549 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 550 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 551 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 552 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 553 }; 554 static freq_info PM_753H_90[] = { 555 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 556 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 557 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 558 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 559 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 560 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 561 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 562 }; 563 static freq_info PM_753I_90[] = { 564 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 565 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 566 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 567 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 568 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 569 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 570 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 571 }; 572 static freq_info PM_753J_90[] = { 573 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 574 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 575 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 576 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 577 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 578 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 579 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 580 }; 581 static freq_info PM_753K_90[] = { 582 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 583 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 584 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 585 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 586 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 587 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 588 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 589 }; 590 static freq_info PM_753L_90[] = { 591 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 592 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 593 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 594 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 595 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 596 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 597 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 598 }; 599 600 static freq_info PM_733JG_90[] = { 601 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 602 FREQ_INFO(1100, 956, INTEL_BUS_CLK), 603 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 604 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 605 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 606 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 607 }; 608 static freq_info PM_733JH_90[] = { 609 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 610 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 611 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 612 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 613 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 614 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 615 }; 616 static freq_info PM_733JI_90[] = { 617 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 618 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 619 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 620 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 621 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 622 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 623 }; 624 static freq_info PM_733JJ_90[] = { 625 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 626 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 627 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 628 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 629 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 630 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 631 }; 632 static freq_info PM_733JK_90[] = { 633 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 634 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 635 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 636 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 637 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 638 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 639 }; 640 static freq_info PM_733JL_90[] = { 641 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 642 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 643 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 644 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 645 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 646 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 647 }; 648 static freq_info PM_733_90[] = { 649 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 650 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 651 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 652 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 653 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 654 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 655 }; 656 static freq_info PM_723_90[] = { 657 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 658 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 659 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 660 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 661 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 662 }; 663 664 /* 665 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 666 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 667 */ 668 static freq_info C7M_795[] = { 669 /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 670 FREQ_INFO_PWR(2000, 1148, 133, 20000), 671 FREQ_INFO_PWR(1867, 1132, 133, 18000), 672 FREQ_INFO_PWR(1600, 1100, 133, 15000), 673 FREQ_INFO_PWR(1467, 1052, 133, 13000), 674 FREQ_INFO_PWR(1200, 1004, 133, 10000), 675 FREQ_INFO_PWR( 800, 844, 133, 7000), 676 FREQ_INFO_PWR( 667, 844, 133, 6000), 677 FREQ_INFO_PWR( 533, 844, 133, 5000), 678 }; 679 static freq_info C7M_785[] = { 680 /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 681 FREQ_INFO_PWR(1867, 1148, 133, 18000), 682 FREQ_INFO_PWR(1600, 1100, 133, 15000), 683 FREQ_INFO_PWR(1467, 1052, 133, 13000), 684 FREQ_INFO_PWR(1200, 1004, 133, 10000), 685 FREQ_INFO_PWR( 800, 844, 133, 7000), 686 FREQ_INFO_PWR( 667, 844, 133, 6000), 687 FREQ_INFO_PWR( 533, 844, 133, 5000), 688 }; 689 static freq_info C7M_765[] = { 690 /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 691 FREQ_INFO_PWR(1600, 1084, 133, 15000), 692 FREQ_INFO_PWR(1467, 1052, 133, 13000), 693 FREQ_INFO_PWR(1200, 1004, 133, 10000), 694 FREQ_INFO_PWR( 800, 844, 133, 7000), 695 FREQ_INFO_PWR( 667, 844, 133, 6000), 696 FREQ_INFO_PWR( 533, 844, 133, 5000), 697 }; 698 699 static freq_info C7M_794[] = { 700 /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 701 FREQ_INFO_PWR(2000, 1148, 100, 20000), 702 FREQ_INFO_PWR(1800, 1132, 100, 18000), 703 FREQ_INFO_PWR(1600, 1100, 100, 15000), 704 FREQ_INFO_PWR(1400, 1052, 100, 13000), 705 FREQ_INFO_PWR(1000, 1004, 100, 10000), 706 FREQ_INFO_PWR( 800, 844, 100, 7000), 707 FREQ_INFO_PWR( 600, 844, 100, 6000), 708 FREQ_INFO_PWR( 400, 844, 100, 5000), 709 }; 710 static freq_info C7M_784[] = { 711 /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 712 FREQ_INFO_PWR(1800, 1148, 100, 18000), 713 FREQ_INFO_PWR(1600, 1100, 100, 15000), 714 FREQ_INFO_PWR(1400, 1052, 100, 13000), 715 FREQ_INFO_PWR(1000, 1004, 100, 10000), 716 FREQ_INFO_PWR( 800, 844, 100, 7000), 717 FREQ_INFO_PWR( 600, 844, 100, 6000), 718 FREQ_INFO_PWR( 400, 844, 100, 5000), 719 }; 720 static freq_info C7M_764[] = { 721 /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 722 FREQ_INFO_PWR(1600, 1084, 100, 15000), 723 FREQ_INFO_PWR(1400, 1052, 100, 13000), 724 FREQ_INFO_PWR(1000, 1004, 100, 10000), 725 FREQ_INFO_PWR( 800, 844, 100, 7000), 726 FREQ_INFO_PWR( 600, 844, 100, 6000), 727 FREQ_INFO_PWR( 400, 844, 100, 5000), 728 }; 729 static freq_info C7M_754[] = { 730 /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 731 FREQ_INFO_PWR(1500, 1004, 100, 12000), 732 FREQ_INFO_PWR(1400, 988, 100, 11000), 733 FREQ_INFO_PWR(1000, 940, 100, 9000), 734 FREQ_INFO_PWR( 800, 844, 100, 7000), 735 FREQ_INFO_PWR( 600, 844, 100, 6000), 736 FREQ_INFO_PWR( 400, 844, 100, 5000), 737 }; 738 static freq_info C7M_771[] = { 739 /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 740 FREQ_INFO_PWR(1200, 860, 100, 7000), 741 FREQ_INFO_PWR(1000, 860, 100, 6000), 742 FREQ_INFO_PWR( 800, 844, 100, 5500), 743 FREQ_INFO_PWR( 600, 844, 100, 5000), 744 FREQ_INFO_PWR( 400, 844, 100, 4000), 745 }; 746 747 static freq_info C7M_775_ULV[] = { 748 /* 1.50GHz Centaur C7-M ULV */ 749 FREQ_INFO_PWR(1500, 956, 100, 7500), 750 FREQ_INFO_PWR(1400, 940, 100, 6000), 751 FREQ_INFO_PWR(1000, 860, 100, 5000), 752 FREQ_INFO_PWR( 800, 828, 100, 2800), 753 FREQ_INFO_PWR( 600, 796, 100, 2500), 754 FREQ_INFO_PWR( 400, 796, 100, 2000), 755 }; 756 static freq_info C7M_772_ULV[] = { 757 /* 1.20GHz Centaur C7-M ULV */ 758 FREQ_INFO_PWR(1200, 844, 100, 5000), 759 FREQ_INFO_PWR(1000, 844, 100, 4000), 760 FREQ_INFO_PWR( 800, 828, 100, 2800), 761 FREQ_INFO_PWR( 600, 796, 100, 2500), 762 FREQ_INFO_PWR( 400, 796, 100, 2000), 763 }; 764 static freq_info C7M_779_ULV[] = { 765 /* 1.00GHz Centaur C7-M ULV */ 766 FREQ_INFO_PWR(1000, 796, 100, 3500), 767 FREQ_INFO_PWR( 800, 796, 100, 2800), 768 FREQ_INFO_PWR( 600, 796, 100, 2500), 769 FREQ_INFO_PWR( 400, 796, 100, 2000), 770 }; 771 static freq_info C7M_770_ULV[] = { 772 /* 1.00GHz Centaur C7-M ULV */ 773 FREQ_INFO_PWR(1000, 844, 100, 5000), 774 FREQ_INFO_PWR( 800, 796, 100, 2800), 775 FREQ_INFO_PWR( 600, 796, 100, 2500), 776 FREQ_INFO_PWR( 400, 796, 100, 2000), 777 }; 778 779 static cpu_info ESTprocs[] = { 780 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 781 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 782 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 783 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 784 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 785 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 786 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 787 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 788 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 789 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 790 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 791 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 792 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 793 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 794 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 795 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 796 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 797 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 798 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 799 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 800 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 801 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 802 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 803 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 804 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 805 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 806 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 807 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 808 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 809 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 810 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 811 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 812 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 813 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 814 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 815 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 816 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 817 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 818 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 819 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 820 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 821 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 822 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 823 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 824 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 825 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 826 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 827 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 828 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 829 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 830 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 831 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 832 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 833 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 834 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 835 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 836 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 837 838 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 839 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 840 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 841 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 842 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 843 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 844 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 845 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 846 CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 847 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 848 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 849 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 850 { 0, 0, NULL }, 851 }; 852 853 static void est_identify(driver_t *driver, device_t parent); 854 static int est_features(driver_t *driver, u_int *features); 855 static int est_probe(device_t parent); 856 static int est_attach(device_t parent); 857 static int est_detach(device_t parent); 858 static int est_get_info(device_t dev); 859 static int est_acpi_info(device_t dev, freq_info **freqs, 860 size_t *freqslen); 861 static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs, 862 size_t *freqslen); 863 static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs, 864 size_t *freqslen); 865 static freq_info *est_get_current(freq_info *freq_list, size_t tablen); 866 static int est_settings(device_t dev, struct cf_setting *sets, int *count); 867 static int est_set(device_t dev, const struct cf_setting *set); 868 static int est_get(device_t dev, struct cf_setting *set); 869 static int est_type(device_t dev, int *type); 870 static int est_set_id16(device_t dev, uint16_t id16, int need_check); 871 static void est_get_id16(uint16_t *id16_p); 872 873 static device_method_t est_methods[] = { 874 /* Device interface */ 875 DEVMETHOD(device_identify, est_identify), 876 DEVMETHOD(device_probe, est_probe), 877 DEVMETHOD(device_attach, est_attach), 878 DEVMETHOD(device_detach, est_detach), 879 880 /* cpufreq interface */ 881 DEVMETHOD(cpufreq_drv_set, est_set), 882 DEVMETHOD(cpufreq_drv_get, est_get), 883 DEVMETHOD(cpufreq_drv_type, est_type), 884 DEVMETHOD(cpufreq_drv_settings, est_settings), 885 886 /* ACPI interface */ 887 DEVMETHOD(acpi_get_features, est_features), 888 {0, 0} 889 }; 890 891 static driver_t est_driver = { 892 "est", 893 est_methods, 894 sizeof(struct est_softc), 895 }; 896 897 DRIVER_MODULE(est, cpu, est_driver, 0, 0); 898 MODULE_DEPEND(est, hwpstate_intel, 1, 1, 1); 899 900 static int 901 est_features(driver_t *driver, u_int *features) 902 { 903 904 /* 905 * Notify the ACPI CPU that we support direct access to MSRs. 906 * XXX C1 "I/O then Halt" seems necessary for some broken BIOS. 907 */ 908 *features = ACPI_CAP_PERF_MSRS | ACPI_CAP_C1_IO_HALT; 909 return (0); 910 } 911 912 static void 913 est_identify(driver_t *driver, device_t parent) 914 { 915 device_t child; 916 917 /* 918 * Defer to hwpstate if it is present. This priority logic 919 * should be replaced with normal newbus probing in the 920 * future. 921 */ 922 intel_hwpstate_identify(NULL, parent); 923 if (device_find_child(parent, "hwpstate_intel", -1) != NULL) 924 return; 925 926 /* Make sure we're not being doubly invoked. */ 927 if (device_find_child(parent, "est", -1) != NULL) 928 return; 929 930 /* Check that CPUID is supported and the vendor is Intel.*/ 931 if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL && 932 cpu_vendor_id != CPU_VENDOR_CENTAUR)) 933 return; 934 935 /* 936 * Check if the CPU supports EST. 937 */ 938 if (!(cpu_feature2 & CPUID2_EST)) 939 return; 940 941 /* 942 * We add a child for each CPU since settings must be performed 943 * on each CPU in the SMP case. 944 */ 945 child = BUS_ADD_CHILD(parent, 10, "est", device_get_unit(parent)); 946 if (child == NULL) 947 device_printf(parent, "add est child failed\n"); 948 } 949 950 static int 951 est_probe(device_t dev) 952 { 953 device_t perf_dev; 954 uint64_t msr; 955 int error, type; 956 957 if (resource_disabled("est", 0)) 958 return (ENXIO); 959 960 /* 961 * If the ACPI perf driver has attached and is not just offering 962 * info, let it manage things. 963 */ 964 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 965 if (perf_dev && device_is_attached(perf_dev)) { 966 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 967 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 968 return (ENXIO); 969 } 970 971 /* Attempt to enable SpeedStep if not currently enabled. */ 972 msr = rdmsr(MSR_MISC_ENABLE); 973 if ((msr & MSR_SS_ENABLE) == 0) { 974 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 975 if (bootverbose) 976 device_printf(dev, "enabling SpeedStep\n"); 977 978 /* Check if the enable failed. */ 979 msr = rdmsr(MSR_MISC_ENABLE); 980 if ((msr & MSR_SS_ENABLE) == 0) { 981 device_printf(dev, "failed to enable SpeedStep\n"); 982 return (ENXIO); 983 } 984 } 985 986 device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 987 return (0); 988 } 989 990 static int 991 est_attach(device_t dev) 992 { 993 struct est_softc *sc; 994 995 sc = device_get_softc(dev); 996 sc->dev = dev; 997 998 /* On SMP system we can't guarantie independent freq setting. */ 999 if (strict == -1 && mp_ncpus > 1) 1000 strict = 0; 1001 /* Check CPU for supported settings. */ 1002 if (est_get_info(dev)) 1003 return (ENXIO); 1004 1005 cpufreq_register(dev); 1006 return (0); 1007 } 1008 1009 static int 1010 est_detach(device_t dev) 1011 { 1012 struct est_softc *sc; 1013 int error; 1014 1015 error = cpufreq_unregister(dev); 1016 if (error) 1017 return (error); 1018 1019 sc = device_get_softc(dev); 1020 if (sc->acpi_settings || sc->msr_settings) 1021 free(sc->freq_list, M_DEVBUF); 1022 return (0); 1023 } 1024 1025 /* 1026 * Probe for supported CPU settings. First, check our static table of 1027 * settings. If no match, try using the ones offered by acpi_perf 1028 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1029 * series) export both legacy SMM IO-based access and direct MSR access 1030 * but the direct access specifies invalid values for _PSS. 1031 */ 1032 static int 1033 est_get_info(device_t dev) 1034 { 1035 struct est_softc *sc; 1036 uint64_t msr; 1037 int error; 1038 1039 sc = device_get_softc(dev); 1040 msr = rdmsr(MSR_PERF_STATUS); 1041 error = est_table_info(dev, msr, &sc->freq_list, &sc->flist_len); 1042 if (error) 1043 error = est_acpi_info(dev, &sc->freq_list, &sc->flist_len); 1044 if (error) 1045 error = est_msr_info(dev, msr, &sc->freq_list, &sc->flist_len); 1046 1047 if (error) { 1048 printf( 1049 "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1050 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1051 return (ENXIO); 1052 } 1053 1054 return (0); 1055 } 1056 1057 static int 1058 est_acpi_info(device_t dev, freq_info **freqs, size_t *freqslen) 1059 { 1060 struct est_softc *sc; 1061 struct cf_setting *sets; 1062 freq_info *table; 1063 device_t perf_dev; 1064 int count, error, i, j; 1065 uint16_t saved_id16; 1066 1067 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1068 if (perf_dev == NULL || !device_is_attached(perf_dev)) 1069 return (ENXIO); 1070 1071 /* Fetch settings from acpi_perf. */ 1072 sc = device_get_softc(dev); 1073 table = NULL; 1074 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1075 if (sets == NULL) 1076 return (ENOMEM); 1077 count = MAX_SETTINGS; 1078 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1079 if (error) 1080 goto out; 1081 1082 /* Parse settings into our local table format. */ 1083 table = malloc(count * sizeof(*table), M_DEVBUF, M_NOWAIT); 1084 if (table == NULL) { 1085 error = ENOMEM; 1086 goto out; 1087 } 1088 est_get_id16(&saved_id16); 1089 for (i = 0, j = 0; i < count; i++) { 1090 /* 1091 * Confirm id16 value is correct. 1092 */ 1093 if (sets[i].freq > 0) { 1094 error = est_set_id16(dev, sets[i].spec[0], strict); 1095 if (error != 0) { 1096 if (bootverbose) 1097 device_printf(dev, "Invalid freq %u, " 1098 "ignored.\n", sets[i].freq); 1099 continue; 1100 } 1101 table[j].freq = sets[i].freq; 1102 table[j].volts = sets[i].volts; 1103 table[j].id16 = sets[i].spec[0]; 1104 table[j].power = sets[i].power; 1105 ++j; 1106 } 1107 } 1108 /* restore saved setting */ 1109 est_set_id16(dev, saved_id16, 0); 1110 1111 sc->acpi_settings = TRUE; 1112 *freqs = table; 1113 *freqslen = j; 1114 error = 0; 1115 1116 out: 1117 if (sets) 1118 free(sets, M_TEMP); 1119 if (error && table) 1120 free(table, M_DEVBUF); 1121 return (error); 1122 } 1123 1124 static int 1125 est_table_info(device_t dev, uint64_t msr, freq_info **freqs, size_t *freqslen) 1126 { 1127 cpu_info *p; 1128 uint32_t id; 1129 1130 /* Find a table which matches (vendor, id32). */ 1131 id = msr >> 32; 1132 for (p = ESTprocs; p->id32 != 0; p++) { 1133 if (p->vendor_id == cpu_vendor_id && p->id32 == id) 1134 break; 1135 } 1136 if (p->id32 == 0) 1137 return (EOPNOTSUPP); 1138 1139 /* Make sure the current setpoint is valid. */ 1140 if (est_get_current(p->freqtab, p->tablen) == NULL) { 1141 device_printf(dev, "current setting not found in table\n"); 1142 return (EOPNOTSUPP); 1143 } 1144 1145 *freqs = p->freqtab; 1146 *freqslen = p->tablen; 1147 return (0); 1148 } 1149 1150 static int 1151 bus_speed_ok(int bus) 1152 { 1153 1154 switch (bus) { 1155 case 100: 1156 case 133: 1157 case 333: 1158 return (1); 1159 default: 1160 return (0); 1161 } 1162 } 1163 1164 /* 1165 * Flesh out a simple rate table containing the high and low frequencies 1166 * based on the current clock speed and the upper 32 bits of the MSR. 1167 */ 1168 static int 1169 est_msr_info(device_t dev, uint64_t msr, freq_info **freqs, size_t *freqslen) 1170 { 1171 struct est_softc *sc; 1172 freq_info *fp; 1173 int bus, freq, volts; 1174 uint16_t id; 1175 1176 if (!msr_info_enabled) 1177 return (EOPNOTSUPP); 1178 1179 /* Figure out the bus clock. */ 1180 freq = atomic_load_acq_64(&tsc_freq) / 1000000; 1181 id = msr >> 32; 1182 bus = freq / (id >> 8); 1183 device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus); 1184 if (!bus_speed_ok(bus)) { 1185 /* We may be running on the low frequency. */ 1186 id = msr >> 48; 1187 bus = freq / (id >> 8); 1188 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus); 1189 if (!bus_speed_ok(bus)) 1190 return (EOPNOTSUPP); 1191 1192 /* Calculate high frequency. */ 1193 id = msr >> 32; 1194 freq = ((id >> 8) & 0xff) * bus; 1195 } 1196 1197 /* Fill out a new freq table containing just the high and low freqs. */ 1198 sc = device_get_softc(dev); 1199 fp = malloc(sizeof(freq_info) * 2, M_DEVBUF, M_WAITOK | M_ZERO); 1200 1201 /* First, the high frequency. */ 1202 volts = id & 0xff; 1203 if (volts != 0) { 1204 volts <<= 4; 1205 volts += 700; 1206 } 1207 fp[0].freq = freq; 1208 fp[0].volts = volts; 1209 fp[0].id16 = id; 1210 fp[0].power = CPUFREQ_VAL_UNKNOWN; 1211 device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq, 1212 volts); 1213 1214 /* Second, the low frequency. */ 1215 id = msr >> 48; 1216 freq = ((id >> 8) & 0xff) * bus; 1217 volts = id & 0xff; 1218 if (volts != 0) { 1219 volts <<= 4; 1220 volts += 700; 1221 } 1222 fp[1].freq = freq; 1223 fp[1].volts = volts; 1224 fp[1].id16 = id; 1225 fp[1].power = CPUFREQ_VAL_UNKNOWN; 1226 device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq, 1227 volts); 1228 1229 /* Table is already terminated due to M_ZERO. */ 1230 sc->msr_settings = TRUE; 1231 *freqs = fp; 1232 *freqslen = 2; 1233 return (0); 1234 } 1235 1236 static void 1237 est_get_id16(uint16_t *id16_p) 1238 { 1239 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1240 } 1241 1242 static int 1243 est_set_id16(device_t dev, uint16_t id16, int need_check) 1244 { 1245 uint64_t msr; 1246 uint16_t new_id16; 1247 int ret = 0; 1248 1249 /* Read the current register, mask out the old, set the new id. */ 1250 msr = rdmsr(MSR_PERF_CTL); 1251 msr = (msr & ~0xffff) | id16; 1252 wrmsr(MSR_PERF_CTL, msr); 1253 1254 if (need_check) { 1255 /* Wait a short while and read the new status. */ 1256 DELAY(EST_TRANS_LAT); 1257 est_get_id16(&new_id16); 1258 if (new_id16 != id16) { 1259 if (bootverbose) 1260 device_printf(dev, "Invalid id16 (set, cur) " 1261 "= (%u, %u)\n", id16, new_id16); 1262 ret = ENXIO; 1263 } 1264 } 1265 return (ret); 1266 } 1267 1268 static freq_info * 1269 est_get_current(freq_info *freq_list, size_t tablen) 1270 { 1271 freq_info *f; 1272 int i; 1273 uint16_t id16; 1274 1275 /* 1276 * Try a few times to get a valid value. Sometimes, if the CPU 1277 * is in the middle of an asynchronous transition (i.e., P4TCC), 1278 * we get a temporary invalid result. 1279 */ 1280 for (i = 0; i < 5; i++) { 1281 est_get_id16(&id16); 1282 for (f = freq_list; f < freq_list + tablen; f++) { 1283 if (f->id16 == id16) 1284 return (f); 1285 } 1286 DELAY(100); 1287 } 1288 return (NULL); 1289 } 1290 1291 static int 1292 est_settings(device_t dev, struct cf_setting *sets, int *count) 1293 { 1294 struct est_softc *sc; 1295 freq_info *f; 1296 int i; 1297 1298 sc = device_get_softc(dev); 1299 if (*count < EST_MAX_SETTINGS) 1300 return (E2BIG); 1301 1302 i = 0; 1303 for (f = sc->freq_list; f < sc->freq_list + sc->flist_len; f++, i++) { 1304 sets[i].freq = f->freq; 1305 sets[i].volts = f->volts; 1306 sets[i].power = f->power; 1307 sets[i].lat = EST_TRANS_LAT; 1308 sets[i].dev = dev; 1309 } 1310 *count = i; 1311 1312 return (0); 1313 } 1314 1315 static int 1316 est_set(device_t dev, const struct cf_setting *set) 1317 { 1318 struct est_softc *sc; 1319 freq_info *f; 1320 1321 /* Find the setting matching the requested one. */ 1322 sc = device_get_softc(dev); 1323 for (f = sc->freq_list; f < sc->freq_list + sc->flist_len; f++) { 1324 if (f->freq == set->freq) 1325 break; 1326 } 1327 if (f->freq == 0) 1328 return (EINVAL); 1329 1330 /* Read the current register, mask out the old, set the new id. */ 1331 est_set_id16(dev, f->id16, 0); 1332 1333 return (0); 1334 } 1335 1336 static int 1337 est_get(device_t dev, struct cf_setting *set) 1338 { 1339 struct est_softc *sc; 1340 freq_info *f; 1341 1342 sc = device_get_softc(dev); 1343 f = est_get_current(sc->freq_list, sc->flist_len); 1344 if (f == NULL) 1345 return (ENXIO); 1346 1347 set->freq = f->freq; 1348 set->volts = f->volts; 1349 set->power = f->power; 1350 set->lat = EST_TRANS_LAT; 1351 set->dev = dev; 1352 return (0); 1353 } 1354 1355 static int 1356 est_type(device_t dev, int *type) 1357 { 1358 1359 if (type == NULL) 1360 return (EINVAL); 1361 1362 *type = CPUFREQ_TYPE_ABSOLUTE; 1363 return (0); 1364 } 1365