1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Jessica Clarke <jrtc27@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* TODO: Provide interrupt controller interface */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/rman.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/gpio.h> 40 41 #include <dev/gpio/gpiobusvar.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 45 #include <machine/bus.h> 46 47 /* Registers are 32-bit so can only fit 32 pins */ 48 #define SFGPIO_MAX_PINS 32 49 50 #define SFGPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 51 52 #define SFGPIO_INPUT_VAL 0x0 53 #define SFGPIO_INPUT_EN 0x4 54 #define SFGPIO_OUTPUT_EN 0x8 55 #define SFGPIO_OUTPUT_VAL 0xc 56 #define SFGPIO_RISE_IE 0x18 57 #define SFGPIO_RISE_IP 0x1c 58 #define SFGPIO_FALL_IE 0x20 59 #define SFGPIO_FALL_IP 0x24 60 #define SFGPIO_HIGH_IE 0x28 61 #define SFGPIO_HIGH_IP 0x2c 62 #define SFGPIO_LOW_IE 0x30 63 #define SFGPIO_LOW_IP 0x34 64 65 struct sfgpio_softc { 66 device_t dev; 67 device_t busdev; 68 struct mtx mtx; 69 struct resource *mem_res; 70 int mem_rid; 71 struct resource *irq_res; 72 int irq_rid; 73 int npins; 74 struct gpio_pin gpio_pins[SFGPIO_MAX_PINS]; 75 }; 76 77 #define SFGPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx) 78 #define SFGPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 79 80 #define SFGPIO_READ(_sc, _off) \ 81 bus_read_4((_sc)->mem_res, (_off)) 82 #define SFGPIO_WRITE(_sc, _off, _val) \ 83 bus_write_4((_sc)->mem_res, (_off), (_val)) 84 85 static struct ofw_compat_data compat_data[] = { 86 { "sifive,gpio0", 1 }, 87 { NULL, 0 }, 88 }; 89 90 static int 91 sfgpio_probe(device_t dev) 92 { 93 if (!ofw_bus_status_okay(dev)) 94 return (ENXIO); 95 96 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 97 return (ENXIO); 98 99 device_set_desc(dev, "SiFive GPIO Controller"); 100 101 return (BUS_PROBE_DEFAULT); 102 } 103 104 static int 105 sfgpio_attach(device_t dev) 106 { 107 struct sfgpio_softc *sc; 108 phandle_t node; 109 int error, i; 110 pcell_t npins; 111 uint32_t input_en, output_en; 112 113 sc = device_get_softc(dev); 114 sc->dev = dev; 115 116 node = ofw_bus_get_node(dev); 117 118 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF); 119 120 sc->mem_rid = 0; 121 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 122 &sc->mem_rid, RF_ACTIVE); 123 if (sc->mem_res == NULL) { 124 device_printf(dev, "Cannot allocate memory resource\n"); 125 error = ENXIO; 126 goto fail; 127 } 128 129 if (OF_getencprop(node, "ngpios", &npins, sizeof(npins)) <= 0) { 130 /* Optional; defaults to 16 */ 131 npins = 16; 132 } else if (npins > SFGPIO_MAX_PINS) { 133 device_printf(dev, "Too many pins: %d\n", npins); 134 error = ENXIO; 135 goto fail; 136 } 137 sc->npins = npins; 138 139 sc->irq_rid = 0; 140 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 141 RF_ACTIVE); 142 if (sc->irq_res == NULL) { 143 device_printf(dev, "Cannot allocate IRQ resource\n"); 144 error = ENXIO; 145 goto fail; 146 } 147 148 input_en = SFGPIO_READ(sc, SFGPIO_INPUT_EN); 149 output_en = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN); 150 for (i = 0; i < sc->npins; ++i) { 151 sc->gpio_pins[i].gp_pin = i; 152 sc->gpio_pins[i].gp_caps = SFGPIO_DEFAULT_CAPS; 153 sc->gpio_pins[i].gp_flags = 154 ((input_en & (1u << i)) ? GPIO_PIN_INPUT : 0) | 155 ((output_en & (1u << i)) ? GPIO_PIN_OUTPUT : 0); 156 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "GPIO%d", i); 157 sc->gpio_pins[i].gp_name[GPIOMAXNAME - 1] = '\0'; 158 } 159 160 sc->busdev = gpiobus_attach_bus(dev); 161 if (sc->busdev == NULL) { 162 device_printf(dev, "Cannot attach gpiobus\n"); 163 error = ENXIO; 164 goto fail; 165 } 166 167 return (0); 168 169 fail: 170 if (sc->busdev != NULL) 171 gpiobus_detach_bus(dev); 172 if (sc->irq_res != NULL) 173 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 174 sc->irq_res); 175 if (sc->mem_res != NULL) 176 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, 177 sc->mem_res); 178 mtx_destroy(&sc->mtx); 179 return (error); 180 } 181 182 static device_t 183 sfgpio_get_bus(device_t dev) 184 { 185 struct sfgpio_softc *sc; 186 187 sc = device_get_softc(dev); 188 189 return (sc->busdev); 190 } 191 192 static int 193 sfgpio_pin_max(device_t dev, int *maxpin) 194 { 195 struct sfgpio_softc *sc; 196 197 sc = device_get_softc(dev); 198 199 *maxpin = sc->npins - 1; 200 201 return (0); 202 } 203 204 static int 205 sfgpio_pin_set(device_t dev, uint32_t pin, unsigned int val) 206 { 207 struct sfgpio_softc *sc; 208 uint32_t reg; 209 210 sc = device_get_softc(dev); 211 212 if (pin >= sc->npins) 213 return (EINVAL); 214 215 SFGPIO_LOCK(sc); 216 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL); 217 if (val) 218 reg |= (1u << pin); 219 else 220 reg &= ~(1u << pin); 221 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL, reg); 222 SFGPIO_UNLOCK(sc); 223 224 return (0); 225 } 226 227 static int 228 sfgpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 229 { 230 struct sfgpio_softc *sc; 231 uint32_t reg; 232 233 sc = device_get_softc(dev); 234 235 if (pin >= sc->npins) 236 return (EINVAL); 237 238 SFGPIO_LOCK(sc); 239 if (sc->gpio_pins[pin].gp_flags & GPIO_PIN_OUTPUT) 240 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL); 241 else 242 reg = SFGPIO_READ(sc, SFGPIO_INPUT_VAL); 243 *val = (reg & (1u << pin)) ? 1 : 0; 244 SFGPIO_UNLOCK(sc); 245 246 return (0); 247 } 248 249 static int 250 sfgpio_pin_toggle(device_t dev, uint32_t pin) 251 { 252 struct sfgpio_softc *sc; 253 uint32_t reg; 254 255 sc = device_get_softc(dev); 256 257 if (pin >= sc->npins) 258 return (EINVAL); 259 260 SFGPIO_LOCK(sc); 261 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL); 262 reg ^= (1u << pin); 263 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL, reg); 264 SFGPIO_UNLOCK(sc); 265 266 return (0); 267 } 268 269 static int 270 sfgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 271 { 272 struct sfgpio_softc *sc; 273 274 sc = device_get_softc(dev); 275 276 if (pin >= sc->npins) 277 return (EINVAL); 278 279 SFGPIO_LOCK(sc); 280 *caps = sc->gpio_pins[pin].gp_caps; 281 SFGPIO_UNLOCK(sc); 282 283 return (0); 284 } 285 286 static int 287 sfgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 288 { 289 struct sfgpio_softc *sc; 290 291 sc = device_get_softc(dev); 292 293 if (pin >= sc->npins) 294 return (EINVAL); 295 296 SFGPIO_LOCK(sc); 297 *flags = sc->gpio_pins[pin].gp_flags; 298 SFGPIO_UNLOCK(sc); 299 300 return (0); 301 } 302 303 static int 304 sfgpio_pin_getname(device_t dev, uint32_t pin, char *name) 305 { 306 struct sfgpio_softc *sc; 307 308 sc = device_get_softc(dev); 309 310 if (pin >= sc->npins) 311 return (EINVAL); 312 313 SFGPIO_LOCK(sc); 314 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 315 SFGPIO_UNLOCK(sc); 316 317 return (0); 318 } 319 320 static int 321 sfgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 322 { 323 struct sfgpio_softc *sc; 324 uint32_t reg; 325 326 sc = device_get_softc(dev); 327 328 if (pin >= sc->npins) 329 return (EINVAL); 330 331 SFGPIO_LOCK(sc); 332 333 reg = SFGPIO_READ(sc, SFGPIO_INPUT_EN); 334 if (flags & GPIO_PIN_INPUT) { 335 reg |= (1u << pin); 336 sc->gpio_pins[pin].gp_flags |= GPIO_PIN_INPUT; 337 } else { 338 reg &= ~(1u << pin); 339 sc->gpio_pins[pin].gp_flags &= ~GPIO_PIN_INPUT; 340 } 341 SFGPIO_WRITE(sc, SFGPIO_INPUT_EN, reg); 342 343 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN); 344 if (flags & GPIO_PIN_OUTPUT) { 345 reg |= (1u << pin); 346 sc->gpio_pins[pin].gp_flags |= GPIO_PIN_OUTPUT; 347 } else { 348 reg &= ~(1u << pin); 349 sc->gpio_pins[pin].gp_flags &= ~GPIO_PIN_OUTPUT; 350 } 351 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_EN, reg); 352 353 SFGPIO_UNLOCK(sc); 354 355 return (0); 356 } 357 358 static int 359 sfgpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 360 uint32_t change_pins, uint32_t *orig_pins) 361 { 362 struct sfgpio_softc *sc; 363 uint32_t reg; 364 365 if (first_pin != 0) 366 return (EINVAL); 367 368 sc = device_get_softc(dev); 369 370 SFGPIO_LOCK(sc); 371 372 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL); 373 374 if (orig_pins != NULL) 375 /* Only input_val is implicitly masked by input_en */ 376 *orig_pins = SFGPIO_READ(sc, SFGPIO_INPUT_VAL) | 377 (reg & SFGPIO_READ(sc, SFGPIO_OUTPUT_EN)); 378 379 if ((clear_pins | change_pins) != 0) 380 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL, 381 (reg & ~clear_pins) ^ change_pins); 382 383 SFGPIO_UNLOCK(sc); 384 385 return (0); 386 } 387 388 static int 389 sfgpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 390 uint32_t *pin_flags) 391 { 392 struct sfgpio_softc *sc; 393 uint32_t ireg, oreg; 394 int i; 395 396 sc = device_get_softc(dev); 397 398 if (first_pin != 0 || num_pins > sc->npins) 399 return (EINVAL); 400 401 SFGPIO_LOCK(sc); 402 403 ireg = SFGPIO_READ(sc, SFGPIO_INPUT_EN); 404 oreg = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN); 405 for (i = 0; i < num_pins; ++i) { 406 if (pin_flags[i] & GPIO_PIN_INPUT) { 407 ireg |= (1u << i); 408 oreg &= ~(1u << i); 409 sc->gpio_pins[i].gp_flags |= GPIO_PIN_INPUT; 410 sc->gpio_pins[i].gp_flags &= ~GPIO_PIN_OUTPUT; 411 } else if (pin_flags[i] & GPIO_PIN_OUTPUT) { 412 ireg &= ~(1u << i); 413 oreg |= (1u << i); 414 sc->gpio_pins[i].gp_flags &= ~GPIO_PIN_INPUT; 415 sc->gpio_pins[i].gp_flags |= GPIO_PIN_OUTPUT; 416 } 417 } 418 SFGPIO_WRITE(sc, SFGPIO_INPUT_EN, ireg); 419 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_EN, oreg); 420 421 SFGPIO_UNLOCK(sc); 422 423 return (0); 424 } 425 426 static phandle_t 427 sfgpio_get_node(device_t bus, device_t dev) 428 { 429 return (ofw_bus_get_node(bus)); 430 } 431 432 static device_method_t sfgpio_methods[] = { 433 /* Device interface */ 434 DEVMETHOD(device_probe, sfgpio_probe), 435 DEVMETHOD(device_attach, sfgpio_attach), 436 437 /* GPIO protocol */ 438 DEVMETHOD(gpio_get_bus, sfgpio_get_bus), 439 DEVMETHOD(gpio_pin_max, sfgpio_pin_max), 440 DEVMETHOD(gpio_pin_set, sfgpio_pin_set), 441 DEVMETHOD(gpio_pin_get, sfgpio_pin_get), 442 DEVMETHOD(gpio_pin_toggle, sfgpio_pin_toggle), 443 DEVMETHOD(gpio_pin_getcaps, sfgpio_pin_getcaps), 444 DEVMETHOD(gpio_pin_getflags, sfgpio_pin_getflags), 445 DEVMETHOD(gpio_pin_getname, sfgpio_pin_getname), 446 DEVMETHOD(gpio_pin_setflags, sfgpio_pin_setflags), 447 DEVMETHOD(gpio_pin_access_32, sfgpio_pin_access_32), 448 DEVMETHOD(gpio_pin_config_32, sfgpio_pin_config_32), 449 450 /* ofw_bus interface */ 451 DEVMETHOD(ofw_bus_get_node, sfgpio_get_node), 452 453 DEVMETHOD_END 454 }; 455 456 DEFINE_CLASS_0(gpio, sfgpio_driver, sfgpio_methods, 457 sizeof(struct sfgpio_softc)); 458 EARLY_DRIVER_MODULE(gpio, simplebus, sfgpio_driver, 0, 0, 459 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 460 MODULE_DEPEND(sfgpio, gpiobus, 1, 1, 1); 461