1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Axiado Corporation 5 * All rights reserved. 6 * 7 * This software was developed in part by Nick O'Brien and Rishul Naik 8 * for Axiado Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/clock.h> 37 #include <sys/eventhandler.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/sdt.h> 44 #include <sys/time.h> 45 #include <sys/timespec.h> 46 #include <sys/timex.h> 47 #include <sys/watchdog.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <machine/bus.h> 53 #include <machine/clock.h> 54 #include <machine/intr.h> 55 #include <machine/resource.h> 56 57 #include "clock_if.h" 58 59 #define FEAON_AON_WDT_BASE 0x0 60 #define FEAON_AON_RTC_BASE 0x40 61 #define FEAON_AON_CLKCFG_BASE 0x70 62 #define FEAON_AON_BACKUP_BASE 0x80 63 #define FEAON_AON_PMU_BASE 0x100 64 65 /* Watchdog specific */ 66 #define FEAON_WDT_CFG 0x0 67 #define FEAON_WDT_COUNT 0x8 68 #define FEAON_WDT_DOGS 0x10 69 #define FEAON_WDT_FEED 0x18 70 #define FEAON_WDT_KEY 0x1C 71 #define FEAON_WDT_CMP 0x20 72 73 #define FEAON_WDT_CFG_SCALE_MASK 0xF 74 #define FEAON_WDT_CFG_RST_EN (1 << 8) 75 #define FEAON_WDT_CFG_ZERO_CMP (1 << 9) 76 #define FEAON_WDT_CFG_EN_ALWAYS (1 << 12) 77 #define FEAON_WDT_CFG_EN_CORE_AWAKE (1 << 13) 78 #define FEAON_WDT_CFG_IP (1 << 28) 79 80 #define FEAON_WDT_CMP_MASK 0xFFFF 81 82 #define FEAON_WDT_FEED_FOOD 0xD09F00D 83 84 #define FEAON_WDT_KEY_UNLOCK 0x51F15E 85 86 #define FEAON_WDT_TIMEBASE_FREQ 31250 87 #define FEAON_WDT_TIMEBASE_RATIO (NANOSECOND / FEAON_WDT_TIMEBASE_FREQ) 88 89 /* Real-time clock specific */ 90 #define FEAON_RTC_CFG 0x40 91 #define FEAON_RTC_LO 0x48 92 #define FEAON_RTC_HI 0x4C 93 #define FEAON_RTC_CMP 0x60 94 95 #define FEAON_RTC_CFG_SCALE_MASK 0xF 96 #define FEAON_RTC_CFG_EN (1 << 12) 97 #define FEAON_RTC_CFG_IP (1 << 28) 98 99 #define FEAON_RTC_HI_MASK 0xFFFF 100 101 #define FEAON_RTC_TIMEBASE_FREQ 31250LL 102 103 #define FEAON_LOCK(sc) mtx_lock(&(sc)->mtx) 104 #define FEAON_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 105 #define FEAON_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 106 #define FEAON_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 107 108 #define FEAON_READ_4(sc, reg) bus_read_4(sc->reg_res, reg) 109 #define FEAON_WRITE_4(sc, reg, val) bus_write_4(sc->reg_res, reg, val) 110 111 #define FEAON_WDT_WRITE_4(sc, reg, val) do { \ 112 FEAON_WRITE_4(sc, (FEAON_WDT_KEY), (FEAON_WDT_KEY_UNLOCK)); \ 113 FEAON_WRITE_4(sc, reg, val); \ 114 } while (0) 115 116 struct feaon_softc { 117 device_t dev; 118 struct mtx mtx; 119 120 /* Resources */ 121 int reg_rid; 122 struct resource *reg_res; 123 124 /* WDT */ 125 eventhandler_tag ev_tag; 126 }; 127 128 static void 129 feaon_wdt_event(void *arg, unsigned int cmd, int *err) 130 { 131 struct feaon_softc *sc; 132 uint32_t scale, val; 133 uint64_t time; 134 135 sc = (struct feaon_softc *)arg; 136 FEAON_LOCK(sc); 137 138 /* First feed WDT */ 139 FEAON_WDT_WRITE_4(sc, FEAON_WDT_FEED, FEAON_WDT_FEED_FOOD); 140 141 if ((cmd & WD_INTERVAL) == WD_TO_NEVER) { 142 /* Disable WDT */ 143 val = FEAON_READ_4(sc, FEAON_WDT_CFG); 144 val &= ~(FEAON_WDT_CFG_EN_ALWAYS | FEAON_WDT_CFG_EN_CORE_AWAKE); 145 FEAON_WDT_WRITE_4(sc, FEAON_WDT_CFG, val); 146 goto exit; 147 } 148 149 /* Calculate time in WDT frequency */ 150 time = 1LL << (cmd & WD_INTERVAL); 151 time /= FEAON_WDT_TIMEBASE_RATIO; 152 153 /* Fit time in CMP register with scale */ 154 scale = 0; 155 while (time > FEAON_WDT_CMP_MASK) { 156 time >>= 1; 157 scale++; 158 } 159 160 if (time > FEAON_WDT_CMP_MASK || scale > FEAON_WDT_CFG_SCALE_MASK) { 161 device_printf(sc->dev, "Time interval too large for WDT\n"); 162 *err = EINVAL; 163 goto exit; 164 } 165 166 /* Program WDT */ 167 val = FEAON_READ_4(sc, FEAON_WDT_CFG); 168 val &= ~FEAON_WDT_CFG_SCALE_MASK; 169 val |= scale | FEAON_WDT_CFG_RST_EN | FEAON_WDT_CFG_EN_ALWAYS | 170 FEAON_WDT_CFG_ZERO_CMP; 171 172 FEAON_WDT_WRITE_4(sc, FEAON_WDT_CMP, (uint32_t)time); 173 FEAON_WDT_WRITE_4(sc, FEAON_WDT_CFG, val); 174 175 exit: 176 FEAON_UNLOCK(sc); 177 } 178 179 static int 180 feaon_rtc_settime(device_t dev, struct timespec *ts) 181 { 182 struct feaon_softc *sc; 183 uint64_t time; 184 uint32_t cfg; 185 uint8_t scale; 186 187 scale = 0; 188 sc = device_get_softc(dev); 189 190 FEAON_LOCK(sc); 191 192 clock_dbgprint_ts(dev, CLOCK_DBG_WRITE, ts); 193 194 time = ts->tv_sec * FEAON_RTC_TIMEBASE_FREQ; 195 196 /* Find an appropriate scale */ 197 while (time >= 0xFFFFFFFFFFFFLL) { 198 scale++; 199 time >>= 1; 200 } 201 if (scale > FEAON_RTC_CFG_SCALE_MASK) { 202 device_printf(sc->dev, "Time value too large for RTC\n"); 203 FEAON_UNLOCK(sc); 204 return (1); 205 } 206 cfg = FEAON_READ_4(sc, FEAON_RTC_CFG) & ~FEAON_RTC_CFG_SCALE_MASK; 207 cfg |= scale; 208 209 FEAON_WRITE_4(sc, FEAON_RTC_CFG, cfg); 210 FEAON_WRITE_4(sc, FEAON_RTC_LO, (uint32_t)time); 211 FEAON_WRITE_4(sc, FEAON_RTC_HI, (time >> 32) & FEAON_RTC_HI_MASK); 212 213 FEAON_UNLOCK(sc); 214 215 return (0); 216 } 217 218 static int 219 feaon_rtc_gettime(device_t dev, struct timespec *ts) 220 { 221 struct feaon_softc *sc; 222 uint64_t time; 223 uint8_t scale; 224 225 sc = device_get_softc(dev); 226 FEAON_LOCK(sc); 227 228 time = FEAON_READ_4(sc, FEAON_RTC_LO); 229 time |= ((uint64_t)FEAON_READ_4(sc, FEAON_RTC_HI)) << 32; 230 231 scale = FEAON_READ_4(sc, FEAON_RTC_CFG) & FEAON_RTC_CFG_SCALE_MASK; 232 time <<= scale; 233 234 ts->tv_sec = time / FEAON_RTC_TIMEBASE_FREQ; 235 ts->tv_nsec = (time % FEAON_RTC_TIMEBASE_FREQ) * 236 (NANOSECOND / FEAON_RTC_TIMEBASE_FREQ); 237 238 clock_dbgprint_ts(dev, CLOCK_DBG_READ, ts); 239 240 FEAON_UNLOCK(sc); 241 242 return (0); 243 } 244 245 static int 246 feaon_attach(device_t dev) 247 { 248 struct feaon_softc *sc; 249 int err; 250 251 sc = device_get_softc(dev); 252 sc->dev = dev; 253 254 /* Mutex setup */ 255 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF); 256 257 /* Resource setup */ 258 sc->reg_rid = 0; 259 if ((sc->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 260 &sc->reg_rid, RF_ACTIVE)) == NULL) { 261 device_printf(dev, "Error allocating memory resource.\n"); 262 err = ENXIO; 263 goto error; 264 } 265 266 /* Enable RTC */ 267 clock_register(dev, 1000000); /* 1 sec resolution */ 268 FEAON_LOCK(sc); 269 FEAON_WRITE_4(sc, FEAON_RTC_CFG, FEAON_RTC_CFG_EN); 270 FEAON_UNLOCK(sc); 271 272 /* Register WDT */ 273 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, feaon_wdt_event, sc, 0); 274 275 return (0); 276 277 error: 278 bus_release_resource(dev, SYS_RES_MEMORY, sc->reg_rid, sc->reg_res); 279 mtx_destroy(&sc->mtx); 280 return (err); 281 } 282 283 static int 284 feaon_probe(device_t dev) 285 { 286 287 if (!ofw_bus_status_okay(dev)) 288 return (ENXIO); 289 290 if (!ofw_bus_is_compatible(dev, "sifive,aon0")) 291 return (ENXIO); 292 293 device_set_desc(dev, "SiFive FE310 Always-On Controller"); 294 return (BUS_PROBE_DEFAULT); 295 } 296 297 static device_method_t feaon_methods[] = { 298 DEVMETHOD(device_probe, feaon_probe), 299 DEVMETHOD(device_attach, feaon_attach), 300 301 /* RTC */ 302 DEVMETHOD(clock_gettime, feaon_rtc_gettime), 303 DEVMETHOD(clock_settime, feaon_rtc_settime), 304 305 DEVMETHOD_END 306 }; 307 308 static driver_t feaon_driver = { 309 "fe310aon", 310 feaon_methods, 311 sizeof(struct feaon_softc) 312 }; 313 314 DRIVER_MODULE(fe310aon, simplebus, feaon_driver, 0, 0); 315