1 /*- 2 * Copyright (c) 2016-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * Copyright (c) 2019 Mitchell Horne <mhorne@FreeBSD.org> 5 * 6 * Portions of this software were developed by SRI International and the 7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 9 * 10 * Portions of this software were developed by the University of Cambridge 11 * Computer Laboratory as part of the CTSRD Project, with support from the 12 * UK Higher Education Innovation Fund (HEIF). 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD$ 36 */ 37 38 #ifndef _MACHINE_SBI_H_ 39 #define _MACHINE_SBI_H_ 40 41 /* SBI Specification Version */ 42 #define SBI_SPEC_VERS_MAJOR_OFFSET 24 43 #define SBI_SPEC_VERS_MAJOR_MASK (0x7F << SBI_SPEC_VERS_MAJOR_OFFSET) 44 #define SBI_SPEC_VERS_MINOR_OFFSET 0 45 #define SBI_SPEC_VERS_MINOR_MASK (0xFFFFFF << SBI_SPEC_VERS_MINOR_OFFSET) 46 47 /* SBI Implementation IDs */ 48 #define SBI_IMPL_ID_BBL 0 49 #define SBI_IMPL_ID_OPENSBI 1 50 #define SBI_IMPL_ID_XVISOR 2 51 #define SBI_IMPL_ID_KVM 3 52 #define SBI_IMPL_ID_RUSTSBI 4 53 #define SBI_IMPL_ID_DIOSIX 5 54 55 /* SBI Error Codes */ 56 #define SBI_SUCCESS 0 57 #define SBI_ERR_FAILURE -1 58 #define SBI_ERR_NOT_SUPPORTED -2 59 #define SBI_ERR_INVALID_PARAM -3 60 #define SBI_ERR_DENIED -4 61 #define SBI_ERR_INVALID_ADDRESS -5 62 #define SBI_ERR_ALREADY_AVAILABLE -6 63 64 /* SBI Base Extension */ 65 #define SBI_EXT_ID_BASE 0x10 66 #define SBI_BASE_GET_SPEC_VERSION 0 67 #define SBI_BASE_GET_IMPL_ID 1 68 #define SBI_BASE_GET_IMPL_VERSION 2 69 #define SBI_BASE_PROBE_EXTENSION 3 70 #define SBI_BASE_GET_MVENDORID 4 71 #define SBI_BASE_GET_MARCHID 5 72 #define SBI_BASE_GET_MIMPID 6 73 74 /* Timer (TIME) Extension */ 75 #define SBI_EXT_ID_TIME 0x54494D45 76 #define SBI_TIME_SET_TIMER 0 77 78 /* IPI (IPI) Extension */ 79 #define SBI_EXT_ID_IPI 0x735049 80 #define SBI_IPI_SEND_IPI 0 81 82 /* RFENCE (RFNC) Extension */ 83 #define SBI_EXT_ID_RFNC 0x52464E43 84 #define SBI_RFNC_REMOTE_FENCE_I 0 85 #define SBI_RFNC_REMOTE_SFENCE_VMA 1 86 #define SBI_RFNC_REMOTE_SFENCE_VMA_ASID 2 87 #define SBI_RFNC_REMOTE_HFENCE_GVMA_VMID 3 88 #define SBI_RFNC_REMOTE_HFENCE_GVMA 4 89 #define SBI_RFNC_REMOTE_HFENCE_VVMA_ASID 5 90 #define SBI_RFNC_REMOTE_HFENCE_VVMA 6 91 92 /* Hart State Management (HSM) Extension */ 93 #define SBI_EXT_ID_HSM 0x48534D 94 #define SBI_HSM_HART_START 0 95 #define SBI_HSM_HART_STOP 1 96 #define SBI_HSM_HART_STATUS 2 97 #define SBI_HSM_STATUS_STARTED 0 98 #define SBI_HSM_STATUS_STOPPED 1 99 #define SBI_HSM_STATUS_START_PENDING 2 100 #define SBI_HSM_STATUS_STOP_PENDING 3 101 102 /* Legacy Extensions */ 103 #define SBI_SET_TIMER 0 104 #define SBI_CONSOLE_PUTCHAR 1 105 #define SBI_CONSOLE_GETCHAR 2 106 #define SBI_CLEAR_IPI 3 107 #define SBI_SEND_IPI 4 108 #define SBI_REMOTE_FENCE_I 5 109 #define SBI_REMOTE_SFENCE_VMA 6 110 #define SBI_REMOTE_SFENCE_VMA_ASID 7 111 #define SBI_SHUTDOWN 8 112 113 #define SBI_CALL0(e, f) SBI_CALL5(e, f, 0, 0, 0, 0, 0) 114 #define SBI_CALL1(e, f, p1) SBI_CALL5(e, f, p1, 0, 0, 0, 0) 115 #define SBI_CALL2(e, f, p1, p2) SBI_CALL5(e, f, p1, p2, 0, 0, 0) 116 #define SBI_CALL3(e, f, p1, p2, p3) SBI_CALL5(e, f, p1, p2, p3, 0, 0) 117 #define SBI_CALL4(e, f, p1, p2, p3, p4) SBI_CALL5(e, f, p1, p2, p3, p4, 0) 118 #define SBI_CALL5(e, f, p1, p2, p3, p4, p5) sbi_call(e, f, p1, p2, p3, p4, p5) 119 120 /* 121 * Documentation available at 122 * https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc 123 */ 124 125 struct sbi_ret { 126 long error; 127 long value; 128 }; 129 130 static __inline struct sbi_ret 131 sbi_call(uint64_t arg7, uint64_t arg6, uint64_t arg0, uint64_t arg1, 132 uint64_t arg2, uint64_t arg3, uint64_t arg4) 133 { 134 struct sbi_ret ret; 135 136 register uintptr_t a0 __asm ("a0") = (uintptr_t)(arg0); 137 register uintptr_t a1 __asm ("a1") = (uintptr_t)(arg1); 138 register uintptr_t a2 __asm ("a2") = (uintptr_t)(arg2); 139 register uintptr_t a3 __asm ("a3") = (uintptr_t)(arg3); 140 register uintptr_t a4 __asm ("a4") = (uintptr_t)(arg4); 141 register uintptr_t a6 __asm ("a6") = (uintptr_t)(arg6); 142 register uintptr_t a7 __asm ("a7") = (uintptr_t)(arg7); 143 144 __asm __volatile( \ 145 "ecall" \ 146 :"+r"(a0), "+r"(a1) \ 147 :"r"(a2), "r"(a3), "r"(a4), "r"(a6), "r"(a7) \ 148 :"memory"); 149 150 ret.error = a0; 151 ret.value = a1; 152 return (ret); 153 } 154 155 /* Base extension functions and variables. */ 156 extern u_long sbi_spec_version; 157 extern u_long sbi_impl_id; 158 extern u_long sbi_impl_version; 159 160 static __inline long 161 sbi_probe_extension(long id) 162 { 163 return (SBI_CALL1(SBI_EXT_ID_BASE, SBI_BASE_PROBE_EXTENSION, id).value); 164 } 165 166 /* TIME extension functions. */ 167 void sbi_set_timer(uint64_t val); 168 169 /* IPI extension functions. */ 170 void sbi_send_ipi(const u_long *hart_mask); 171 172 /* RFENCE extension functions. */ 173 void sbi_remote_fence_i(const u_long *hart_mask); 174 void sbi_remote_sfence_vma(const u_long *hart_mask, u_long start, u_long size); 175 void sbi_remote_sfence_vma_asid(const u_long *hart_mask, u_long start, 176 u_long size, u_long asid); 177 178 /* Hart State Management extension functions. */ 179 180 /* 181 * Start execution on the specified hart at physical address start_addr. The 182 * register a0 will contain the hart's ID, and a1 will contain the value of 183 * priv. 184 */ 185 int sbi_hsm_hart_start(u_long hart, u_long start_addr, u_long priv); 186 187 /* 188 * Stop execution on the current hart. Interrupts should be disabled, or this 189 * function may return. 190 */ 191 void sbi_hsm_hart_stop(void); 192 193 /* 194 * Get the execution status of the specified hart. The status will be one of: 195 * - SBI_HSM_STATUS_STARTED 196 * - SBI_HSM_STATUS_STOPPED 197 * - SBI_HSM_STATUS_START_PENDING 198 * - SBI_HSM_STATUS_STOP_PENDING 199 */ 200 int sbi_hsm_hart_status(u_long hart); 201 202 /* Legacy extension functions. */ 203 static __inline void 204 sbi_console_putchar(int ch) 205 { 206 207 (void)SBI_CALL1(SBI_CONSOLE_PUTCHAR, 0, ch); 208 } 209 210 static __inline int 211 sbi_console_getchar(void) 212 { 213 214 /* 215 * XXX: The "error" is returned here because legacy SBI functions 216 * continue to return their value in a0. 217 */ 218 return (SBI_CALL0(SBI_CONSOLE_GETCHAR, 0).error); 219 } 220 221 static __inline void 222 sbi_shutdown(void) 223 { 224 225 (void)SBI_CALL0(SBI_SHUTDOWN, 0); 226 } 227 228 void sbi_print_version(void); 229 void sbi_init(void); 230 231 #endif /* !_MACHINE_SBI_H_ */ 232