1 /*- 2 * Copyright (c) 2016-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * Copyright (c) 2019 Mitchell Horne <mhorne@FreeBSD.org> 5 * 6 * Portions of this software were developed by SRI International and the 7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 9 * 10 * Portions of this software were developed by the University of Cambridge 11 * Computer Laboratory as part of the CTSRD Project, with support from the 12 * UK Higher Education Innovation Fund (HEIF). 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD$ 36 */ 37 38 #ifndef _MACHINE_SBI_H_ 39 #define _MACHINE_SBI_H_ 40 41 /* SBI Specification Version */ 42 #define SBI_SPEC_VERS_MAJOR_OFFSET 24 43 #define SBI_SPEC_VERS_MAJOR_MASK (0x7F << SBI_SPEC_VERS_MAJOR_OFFSET) 44 #define SBI_SPEC_VERS_MINOR_OFFSET 0 45 #define SBI_SPEC_VERS_MINOR_MASK (0xFFFFFF << SBI_SPEC_VERS_MINOR_OFFSET) 46 47 /* SBI Implementation IDs */ 48 #define SBI_IMPL_ID_BBL 0 49 #define SBI_IMPL_ID_OPENSBI 1 50 51 /* SBI Error Codes */ 52 #define SBI_SUCCESS 0 53 #define SBI_ERR_FAILURE -1 54 #define SBI_ERR_NOT_SUPPORTED -2 55 #define SBI_ERR_INVALID_PARAM -3 56 #define SBI_ERR_DENIED -4 57 #define SBI_ERR_INVALID_ADDRESS -5 58 #define SBI_ERR_ALREADY_AVAILABLE -6 59 60 /* SBI Base Extension */ 61 #define SBI_EXT_ID_BASE 0x10 62 #define SBI_BASE_GET_SPEC_VERSION 0 63 #define SBI_BASE_GET_IMPL_ID 1 64 #define SBI_BASE_GET_IMPL_VERSION 2 65 #define SBI_BASE_PROBE_EXTENSION 3 66 #define SBI_BASE_GET_MVENDORID 4 67 #define SBI_BASE_GET_MARCHID 5 68 #define SBI_BASE_GET_MIMPID 6 69 70 /* Timer (TIME) Extension */ 71 #define SBI_EXT_ID_TIME 0x54494D45 72 #define SBI_TIME_SET_TIMER 0 73 74 /* IPI (IPI) Extension */ 75 #define SBI_EXT_ID_IPI 0x735049 76 #define SBI_IPI_SEND_IPI 0 77 78 /* RFENCE (RFNC) Extension */ 79 #define SBI_EXT_ID_RFNC 0x52464E43 80 #define SBI_RFNC_REMOTE_FENCE_I 0 81 #define SBI_RFNC_REMOTE_SFENCE_VMA 1 82 #define SBI_RFNC_REMOTE_SFENCE_VMA_ASID 2 83 #define SBI_RFNC_REMOTE_HFENCE_GVMA_VMID 3 84 #define SBI_RFNC_REMOTE_HFENCE_GVMA 4 85 #define SBI_RFNC_REMOTE_HFENCE_VVMA_ASID 5 86 #define SBI_RFNC_REMOTE_HFENCE_VVMA 6 87 88 /* Hart State Management (HSM) Extension */ 89 #define SBI_EXT_ID_HSM 0x48534D 90 #define SBI_HSM_HART_START 0 91 #define SBI_HSM_HART_STOP 1 92 #define SBI_HSM_HART_STATUS 2 93 #define SBI_HSM_STATUS_STARTED 0 94 #define SBI_HSM_STATUS_STOPPED 1 95 #define SBI_HSM_STATUS_START_PENDING 2 96 #define SBI_HSM_STATUS_STOP_PENDING 3 97 98 /* Legacy Extensions */ 99 #define SBI_SET_TIMER 0 100 #define SBI_CONSOLE_PUTCHAR 1 101 #define SBI_CONSOLE_GETCHAR 2 102 #define SBI_CLEAR_IPI 3 103 #define SBI_SEND_IPI 4 104 #define SBI_REMOTE_FENCE_I 5 105 #define SBI_REMOTE_SFENCE_VMA 6 106 #define SBI_REMOTE_SFENCE_VMA_ASID 7 107 #define SBI_SHUTDOWN 8 108 109 #define SBI_CALL0(e, f) SBI_CALL5(e, f, 0, 0, 0, 0, 0) 110 #define SBI_CALL1(e, f, p1) SBI_CALL5(e, f, p1, 0, 0, 0, 0) 111 #define SBI_CALL2(e, f, p1, p2) SBI_CALL5(e, f, p1, p2, 0, 0, 0) 112 #define SBI_CALL3(e, f, p1, p2, p3) SBI_CALL5(e, f, p1, p2, p3, 0, 0) 113 #define SBI_CALL4(e, f, p1, p2, p3, p4) SBI_CALL5(e, f, p1, p2, p3, p4, 0) 114 #define SBI_CALL5(e, f, p1, p2, p3, p4, p5) sbi_call(e, f, p1, p2, p3, p4, p5) 115 116 /* 117 * Documentation available at 118 * https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc 119 */ 120 121 struct sbi_ret { 122 long error; 123 long value; 124 }; 125 126 static __inline struct sbi_ret 127 sbi_call(uint64_t arg7, uint64_t arg6, uint64_t arg0, uint64_t arg1, 128 uint64_t arg2, uint64_t arg3, uint64_t arg4) 129 { 130 struct sbi_ret ret; 131 132 register uintptr_t a0 __asm ("a0") = (uintptr_t)(arg0); 133 register uintptr_t a1 __asm ("a1") = (uintptr_t)(arg1); 134 register uintptr_t a2 __asm ("a2") = (uintptr_t)(arg2); 135 register uintptr_t a3 __asm ("a3") = (uintptr_t)(arg3); 136 register uintptr_t a4 __asm ("a4") = (uintptr_t)(arg4); 137 register uintptr_t a6 __asm ("a6") = (uintptr_t)(arg6); 138 register uintptr_t a7 __asm ("a7") = (uintptr_t)(arg7); 139 140 __asm __volatile( \ 141 "ecall" \ 142 :"+r"(a0), "+r"(a1) \ 143 :"r"(a2), "r"(a3), "r"(a4), "r"(a6), "r"(a7) \ 144 :"memory"); 145 146 ret.error = a0; 147 ret.value = a1; 148 return (ret); 149 } 150 151 /* Base extension functions and variables. */ 152 extern u_long sbi_spec_version; 153 extern u_long sbi_impl_id; 154 extern u_long sbi_impl_version; 155 156 static __inline long 157 sbi_probe_extension(long id) 158 { 159 return (SBI_CALL1(SBI_EXT_ID_BASE, SBI_BASE_PROBE_EXTENSION, id).value); 160 } 161 162 /* TIME extension functions. */ 163 void sbi_set_timer(uint64_t val); 164 165 /* IPI extension functions. */ 166 void sbi_send_ipi(const u_long *hart_mask); 167 168 /* RFENCE extension functions. */ 169 void sbi_remote_fence_i(const u_long *hart_mask); 170 void sbi_remote_sfence_vma(const u_long *hart_mask, u_long start, u_long size); 171 void sbi_remote_sfence_vma_asid(const u_long *hart_mask, u_long start, 172 u_long size, u_long asid); 173 174 /* Hart State Management extension functions. */ 175 176 /* 177 * Start execution on the specified hart at physical address start_addr. The 178 * register a0 will contain the hart's ID, and a1 will contain the value of 179 * priv. 180 */ 181 int sbi_hsm_hart_start(u_long hart, u_long start_addr, u_long priv); 182 183 /* 184 * Stop execution on the current hart. Interrupts should be disabled, or this 185 * function may return. 186 */ 187 void sbi_hsm_hart_stop(void); 188 189 /* 190 * Get the execution status of the specified hart. The status will be one of: 191 * - SBI_HSM_STATUS_STARTED 192 * - SBI_HSM_STATUS_STOPPED 193 * - SBI_HSM_STATUS_START_PENDING 194 * - SBI_HSM_STATUS_STOP_PENDING 195 */ 196 int sbi_hsm_hart_status(u_long hart); 197 198 /* Legacy extension functions. */ 199 static __inline void 200 sbi_console_putchar(int ch) 201 { 202 203 (void)SBI_CALL1(SBI_CONSOLE_PUTCHAR, 0, ch); 204 } 205 206 static __inline int 207 sbi_console_getchar(void) 208 { 209 210 /* 211 * XXX: The "error" is returned here because legacy SBI functions 212 * continue to return their value in a0. 213 */ 214 return (SBI_CALL0(SBI_CONSOLE_GETCHAR, 0).error); 215 } 216 217 static __inline void 218 sbi_shutdown(void) 219 { 220 221 (void)SBI_CALL0(SBI_SHUTDOWN, 0); 222 } 223 224 void sbi_print_version(void); 225 void sbi_init(void); 226 227 #endif /* !_MACHINE_SBI_H_ */ 228