1 /*- 2 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 #ifndef _MACHINE_RISCVREG_H_ 38 #define _MACHINE_RISCVREG_H_ 39 40 /* Machine mode requests */ 41 #define ECALL_MTIMECMP 0x01 42 #define ECALL_CLEAR_PENDING 0x02 43 #define ECALL_HTIF_CMD 0x03 44 #define ECALL_HTIF_GET_ENTRY 0x04 45 #define ECALL_MCPUID_GET 0x05 46 #define ECALL_MIMPID_GET 0x06 47 #define ECALL_SEND_IPI 0x07 48 #define ECALL_CLEAR_IPI 0x08 49 #define ECALL_HTIF_LOWPUTC 0x09 50 #define ECALL_MIE_SET 0x10 51 52 #define EXCP_SHIFT 0 53 #define EXCP_MASK (0xf << EXCP_SHIFT) 54 #define EXCP_INSTR_ADDR_MISALIGNED 0 55 #define EXCP_INSTR_ACCESS_FAULT 1 56 #define EXCP_INSTR_ILLEGAL 2 57 #define EXCP_INSTR_BREAKPOINT 3 58 #define EXCP_LOAD_ADDR_MISALIGNED 4 59 #define EXCP_LOAD_ACCESS_FAULT 5 60 #define EXCP_STORE_ADDR_MISALIGNED 6 61 #define EXCP_STORE_ACCESS_FAULT 7 62 #define EXCP_UMODE_ENV_CALL 8 63 #define EXCP_SMODE_ENV_CALL 9 64 #define EXCP_HMODE_ENV_CALL 10 65 #define EXCP_MMODE_ENV_CALL 11 66 #define EXCP_INTR (1 << 31) 67 #define EXCP_INTR_SOFTWARE 0 68 #define EXCP_INTR_TIMER 1 69 #define EXCP_INTR_HTIF 2 70 71 #define SSTATUS_IE (1 << 0) 72 #define SSTATUS_PIE (1 << 3) 73 #define SSTATUS_PS (1 << 4) 74 75 #define MSTATUS_MPRV (1 << 16) 76 #define MSTATUS_PRV_SHIFT 1 77 #define MSTATUS_PRV1_SHIFT 4 78 #define MSTATUS_PRV2_SHIFT 7 79 #define MSTATUS_PRV_MASK (0x3 << MSTATUS_PRV_SHIFT) 80 #define MSTATUS_PRV_U 0 /* user */ 81 #define MSTATUS_PRV_S 1 /* supervisor */ 82 #define MSTATUS_PRV_H 2 /* hypervisor */ 83 #define MSTATUS_PRV_M 3 /* machine */ 84 85 #define MSTATUS_VM_SHIFT 17 86 #define MSTATUS_VM_MASK 0x1f 87 #define MSTATUS_VM_MBARE 0 88 #define MSTATUS_VM_MBB 1 89 #define MSTATUS_VM_MBBID 2 90 #define MSTATUS_VM_SV32 8 91 #define MSTATUS_VM_SV39 9 92 #define MSTATUS_VM_SV48 10 93 94 #define MIE_SSIE (1 << 1) 95 #define MIE_HSIE (1 << 2) 96 #define MIE_MSIE (1 << 3) 97 #define MIE_STIE (1 << 5) 98 #define MIE_HTIE (1 << 6) 99 #define MIE_MTIE (1 << 7) 100 101 #define MIP_SSIP (1 << 1) 102 #define MIP_HSIP (1 << 2) 103 #define MIP_MSIP (1 << 3) 104 #define MIP_STIP (1 << 5) 105 #define MIP_HTIP (1 << 6) 106 #define MIP_MTIP (1 << 7) 107 108 #define SR_IE (1 << 0) 109 #define SR_IE1 (1 << 3) 110 #define SR_IE2 (1 << 6) 111 #define SR_IE3 (1 << 9) 112 113 #define SIE_SSIE (1 << 1) 114 #define SIE_STIE (1 << 5) 115 116 /* Note: sip register has no SIP_STIP bit in Spike simulator */ 117 #define SIP_SSIP (1 << 1) 118 #define SIP_STIP (1 << 5) 119 120 #define NCSRS 4096 121 #define CSR_IPI 0x783 122 #define XLEN 8 123 124 #define CSR_ZIMM(val) \ 125 (__builtin_constant_p(val) && ((u_long)(val) < 32)) 126 127 #define csr_swap(csr, val) \ 128 ({ if (CSR_ZIMM(val)) \ 129 __asm __volatile("csrrwi %0, " #csr ", %1" \ 130 : "=r" (val) : "i" (val)); \ 131 else \ 132 __asm __volatile("csrrw %0, " #csr ", %1" \ 133 : "=r" (val) : "r" (val)); \ 134 val; \ 135 }) 136 137 #define csr_write(csr, val) \ 138 ({ if (CSR_ZIMM(val)) \ 139 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \ 140 else \ 141 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \ 142 }) 143 144 #define csr_set(csr, val) \ 145 ({ if (CSR_ZIMM(val)) \ 146 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \ 147 else \ 148 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \ 149 }) 150 151 #define csr_clear(csr, val) \ 152 ({ if (CSR_ZIMM(val)) \ 153 __asm __volatile("csrci " #csr ", %0" :: "i" (val)); \ 154 else \ 155 __asm __volatile("csrc " #csr ", %0" :: "r" (val)); \ 156 }) 157 158 #define csr_read(csr) \ 159 ({ u_long val; \ 160 __asm __volatile("csrr %0, " #csr : "=r" (val)); \ 161 val; \ 162 }) 163 164 #endif /* !_MACHINE_RISCVREG_H_ */ 165