1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 #ifndef _MACHINE_RISCVREG_H_ 38 #define _MACHINE_RISCVREG_H_ 39 40 /* Machine mode requests */ 41 #define ECALL_MTIMECMP 0x1 42 #define ECALL_CLEAR_PENDING 0x2 43 #define ECALL_HTIF_CMD 0x3 44 #define ECALL_HTIF_GET_ENTRY 0x4 45 #define ECALL_MCPUID_GET 0x5 46 #define ECALL_MIMPID_GET 0x6 47 48 #define EXCP_SHIFT 0 49 #define EXCP_MASK (0xf << EXCP_SHIFT) 50 #define EXCP_INSTR_ADDR_MISALIGNED 0 51 #define EXCP_INSTR_ACCESS_FAULT 1 52 #define EXCP_INSTR_ILLEGAL 2 53 #define EXCP_INSTR_BREAKPOINT 3 54 #define EXCP_LOAD_ADDR_MISALIGNED 4 55 #define EXCP_LOAD_ACCESS_FAULT 5 56 #define EXCP_STORE_ADDR_MISALIGNED 6 57 #define EXCP_STORE_ACCESS_FAULT 7 58 #define EXCP_UMODE_ENV_CALL 8 59 #define EXCP_SMODE_ENV_CALL 9 60 #define EXCP_HMODE_ENV_CALL 10 61 #define EXCP_MMODE_ENV_CALL 11 62 #define EXCP_INTR (1 << 31) 63 #define EXCP_INTR_SOFTWARE 0 64 #define EXCP_INTR_TIMER 1 65 #define EXCP_INTR_HTIF 2 66 67 #define SSTATUS_IE (1 << 0) 68 #define SSTATUS_PIE (1 << 3) 69 #define SSTATUS_PS (1 << 4) 70 71 #define MSTATUS_MPRV (1 << 16) 72 #define MSTATUS_PRV_SHIFT 1 73 #define MSTATUS_PRV1_SHIFT 4 74 #define MSTATUS_PRV2_SHIFT 7 75 #define MSTATUS_PRV_MASK (0x3 << MSTATUS_PRV_SHIFT) 76 #define MSTATUS_PRV_U 0 /* user */ 77 #define MSTATUS_PRV_S 1 /* supervisor */ 78 #define MSTATUS_PRV_H 2 /* hypervisor */ 79 #define MSTATUS_PRV_M 3 /* machine */ 80 81 #define MSTATUS_VM_SHIFT 17 82 #define MSTATUS_VM_MASK 0x1f 83 #define MSTATUS_VM_MBARE 0 84 #define MSTATUS_VM_MBB 1 85 #define MSTATUS_VM_MBBID 2 86 #define MSTATUS_VM_SV32 8 87 #define MSTATUS_VM_SV39 9 88 #define MSTATUS_VM_SV48 10 89 90 #define MIE_SSIE (1 << 1) 91 #define MIE_HSIE (1 << 2) 92 #define MIE_MSIE (1 << 3) 93 #define MIE_STIE (1 << 5) 94 #define MIE_HTIE (1 << 6) 95 #define MIE_MTIE (1 << 7) 96 97 #define MIP_SSIP (1 << 1) 98 #define MIP_HSIP (1 << 2) 99 #define MIP_MSIP (1 << 3) 100 #define MIP_STIP (1 << 5) 101 #define MIP_HTIP (1 << 6) 102 #define MIP_MTIP (1 << 7) 103 104 #define SR_IE (1 << 0) 105 #define SR_IE1 (1 << 3) 106 #define SR_IE2 (1 << 6) 107 #define SR_IE3 (1 << 9) 108 109 #define SIE_SSIE (1 << 1) 110 #define SIE_STIE (1 << 5) 111 112 /* Note: sip register is not yet implement in Spike simulator */ 113 #define SIP_STIP (1 << 5) 114 115 #define CSR_ZIMM(val) \ 116 (__builtin_constant_p(val) && ((u_long)(val) < 32)) 117 118 #define csr_swap(csr, val) \ 119 ({ if (CSR_ZIMM(val)) \ 120 __asm __volatile("csrrwi %0, " #csr ", %1" \ 121 : "=r" (val) : "i" (val)); \ 122 else \ 123 __asm __volatile("csrrw %0, " #csr ", %1" \ 124 : "=r" (val) : "r" (val)); \ 125 val; \ 126 }) 127 128 #define csr_write(csr, val) \ 129 ({ if (CSR_ZIMM(val)) \ 130 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \ 131 else \ 132 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \ 133 }) 134 135 #define csr_set(csr, val) \ 136 ({ if (CSR_ZIMM(val)) \ 137 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \ 138 else \ 139 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \ 140 }) 141 142 #define csr_clear(csr, val) \ 143 ({ if (CSR_ZIMM(val)) \ 144 __asm __volatile("csrci " #csr ", %0" :: "i" (val)); \ 145 else \ 146 __asm __volatile("csrc " #csr ", %0" :: "r" (val)); \ 147 }) 148 149 #define csr_read(csr) \ 150 ({ u_long val; \ 151 __asm __volatile("csrr %0, " #csr : "=r" (val)); \ 152 val; \ 153 }) 154 155 #endif /* !_MACHINE_RISCVREG_H_ */ 156