xref: /freebsd/sys/riscv/include/riscvreg.h (revision 13ea0450a9c8742119d36f3bf8f47accdce46e54)
1 /*-
2  * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
3  * All rights reserved.
4  *
5  * Portions of this software were developed by SRI International and the
6  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
8  *
9  * Portions of this software were developed by the University of Cambridge
10  * Computer Laboratory as part of the CTSRD Project, with support from the
11  * UK Higher Education Innovation Fund (HEIF).
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 1. Redistributions of source code must retain the above copyright
17  *    notice, this list of conditions and the following disclaimer.
18  * 2. Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the distribution.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32  * SUCH DAMAGE.
33  *
34  * $FreeBSD$
35  */
36 
37 #ifndef _MACHINE_RISCVREG_H_
38 #define	_MACHINE_RISCVREG_H_
39 
40 #define	EXCP_SHIFT			0
41 #define	EXCP_MASK			(0xf << EXCP_SHIFT)
42 #define	EXCP_MISALIGNED_FETCH		0
43 #define	EXCP_FAULT_FETCH		1
44 #define	EXCP_ILLEGAL_INSTRUCTION	2
45 #define	EXCP_BREAKPOINT			3
46 #define	EXCP_MISALIGNED_LOAD		4
47 #define	EXCP_FAULT_LOAD			5
48 #define	EXCP_MISALIGNED_STORE		6
49 #define	EXCP_FAULT_STORE		7
50 #define	EXCP_USER_ECALL			8
51 #define	EXCP_SUPERVISOR_ECALL		9
52 #define	EXCP_HYPERVISOR_ECALL		10
53 #define	EXCP_MACHINE_ECALL		11
54 #define	EXCP_INST_PAGE_FAULT		12
55 #define	EXCP_LOAD_PAGE_FAULT		13
56 #define	EXCP_STORE_PAGE_FAULT		15
57 #define	EXCP_INTR			(1ul << 63)
58 
59 #define	SSTATUS_UIE			(1 << 0)
60 #define	SSTATUS_SIE			(1 << 1)
61 #define	SSTATUS_UPIE			(1 << 4)
62 #define	SSTATUS_SPIE			(1 << 5)
63 #define	SSTATUS_SPIE_SHIFT		5
64 #define	SSTATUS_SPP			(1 << 8)
65 #define	SSTATUS_SPP_SHIFT		8
66 #define	SSTATUS_FS_SHIFT		13
67 #define	SSTATUS_FS_OFF			(0x0 << SSTATUS_FS_SHIFT)
68 #define	SSTATUS_FS_INITIAL		(0x1 << SSTATUS_FS_SHIFT)
69 #define	SSTATUS_FS_CLEAN		(0x2 << SSTATUS_FS_SHIFT)
70 #define	SSTATUS_FS_DIRTY		(0x3 << SSTATUS_FS_SHIFT)
71 #define	SSTATUS_FS_MASK			(0x3 << SSTATUS_FS_SHIFT)
72 #define	SSTATUS_XS_SHIFT		15
73 #define	SSTATUS_XS_MASK			(0x3 << SSTATUS_XS_SHIFT)
74 #define	SSTATUS_SUM			(1 << 18)
75 #define	SSTATUS32_SD			(1 << 63)
76 #define	SSTATUS64_SD			(1 << 31)
77 
78 #define	MSTATUS_UIE			(1 << 0)
79 #define	MSTATUS_SIE			(1 << 1)
80 #define	MSTATUS_HIE			(1 << 2)
81 #define	MSTATUS_MIE			(1 << 3)
82 #define	MSTATUS_UPIE			(1 << 4)
83 #define	MSTATUS_SPIE			(1 << 5)
84 #define	MSTATUS_SPIE_SHIFT		5
85 #define	MSTATUS_HPIE			(1 << 6)
86 #define	MSTATUS_MPIE			(1 << 7)
87 #define	MSTATUS_MPIE_SHIFT		7
88 #define	MSTATUS_SPP			(1 << 8)
89 #define	MSTATUS_SPP_SHIFT		8
90 #define	MSTATUS_HPP_MASK		0x3
91 #define	MSTATUS_HPP_SHIFT		9
92 #define	MSTATUS_MPP_MASK		0x3
93 #define	MSTATUS_MPP_SHIFT		11
94 #define	MSTATUS_FS_MASK			0x3
95 #define	MSTATUS_FS_SHIFT		13
96 #define	MSTATUS_XS_MASK			0x3
97 #define	MSTATUS_XS_SHIFT		15
98 #define	MSTATUS_MPRV			(1 << 17)
99 #define	MSTATUS_PUM			(1 << 18)
100 #define	MSTATUS_VM_MASK			0x1f
101 #define	MSTATUS_VM_SHIFT		24
102 #define	 MSTATUS_VM_MBARE		0
103 #define	 MSTATUS_VM_MBB			1
104 #define	 MSTATUS_VM_MBBID		2
105 #define	 MSTATUS_VM_SV32		8
106 #define	 MSTATUS_VM_SV39		9
107 #define	 MSTATUS_VM_SV48		10
108 #define	 MSTATUS_VM_SV57		11
109 #define	 MSTATUS_VM_SV64		12
110 #define	MSTATUS32_SD			(1 << 63)
111 #define	MSTATUS64_SD			(1 << 31)
112 
113 #define	MSTATUS_PRV_U			0	/* user */
114 #define	MSTATUS_PRV_S			1	/* supervisor */
115 #define	MSTATUS_PRV_H			2	/* hypervisor */
116 #define	MSTATUS_PRV_M			3	/* machine */
117 
118 #define	MIE_USIE	(1 << 0)
119 #define	MIE_SSIE	(1 << 1)
120 #define	MIE_HSIE	(1 << 2)
121 #define	MIE_MSIE	(1 << 3)
122 #define	MIE_UTIE	(1 << 4)
123 #define	MIE_STIE	(1 << 5)
124 #define	MIE_HTIE	(1 << 6)
125 #define	MIE_MTIE	(1 << 7)
126 
127 #define	MIP_USIP	(1 << 0)
128 #define	MIP_SSIP	(1 << 1)
129 #define	MIP_HSIP	(1 << 2)
130 #define	MIP_MSIP	(1 << 3)
131 #define	MIP_UTIP	(1 << 4)
132 #define	MIP_STIP	(1 << 5)
133 #define	MIP_HTIP	(1 << 6)
134 #define	MIP_MTIP	(1 << 7)
135 
136 #define	SIE_USIE	(1 << 0)
137 #define	SIE_SSIE	(1 << 1)
138 #define	SIE_UTIE	(1 << 4)
139 #define	SIE_STIE	(1 << 5)
140 #define	SIE_UEIE	(1 << 8)
141 #define	SIE_SEIE	(1 << 9)
142 
143 #define	MIP_SEIP	(1 << 9)
144 
145 /* Note: sip register has no SIP_STIP bit in Spike simulator */
146 #define	SIP_SSIP	(1 << 1)
147 #define	SIP_STIP	(1 << 5)
148 
149 #define	SATP_PPN_S	0
150 #define	SATP_PPN_M	(0xfffffffffff << SATP_PPN_S)
151 #define	SATP_ASID_S	44
152 #define	SATP_ASID_M	(0xffff << SATP_ASID_S)
153 #define	SATP_MODE_S	60
154 #define	SATP_MODE_M	(0xf << SATP_MODE_S)
155 #define	SATP_MODE_SV39	(8ULL << SATP_MODE_S)
156 #define	SATP_MODE_SV48	(9ULL << SATP_MODE_S)
157 
158 #define	XLEN		__riscv_xlen
159 #define	XLEN_BYTES	(XLEN / 8)
160 #define	INSN_SIZE	4
161 #define	INSN_C_SIZE	2
162 
163 #define	X_RA	1
164 #define	X_SP	2
165 #define	X_GP	3
166 #define	X_TP	4
167 #define	X_T0	5
168 #define	X_T1	6
169 #define	X_T2	7
170 #define	X_T3	28
171 
172 #define	RD_SHIFT	7
173 #define	RD_MASK		(0x1f << RD_SHIFT)
174 #define	RS1_SHIFT	15
175 #define	RS1_MASK	(0x1f << RS1_SHIFT)
176 #define	RS1_SP		(X_SP << RS1_SHIFT)
177 #define	RS2_SHIFT	20
178 #define	RS2_MASK	(0x1f << RS2_SHIFT)
179 #define	RS2_RA		(X_RA << RS2_SHIFT)
180 #define	IMM_SHIFT	20
181 #define	IMM_MASK	(0xfff << IMM_SHIFT)
182 
183 #define	RS2_C_SHIFT	2
184 #define	RS2_C_MASK	(0x1f << RS2_C_SHIFT)
185 #define	RS2_C_RA	(X_RA << RS2_C_SHIFT)
186 
187 #define	CSR_ZIMM(val)							\
188 	(__builtin_constant_p(val) && ((u_long)(val) < 32))
189 
190 #define	csr_swap(csr, val)						\
191 ({	if (CSR_ZIMM(val))  						\
192 		__asm __volatile("csrrwi %0, " #csr ", %1"		\
193 				: "=r" (val) : "i" (val));		\
194 	else 								\
195 		__asm __volatile("csrrw %0, " #csr ", %1"		\
196 				: "=r" (val) : "r" (val));		\
197 	val;								\
198 })
199 
200 #define	csr_write(csr, val)						\
201 ({	if (CSR_ZIMM(val)) 						\
202 		__asm __volatile("csrwi " #csr ", %0" :: "i" (val));	\
203 	else 								\
204 		__asm __volatile("csrw " #csr ", %0" ::  "r" (val));	\
205 })
206 
207 #define	csr_set(csr, val)						\
208 ({	if (CSR_ZIMM(val)) 						\
209 		__asm __volatile("csrsi " #csr ", %0" :: "i" (val));	\
210 	else								\
211 		__asm __volatile("csrs " #csr ", %0" :: "r" (val));	\
212 })
213 
214 #define	csr_clear(csr, val)						\
215 ({	if (CSR_ZIMM(val))						\
216 		__asm __volatile("csrci " #csr ", %0" :: "i" (val));	\
217 	else								\
218 		__asm __volatile("csrc " #csr ", %0" :: "r" (val));	\
219 })
220 
221 #define	csr_read(csr)							\
222 ({	u_long val;							\
223 	__asm __volatile("csrr %0, " #csr : "=r" (val));		\
224 	val;								\
225 })
226 
227 #if __riscv_xlen == 32
228 #define	csr_read64(csr)							\
229 ({	uint64_t val;							\
230 	uint32_t high, low;						\
231 	__asm __volatile("1: "						\
232 			 "csrr t0, " #csr "h\n"				\
233 			 "csrr %0, " #csr "\n"				\
234 			 "csrr %1, " #csr "h\n"				\
235 			 "bne t0, %1, 1b"				\
236 			 : "=r" (low), "=r" (high)			\
237 			 :						\
238 			 : "t0");					\
239 	val = (low | ((uint64_t)high << 32));				\
240 	val;								\
241 })
242 #else
243 #define	csr_read64(csr)		((uint64_t)csr_read(csr))
244 #endif
245 
246 #endif /* !_MACHINE_RISCVREG_H_ */
247