1 /*- 2 * Copyright (c) 2014 Andrew Turner 3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 4 * All rights reserved. 5 * 6 * Portions of this software were developed by SRI International and the 7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 9 * 10 * Portions of this software were developed by the University of Cambridge 11 * Computer Laboratory as part of the CTSRD Project, with support from the 12 * UK Higher Education Innovation Fund (HEIF). 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD$ 36 */ 37 38 #ifndef _MACHINE_PTE_H_ 39 #define _MACHINE_PTE_H_ 40 41 #ifndef LOCORE 42 typedef uint64_t pd_entry_t; /* page directory entry */ 43 typedef uint64_t pt_entry_t; /* page table entry */ 44 #endif 45 46 /* Level 0 table, 512GiB per entry */ 47 #define L0_SHIFT 39 48 49 /* Level 1 table, 1GiB per entry */ 50 #define L1_SHIFT 30 51 #define L1_SIZE (1 << L1_SHIFT) 52 #define L1_OFFSET (L1_SIZE - 1) 53 54 /* Level 2 table, 2MiB per entry */ 55 #define L2_SHIFT 21 56 #define L2_SIZE (1 << L2_SHIFT) 57 #define L2_OFFSET (L2_SIZE - 1) 58 59 /* Level 3 table, 4KiB per entry */ 60 #define L3_SHIFT 12 61 #define L3_SIZE (1 << L3_SHIFT) 62 #define L3_OFFSET (L3_SIZE - 1) 63 64 #define Ln_ENTRIES (1 << 9) 65 #define Ln_ADDR_MASK (Ln_ENTRIES - 1) 66 67 /* Bits 9:7 are reserved for software */ 68 #define PTE_SW_MANAGED (1 << 8) 69 #define PTE_SW_WIRED (1 << 7) 70 #define PTE_DIRTY (1 << 6) /* Virtual page is written */ 71 #define PTE_REF (1 << 5) /* Virtual page is referenced */ 72 #define PTE_VALID (1 << 0) /* Virtual page is valid */ 73 #define PTE_TYPE_S 1 74 #define PTE_TYPE_M (0xf << PTE_TYPE_S) 75 #define PTE_TYPE_PTR 0 76 #define PTE_TYPE_PTR_G 1 77 #define PTE_TYPE_SROURX 2 /* Supervisor read-only, user read-execute page. */ 78 #define PTE_TYPE_SRWURWX 3 /* Supervisor read-write, user read-write-execute page. */ 79 #define PTE_TYPE_SURO 4 /* Supervisor and user read-only page. */ 80 #define PTE_TYPE_SURW 5 /* Supervisor and user read-write page. */ 81 #define PTE_TYPE_SURX 6 /* Supervisor and user read-execute page. */ 82 #define PTE_TYPE_SURWX 7 /* Supervisor and User Read Write Execute */ 83 #define PTE_TYPE_SRO 8 /* Supervisor read-only page. */ 84 #define PTE_TYPE_SRW 9 /* Supervisor read-write page. */ 85 #define PTE_TYPE_SRX 10 /* Supervisor read-execute page. */ 86 #define PTE_TYPE_SRWX 11 /* Supervisor read-write-execute page. */ 87 #define PTE_TYPE_SRO_G 12 /* Supervisor read-only page--global mapping. */ 88 #define PTE_TYPE_SRW_G 13 /* Supervisor read-write page--global mapping. */ 89 #define PTE_TYPE_SRX_G 14 /* Supervisor read-execute page--global mapping. */ 90 #define PTE_TYPE_SRWX_G 15 /* Supervisor Read Write Execute Global */ 91 92 #define PTE_PPN0_S 10 93 #define PTE_PPN1_S 19 94 #define PTE_PPN2_S 28 95 #define PTE_PPN3_S 37 96 #define PTE_SIZE 8 97 98 #endif /* !_MACHINE_PTE_H_ */ 99 100 /* End of pte.h */ 101