xref: /freebsd/sys/riscv/include/intr.h (revision 63a938566d524836885917d95bd491aa4400b181)
1 /*-
2  * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
3  * All rights reserved.
4  *
5  * Portions of this software were developed by SRI International and the
6  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
8  *
9  * Portions of this software were developed by the University of Cambridge
10  * Computer Laboratory as part of the CTSRD Project, with support from the
11  * UK Higher Education Innovation Fund (HEIF).
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 1. Redistributions of source code must retain the above copyright
17  *    notice, this list of conditions and the following disclaimer.
18  * 2. Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the distribution.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32  * SUCH DAMAGE.
33  *
34  * $FreeBSD$
35  */
36 
37 #ifndef	_MACHINE_INTR_MACHDEP_H_
38 #define	_MACHINE_INTR_MACHDEP_H_
39 
40 struct trapframe;
41 
42 void riscv_init_interrupts(void);
43 int riscv_teardown_intr(void *);
44 int riscv_config_intr(u_int, enum intr_trigger, enum intr_polarity);
45 int riscv_setup_intr(const char *, driver_filter_t *, driver_intr_t *,
46     void *, int, int, void **);
47 void riscv_cpu_intr(struct trapframe *);
48 
49 typedef unsigned long * riscv_intrcnt_t;
50 
51 riscv_intrcnt_t riscv_intrcnt_create(const char *);
52 void riscv_intrcnt_setname(riscv_intrcnt_t, const char *);
53 
54 #ifdef SMP
55 void riscv_setup_ipihandler(driver_filter_t *);
56 void riscv_unmask_ipi(void);
57 #endif
58 
59 enum {
60 	IRQ_SOFTWARE_USER,
61 	IRQ_SOFTWARE_SUPERVISOR,
62 	IRQ_SOFTWARE_HYPERVISOR,
63 	IRQ_SOFTWARE_MACHINE,
64 	IRQ_TIMER_USER,
65 	IRQ_TIMER_SUPERVISOR,
66 	IRQ_TIMER_HYPERVISOR,
67 	IRQ_TIMER_MACHINE,
68 	IRQ_EXTERNAL_USER,
69 	IRQ_EXTERNAL_SUPERVISOR,
70 	IRQ_EXTERNAL_HYPERVISOR,
71 	IRQ_EXTERNAL_MACHINE,
72 #if 0
73 	/* lowRISC TODO */
74 	IRQ_COP,	/* lowRISC only */
75 	IRQ_UART,	/* lowRISC only */
76 #endif
77 	NIRQS
78 };
79 
80 #endif /* !_MACHINE_INTR_MACHDEP_H_ */
81