1 /*- 2 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #ifndef _MACHINE_CPU_H_ 36 #define _MACHINE_CPU_H_ 37 38 #ifndef LOCORE 39 #include <sys/_cpuset.h> 40 41 #include <machine/atomic.h> 42 #include <machine/cpufunc.h> 43 #include <machine/frame.h> 44 #endif 45 46 #define TRAPF_PC(tfp) ((tfp)->tf_sepc) 47 #define TRAPF_USERMODE(tfp) (((tfp)->tf_sstatus & SSTATUS_SPP) == 0) 48 49 #define cpu_getstack(td) ((td)->td_frame->tf_sp) 50 #define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 51 #define cpu_spinwait() /* nothing */ 52 #define cpu_lock_delay() DELAY(1) 53 54 /* 55 * Core manufacturer IDs, as reported by the mvendorid CSR. 56 */ 57 #define MVENDORID_UNIMPL 0x0 58 #define MVENDORID_SIFIVE 0x489 59 #define MVENDORID_THEAD 0x5b7 60 #define MVENDORID_SPACEMIT 0x710 61 62 /* 63 * Micro-architecture ID register, marchid. 64 * 65 * IDs for open-source implementations are allocated globally. Commercial IDs 66 * will have the most-significant bit set. 67 */ 68 #define MARCHID_UNIMPL 0x0 69 #define MARCHID_MSB (1ul << (XLEN - 1)) 70 #define MARCHID_OPENSOURCE(v) (v) 71 #define MARCHID_COMMERCIAL(v) (MARCHID_MSB | (v)) 72 #define MARCHID_IS_OPENSOURCE(m) (((m) & MARCHID_MSB) == 0) 73 74 /* 75 * Open-source marchid values. 76 * 77 * https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md 78 */ 79 #define MARCHID_UCB_ROCKET MARCHID_OPENSOURCE(1) 80 #define MARCHID_UCB_BOOM MARCHID_OPENSOURCE(2) 81 #define MARCHID_UCB_SPIKE MARCHID_OPENSOURCE(5) 82 #define MARCHID_UCAM_RVBS MARCHID_OPENSOURCE(10) 83 84 /* SiFive marchid values */ 85 #define MARCHID_SIFIVE_U7 MARCHID_COMMERCIAL(7) 86 #define MARCHID_SIFIVE_P5 MARCHID_COMMERCIAL(8) 87 88 /* SpacemiT marchid values */ 89 #define MARCHID_SPACEMIT_K1 MARCHID_COMMERCIAL(0x58000001) 90 91 /* 92 * MMU virtual-addressing modes. Support for each level implies the previous, 93 * so Sv48-enabled systems MUST support Sv39, etc. 94 */ 95 #define MMU_SV39 0x1 /* 3-level paging */ 96 #define MMU_SV48 0x2 /* 4-level paging */ 97 #define MMU_SV57 0x4 /* 5-level paging */ 98 99 #ifdef _KERNEL 100 #ifndef LOCORE 101 102 extern char btext[]; 103 extern char etext[]; 104 105 void cpu_halt(void) __dead2; 106 void cpu_reset(void) __dead2; 107 void fork_trampoline(void); 108 void identify_cpu(u_int cpu); 109 void printcpuinfo(u_int cpu); 110 cpuset_t hartmask_to_cpumask(const cpuset_t); 111 112 static __inline uint64_t 113 get_cyclecount(void) 114 { 115 116 return (rdcycle()); 117 } 118 119 #endif /* !LOCORE */ 120 #endif /* _KERNEL */ 121 122 #endif /* !_MACHINE_CPU_H_ */ 123